a Dual Precision,

Low Power BiFET Op Amp

AD648
FEATURES CONNECTION DIAGRAM
DC Performance
400 ␮A max Quiescent Current Plastic Mini-Dip (N) Package,
10 pA max Bias Current, Warmed Up (AD648B) Plastic SOIC (R) Package
1 ␮V max Offset Voltage (AD648B) and
10 ␮V/ⴗC max Drift (AD648B)
CERDIP (Q) Package
2 ␮V p-p Noise, 0.1 Hz to 10 Hz
AC Performance
1.8 V/␮s Slew Rate
1 MHz Unity Gain Bandwidth
Available in Plastic Mini-DIP, CERDIP, and Plastic SOIC
Packages
MIL-STD-883B Parts Available
Surface Mount (SOIC) Package Available in Tape and
Reel in Accordance with EIA-481A Standard
Single Version: AD548

PRODUCT DESCRIPTION –55°C to +125°C and the AD648T* grade is available pro-
The AD648 is a matched pair of low power, precision mono- cessed to MIL-STD-883B, Rev. C.
lithic operational amplifiers. It offers both low bias current The AD648 is available in an 8-lead plastic mini-DIP,
(10 pA max, warmed up) and low quiescent current (400 µA CERDIP, and SOIC.
max) and is fabricated with ion-implanted FET and laser wafer
trimming technologies. Input bias current is guaranteed over the *Not for new design, obsolete April 2002.
AD648’s entire common-mode voltage range.
PRODUCT HIGHLIGHTS
The economical J grade has a maximum guaranteed offset 1. A combination of low supply current, excellent dc and ac
voltage of less than 2 mV and an offset voltage drift of less than performance and low drift makes the AD648 the ideal op
20 µV/°C. This level of dc precision is achieved using Analog’s amp for high performance, low power applications.
laser wafer drift trimming process. The combination of low
quiescent current and low offset voltage drift minimizes changes 2. The AD648 is pin compatible with industry standard dual
in input offset voltage due to self-heating effects. Five grades are op amps such as the LF442, TL062, and AD642, enabling
offered over the commercial, industrial and military temperature designers to improve performance while achieving a reduc-
ranges. tion in power dissipation of up to 85%.
The AD648 is recommended for any dual supply op amp 3. Guaranteed low input offset voltage (2 mV max) and drift
application requiring low power and excellent dc and ac per- (20 µV/°C max) for the AD648J are achieved using Analog
formance. In applications such as battery-powered, precision Devices’ laser drift trimming technology.
instrument front ends and CMOS DAC buffers, the AD648’s 4. Analog Devices specifies each device in the warmed-up
excellent combination of low input offset voltage and drift, low condition, insuring that the device will meet its published
bias current, and low 1/f noise reduces output errors. High specifications in actual use.
common-mode rejection (82 dB, min on the “B” grade) and
5. Matching characteristics are excellent for all grades. The
high open-loop gain ensures better than 12-bit linearity in high
input offset voltage matching between amplifiers in the
impedance, buffer applications.
AD648J is within 2 mV.
The AD648 is pinned out in a standard dual op amp configura-
6. Crosstalk between amplifiers is less than –120 dB at 1 kHz.
tion and is available in seven performance grades. The AD648J
and AD648K are rated over the commercial temperature range
of 0°C to 70°C. The AD648 and AD648B are rated over the
industrial temperature range of –40°C to +85°C. The AD648S
and AD648T are rated over the military temperature range of

REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD648–SPECIFICATIONS (@ + 25ⴗC and V = ⴞ15 V dc, unless otherwise noted.)
S

AD648J/A/S AD648K/B/T
Model Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE1
Initial Offset 0.75 2.0 0.3 1.0
TMIN to TMAX 3.0/3.0/3.0 1.5/1.5/2.0 mV
vs. Temperature 20 10 µV/°C
vs. Supply 80 86 dB
vs. Supply, TMIN to TMAX 76/76/76 80 dB
Long-Term Offset Stability 15 15 µV/month
INPUT BIAS CURREN
Either Input,2 VCM = 0 5 20 3 10 pA
Either Input2 at TMAX, VCM = 0 0.45/1.3/20 0.25/0.65/10 nA
Max Input Bias Current Over
Common-Mode Voltage Range 30 15 pA
Offset Current, VCM = 0 5 10 2 5 pA
Offset Current at TMAX 0.25/0.7/10 0.15/0.35/5 nA
MATCHING CHARACTERISTICS3
Input Offset Voltage 1.0 2.0 0.5 1.0 mV
Input Offset Voltage TMIN to TMAX 3.0/3.0/3.0 1.5/1.5/2.0 mV
Input Offset Voltage vs. Temperature 8 5 µV/°C
Input Bias Current 10 5 pA
Crosstalk –120 –120 dB
INPUT IMPEDANCE
Differential 1 × 101 2储3 1 × 1012储3 Ω储pF
Common Mode 3 × 1012储3 3 × 1012储3 Ω储pF
INPUT VOLTAGE RANGE
Differential4 ± 20 ± 20 V
Common Mode ± 11 ± 12 ± 11 ± 12 V
Common-Mode Rejection
VCM = ± 10 V 76 82 dB
TMIN to TMAX 76/76/76 82 dB
VCM = ± 11 V 70 76 dB
TMIN to TMAX 70/70/70 76 dB
INPUT VOLTAGE NOISE
Voltage 0.1 Hz to 10 Hz 2 2 µV p-p
f = 10 Hz 80 80 nV/√Hz
f = 100 Hz 40 40 nV/√Hz
f = 1 kHz 30 30 nV/√Hz
f = 10 kHz 30 30 nV/√Hz
INPUT CURRENT NOISE
f = 1 kHz 1.8 1.8 fA/√Hz
FREQUENCY RESPONSE
Unity Gain, Small Signal 0.8 1.0 0.8 1.0 MHz
Full Power Response 30 30 kHz
Slew Rate, Unity Gain 1.0 1.8 1.0 1.8 V/µs
Settling Time to ± 0.01% 8 8 µs
OPEN-LOOP GAIN
VO = ± 10 V, RL ≥ 10 kΩ 300 1000 300 1000 V/mV
TMIN to TMAX, RL ≥ 10 kΩ 300/300/300 700 300 700 V/mV
VO = ± 10 V, RL ≥ 5 kΩ 150 500 150 500 V/mV
TMIN to TMAX, RL ≥ 5 kΩ 150/150/150 300 150 300 V/mV

–2– REV. E
 AD648
SPECIFICATIONS (Continued)
AD648J/A/S AD648K/B/T
Model Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Voltage @ RL ≥ 10 kΩ,
TMIN to TMAX ± 12/± 12/± 12 ± 13 ± 12 ± 13 V
Voltage @ RL ≥ 5 kΩ,
TMIN to TMAX ± 11/± 11/± 11 ± 12 ± 11 ± 12 V
Short Circuit Current 15 15 mA
POWER SUPPLY
Rated Performance ± 15 ± 15 V
Operating Range ± 4.5 ± 18 ± 4.5 ± 18 V
Quiescent Current (Both Amplifiers) 340 400 340 400 µA
TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0°C to 70°C) AD648J AD648K
Industrial (–40°C to +85°C) AD648A AD648B
Military (–55°C to +125°C) AD648S AD648T
PACKAGE OPTIONS
SOIC (R-8) AD648JR AD648KR
Plastic (N-8) AD648JN AD648KN
CERDIP (Q-8) AD648AQ5, AD648SQ5 AD648BQ5, AD648TQ/883B5
Tape and Reel AD648JR-REEL, AD648JR-REEL7 AD648KR-REEL, AD648KR-REEL7
NOTES
1
Input Offset Voltage specifications are guaranteed after five minutes of operation at T A = 25°C.
2
Bias Current specifications are guaranteed maximum at either input after five minutes of operation at T A = 25°C. For higher temperature, the current doubles
every 10°C.
3
Matching is defined as the difference between parameters of the two amplifiers.
4
Defined as voltages between inputs, such that neither exceeds ± 10 V from ground.
5
Not for new design. Obsolete April 2002.
Specifications subject to change without notice.

REV. E –3–
AD648
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (Q, H) . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD648J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD648A/B . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD648S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Thermal Characteristics:
8-Pin Plastic Package: θJA = 165°C/Watt
8-Pin CERDIP Package: θJC = 22°C/Watt; θJA = 110°C/Watt
8-Pin SOIC Package: θJC = 42°C/Wat; θJA = 160°C/Watt
3
For supply voltages less than ± 18 V, the absolute maximum input voltage is equal
to the supply voltage.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD648 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. E
 Typical Performance Characteristics— AD648

REV. E –5–
AD648

–6– REV. E
 AD648
APPLICATION NOTES
The AD648 is a pair of JFET-input op amps with a guaranteed
maximum IB of less than 10 pA, and offset and drift laser-
trimmed to 1.0 mV and 10 µV/°C, respectively (AD648B). AC
specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and
8 µs settling time for a 20 V step to ± 0.01%—all at a supply
current less than 400 µA. To capitalize on the device’s perfor-
mance, a number of error sources should be considered.
The minimal power drain and low offset drift of the AD648 Figure 22. Board Layout for Guarding Inputs
reduce self-heating or “warm-up” effects on input offset voltage,
making the AD648 ideal for on/off battery powered applica- INPUT PROTECTION
tions. The power dissipation due to the AD648’s 400 µA supply The AD648 is guaranteed to withstand input voltages equal to
current has a negligible effect on input current, but heavy out- the power supply potential. Exceeding the negative supply volt-
put loading will raise the chip temperature. Since a JFET’s age on either input will forward bias the substrate junction of
input current doubles for every 10°C rise in chip temperature, the chip. The induced current may destroy the amplifier due to
this can be a noticeable effect. excess heat.
The amplifier is designed to be functional with power supply Input protection is required in applications such as a flame
voltages as low as ± 4.5 V. It will exhibit a higher input offset detector in a gas chromatograph, where a very high potential
voltage than at the rated supply voltage of ± 15 V, due to power may be applied to the input terminals during a sensor fault
supply rejection effects. Common-mode range extends from 3 V condition. Figures 23a and 23b show simple current limiting
more positive than the negative supply to 1 V more negative schemes that can be used. RPROTECT should be chosen such that
than the positive supply. Designed to cleanly drive up to 10 kΩ the maximum overload current is 1.0 mA (for example 100 kΩ
and 100 pF loads, the AD648 will drive a 2 kΩ load with reduced for a 100 V overload).
open-loop gain.
Figure 21 shows the recommended crosstalk test circuit. A
typical value for crosstalk is –120 dB at 1 kHz.

Figure 23a. Input Protection of l-to-V Converter

Figure 21. Crosstalk Test Circuit

LAYOUT
To take full advantage of the AD648’s 10 pA max input current,
parasitic leakages must be kept below an acceptable level. The
practical limit of the resistance of epoxy or phenolic circuit
board material is between 1 × 1012 Ω and 3 × 1012 Ω. This can Figure 23b. Voltage Follower Input Protection Method
result in an additional leakage of 5 pA between an input of 0 V
and a –15 V supply line. Teflon or a similar low leakage material Figure 23b shows the recommended method for protecting a
(with a resistance exceeding 1017 Ω) should be used to isolate voltage follower from excessive currents due to high voltage
high impedance input lines from adjacent lines carrying high breakdown. The protection resistor, RP, limits the input current.
voltages. The insulator should be kept clean, since contaminants A nominal value of 100 kΩ will limit the input current to less
will degrade the surface resistance. than 1 mA with a 100 volt input voltage applied.
A metal guard completely surrounding the high impedance The stray capacitance between the summing junction and
nodes and driven by a voltage near the common-mode input ground will produce a high-frequency roll-off with a corner
potential can also be used to reduce some parasitic leakages. frequency equal to:
The guarding pattern in Figure 22 will reduce parasitic leakage 1
f corner =
due to finite board surface resistance; but it will not compensate 2 π RP Cstray
for a low volume resistivity board.
Accordingly, a 100 kΩ value for RP with a 3 pF Cstray will cause
a 3 dB corner frequency to occur at 531 kHz.

REV. E –7–
AD648
Figure 23c shows a diode clamp protection scheme for an I-to-V CMOS DAC’s output current to a voltage and provides the
converter using low leakage diodes. Because the diodes are necessary level shifting to achieve a bipolar voltage output. The
connected to the op amp’s summing junction, which is a virtual circuit operates with a 12-bit plus sign input code. The transfer
ground, their leakage contribution is minimal. function is shown in Figure 25.
The AD7592 is a fully protected dual CMOS SPDT switch with
data latches. R4 and R5 should match to within 0.01% to main-
tain the accuracy of the converter. A mismatch between R4 and
R5 introduces a gain error. Overall gain is trimmed by adjusting
RIN. The AD648’s low input offset voltage, low drift over tem-
perature, and excellent dynamics make it an attractive low
power output buffer.
Figure 23c. I-to-V Converter with Diode Input Protection The input offset voltage of the AD648 output amplifier results
in an output error voltage. This error voltage equals the input
Exceeding the negative common-mode range on either input offset voltage of the op amp times the noise gain of the amplifier.
terminal causes a phase reversal at the output, forcing the ampli-
fier output to the corresponding high or low state. Exceeding That is:
the negative common mode on both inputs simultaneously
VOS Output = VOS Input 1 + FB 
R
forces the output high. Exceeding the positive common-mode
RO
range on a single input does not cause a phase reversal; but if
both inputs exceed the limit, the output will be forced high. In RFB is the feedback resistor for the op amp, which is internal to
all cases, normal amplifier operation is resumed when input the DAC. RO is the DAC’s R-2R ladder output resistance. The
voltages are brought back within the common-mode range. value of RO is code dependent. This has the effect of changing
the offset error voltage at the amplifier’s output. An output
D/A CONVERTER BIPOLAR OUTPUT BUFFER amplifier with a sub millivolt input offset voltage is needed to
The circuit in Figure 24 provides 4 quadrant multiplication with preserve the linearity of the DAC’s transfer function.
a resolution of 12 bits. The AD648 is used to convert the AD7545

Figure 24. 12-Bit Plus Sign Magnitude D/A Converter

SIGN BIT BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT

0 1111 1111 1111 +VIN ⴛ (4095/4096)

0 0000 0000 0000 0V
1 0000 0000 0000 0V
1 1111 1111 1111 –VIN ⴛ (4095/4096)

NOTE
SIGN BIT AT “0“ CONNECTS THE NONINVERTING INPUT OF
A2 TO ANALOG COMMON

Figure 25. Sign Magnitude Code Table

–8– REV. E
 AD648
The AD648 in this configuration provides a 700 kHz small signal DUAL PHOTODIODE PREAMP
bandwidth and 1.8 V/µs typical slew rate. The 33 pF capacitor The performance of the dual photodiode preamp shown in
across the feedback resistor optimizes the circuit’s response. The Figure 27 is enhanced by the AD648’s low input current, input
oscilloscope photos in Figures 26a and 26b show small and voltage offset, and offset voltage drift. Each photodiode sources
large signal outputs of the circuit in Figure 24. Upper traces a current proportional to the incident light power on its surface.
show the input signal VIN. Lower traces are the resulting output RF converts the photodiode current to an output voltage equal
voltage with the DAC’s digital input set to all 1s. The circuit to RF × IS.
settles to ± 0.01% for a 20 V input step in 14 µs. An error budget illustrating the importance of low amplifier
input current, voltage offset, and offset voltage drift to minimize
output voltage errors can be developed by considering the
equivalent circuit for the small (0.2 mm2 area) photodiode
shown in Figure 27. The input current results in an error pro-
portional to the feedback resistance used. The amplifier’s offset
will produce an error proportional to the preamp’s noise gain
(1+RF/RSH), where RSH is the photodiode shunt resistance. The
amplifier’s input current will double with every 10°C rise in
temperature, and the photodiode’s shunt resistance halves with
every 10°C rise. The error budget in Figure 28 assumes a room
temperature photodiode RSH of 500 MΩ, and the maximum
input current and input offset voltage specs of an AD648C.
The capacitance at the amplifier’s negative input (the sum of the
photodiode’s shunt capacitance, the op amp’s differential input
capacitance, stray capacitance due to wiring, etc.) will cause a
Figure 26a. Response to ± 20 V p-p Reference Square rise in the preamp’s noise gain over frequency. This can result in
Wave excess noise over the bandwidth of interest. CF reduces the
noise gain “peaking” at the expense of signal bandwidth.

Figure 26b. Response to ± 100 mV p-p Reference Square

Wave
Figure 27. A Dual Photodiode Pre-Amp

TEMP RSH VOS IB

ⴗC (M⍀) (␮V) (1 + RF/RSH) VOS (pA) IBRF TOTAL
–25 15,970 150 151 ␮V 0.30 30 ␮V 181 ␮V
0 2,830 225 233 ␮V 2.26 262 ␮V 495 ␮V
+25 500 300 360 ␮V 10.00 1.0 mV 1.36 mV
+50 88.5 375 800 ␮V 56.6 5.6 mV 6.40 mV
+75 15.6 450 3.33 mV 320 32 mV 35.3 mV
+85 7.8 480 6.63 mV 640 64 mV 70.6 mV

Figure 28. Photodiode Pre-Amp Errors Over Temperature

REV. E –9–
AD648
INSTRUMENTATION AMPLIFIER the common-mode range, with a common-mode impedance of
The AD648J’s maximum input current of 20 pA per amplifier over 1 × 1012 Ω. The capacitors C1, C2, C3 and C4 compensate
makes it an excellent building block for the high input impedance for peaking in the gain over frequency which is caused by input
instrumentation amplifier shown in Figure 29. Total current capacitance.
drain for this circuit is under 600 µA. This configuration is To calibrate this circuit, first adjust trimmer R1 for common-
optimal for conditioning differential voltages from high imped- mode rejection with 10 V dc applied to the input pins. Next,
ance sources. adjust R2 for zero offset at VOUT with both inputs grounded.
The overall gain of the circuit is controlled by RG, resulting in Trim the circuit a second time for optimal
the following transfer function: performance.
VOUT (R3 + R4) The –3 dB small signal bandwidth for this low power instru-
= 1+
V IN RG mentation amplifier is 700 kHz for a gain of 1 and 10 kHz for a
gain of 100. The typical output slew rate is 1.8 V/µs.
Gains of 1 to 100 can be accommodated with gain nonlinearities
of less than 0.01%. The maximum input current is 30 pA over

Figure 29. Low Power Instrumentation Amplifier

–10– REV. E
 AD648
LOG RATIO AMPLIFIER which have a positive 3500 ppm/°C temperature coefficient.
Log ratio amplifiers are useful for a variety of signal conditioning The transfer function for the output voltage is:
applications, such as linearizing exponential transducer outputs VOUT = 1 V log10 (I2/I1)
and compressing analog signals having a wide dynamic range.
The AD648’s picoamp level input current and low input offset Frequency compensation is provided by R11, R12, C1, and C2.
voltage make it a good choice for the front end amplifier of the Small signal bandwidth is approximately 300 kHz at input cur-
log ratio circuit shown in Figure 30. This circuit produces an rents above 100 µA and will proportionally decrease with lower
output voltage equal to the log base 10 of the ratio of the input signal levels. D1, D2, R13, and R14 compensate for the effects
currents I1 and I2. Resistive inputs R1 and R2 are provided of the two logging transistors’ ohmic emitter resistance.
for voltage inputs. To trim this circuit, set the two input currents to 10 µA and
Input currents I1 and I2 set the collector currents of Q1 and Q2, adjust VOUT to zero by adjusting the potentiometer on A3. Then
a matched pair of logging transistors. Voltages at points A and B set I2 to 1 µA and adjust the scale factor such that the output
are developed according to the following familiar diode equation: voltage is 1 V by trimming potentiometer R10. Offset adjust-
ment for A1 and A2 is provided to increase the accuracy of the
VBE = (kT/q) ln (IC/IES) voltage inputs.
In this equation, k is Boltzmann’s constant, T is absolute This circuit ensures a 1% log conformance error over an input
temperature, q is an electron charge, and IES is the reverse current range of 300 pA to l mA, with low level accuracy limited
saturation current of the logging transistors. The difference of by the AD648’s input current. The low level input voltage accu-
these two voltages is taken by the subtractor section and scaled racy of this circuit is limited by the input offset voltage and drift
by a factor of approximately 16 by resistors R9, R10, and R8. of the AD648.
Temperature compensation is provided by resistors R8 and
R15,

Figure 30. Precision Log Ratio Amplifier

REV. E –11–
AD648
OUTLINE DIMENSIONS
Mini-DIP (N) Package CERDIP (Q) Package
Dimensions shown in inches and (millimeters) Dimensions shown in inches and (millimeters)

C00795–0–5/02(E)
8-Lead SOIC (R) Package
Dimensions shown in millimeters and (inches)

5.00 (0.1968)
4.80 (0.1890)

8 5
0.1574 (4.00) 6.20 (0.2440)
0.1497 (3.80) 1 4 5.80 (0.2284)

PIN 1
1.27 (0.0500) 0.50 (0.0196)
ⴛ 45ⴗ
BSC 0.25 (0.0099)
COPLANARITY 1.75 (0.0688)
0.25 (0.0098) 1.35 (0.0532)
0.10 (0.0040) 8ⴗ
SEATING 0.51 (0.0201) 0.25 (0.0098) 0ⴗ 1.27 (0.0500)
PLANE 0.33 (0.0130) 0.19 (0.0075) 0.41 (0.0160)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

PRINTED IN U.S.A.
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012 AA

Revision History
Location Page
Data Sheet changed from REV. C to REV. E.
Change to SOIC (R-8) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted AD648C column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Deleted METALIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted Metal Can from Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Deleted TO-99 (H) from OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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