Logic Design Lab Department of ECE
Experiment 1
Realization of Logic Gates and Familiarization of FPGAs
Aim:
The experiment aims to familiarize participants with a small FPGA board, covering:
(a) Understanding FPGA board components and interfaces.
(b) Developing Verilog modules for basic gates, synthesizing, implementing, and verifying their truth
tables on the FPGA.
(c) Verifying the universality and non-associativity of NAND and NOR gates by physically uploading
corresponding Verilog files to the FPGA board.
Theory:
A small FPGA board is a compact electronic device featuring a Field-Programmable Gate Array
(FPGA) chip. Designed for educational purposes, prototyping, and hands-on experimentation, these
boards provide users with a platform to learn digital design, programming languages like Verilog or
VHDL, and the synthesis and implementation of custom digital circuits. Equipped with interfaces
such as LEDs, buttons, and connectors, these boards allow individuals to program and modify the
FPGA to create and test specific logic circuits, making them valuable tools for learning and rapid
prototyping in the field of digital design.
I. Verilog Modules for basic gates:
a. NOT Gate
module NOT_gate_level(output Y, input A);
not (Y, A);
endmodule
Test bench
module NOT_Testbench;
reg A;
wire Y;
NOT_gate_level uut(Y,A);
initial begin
A = 0;#100; A = 1;#100; $finish;
end
endmodule
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Simulated Result
b. AND Gate
module AND_2(output Y, input A, B);
and(Y, A, B);
endmodule
Test Bench
module AND_testbench;
reg A;
reg B;
wire Y;
AND_2 uut (Y,A,B);
initial begin
A = 0;B = 0;#100;
A = 0;B = 1;#100;
A = 1;B = 0;#100;
A = 1;B = 1;#100;
$finish;
end
endmodule
Simulated Result
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
c. OR Gate
module OR_2_gate_level(output Y, input A, B);
or(Y, A, B);
endmodule
Test Bench
module test;
reg A;reg B;
wire Y;
OR_2_gate_level uut (Y,A,B);
initial begin
// Initialize Inputs
A = 0;B = 0;#100;
A = 0;B = 1;#100;
A = 1;B = 0;#100;
A = 1;B = 1;#100;
$finish;
end
endmodule
Simulated Result
II. Design of Basic Logic Gates using NAND Gate
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
module nand_universal(input a, b, output not_y, and_y, or_y);
// not_gate
nand (not_y, a, a);
//and_gate
wire out_1;
nand(out_1,a,b);
nand(and_y,out_1,out_1);
//or_gate
wire out_a,out_b;
nand(out_a,a,a);
nand(out_b,b,b);
nand(or_y,out_a,out_b);
endmodule
Test Bench
module check_ncv;
// Inputs
reg a;
reg b;
// Outputs
wire not_y;
wire and_y;
wire or_y;
// Instantiate the Unit Under Test (UUT)
nand_universal uut (a,b,not_y,and_y,or_y);
initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
$finish;
// Add stimulus here
end
endmodule
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Simulated Result
III. Design of Basic Logic Gates using NOR Gate
module nor_universal(input a, b, output not_y, and_y, or_y);
// not_gate
nor (not_y, a, a);
//and_gate
wire out_a,out_b;
nor(out_a,a,a);
nor(out_b,b,b);
nor(and_y,out_a,out_b);
//or_gate
wire out_1;
nor(out_1,a,b);
nand(or_y,out_1,out_1);
endmodule
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Test bench
module nor_test;
// Inputs
reg a;
reg b;
// Outputs
wire not_y;
wire and_y;
wire or_y;
// Instantiate the Unit Under Test (UUT)
nor_universal uut (a,b,not_y,and_y,or_y);
initial begin
// Initialize Inputs
a = 0;b = 0; #100;
a = 0;b = 1; #100;
a = 1;b = 0; #100;
a = 1;b = 1; #100;
$finish;
end
endmodule
Simulated Result
IV. Non associativity of NAND gates
module nand_non_associative(input a, b, c, output lhs, rhs);
// (a NAND b) NAND c
wire out_1_ab;
nand (out_1_ab, a, b);
nand (lhs, out_1_ab, c);
// a NAND (b NAND c)
wire out_2_bc;
nand (out_2_bc, b, c);
nand (rhs, a, out_2_bc);
endmodule
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Test bench
module check;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire lhs;
wire rhs;
// Instantiate the Unit Under Test (UUT)
nand_non_associative uut (a,b,c,lhs,rhs);
initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;
// Add stimulus here
end
endmodule
Simulated output
7
Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
V. Non associativity of NOR gates
module nor_non_associative(input a, b, c, output lhs, rhs);
// (a NOR b) NOR c
wire out_1_ab;
nor (out_1_ab, a, b);
nor (lhs, out_1_ab, c);
// a NOR (b NOR c)
wire out_2_bc;
nor (out_2_bc, b, c);
nor (rhs, a, out_2_bc);
endmodule
Test bench
module check;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire lhs;
wire rhs;
// Instantiate the Unit Under Test (UUT)
nor_non_associative uut (a,b,c,lhs,rhs);
initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;
$finish;
end
endmodule
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Simulated output
PROCEDURE
1. Write Verilog Code:
- Create Verilog code for your FPGA design.
2. Testbench Creation:
- Write a testbench in Verilog to simulate your design.
- The testbench includes stimulus generation and assertions to verify the correctness of your design.
3. Compile Verilog Code:
- Use a Verilog compiler to compile your Verilog code and the testbench.
4. Simulate Design:
- Run the simulation using the compiled files.
- Observe simulation results, waveforms, and any messages or errors reported by the simulation
tool.
5. Functional Verification:
- Verify that your design behaves as expected and meets functional requirements during simulation.
6. Create UCF File:
- Create a User Constraints File (UCF) to specify constraints such as pin assignments, I/O standards,
and others.
- Example UCF file (`your_design.ucf`):
# Pin assignments
NET "a" LOC = P13;
NET "b" LOC = P14;
NET "c" LOC = P15;
7. Synthesis:
- Use a synthesis tool to synthesize your Verilog code into a netlist.
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
8. Generate Bitstream:
- Generate the bitstream file that contains the configuration information for your FPGA.
9. Program FPGA:
- Use a programming tool to load the generated bitstream onto the FPGA.
- Ensure that the FPGA is connected to the correct pins as specified in the UCF file.
10. Verify on FPGA:
- Verify the functionality of your design on the actual FPGA hardware.
Result
Successfully developed Verilog modules for basic gates, verified their truth tables on the FPGA, and
confirmed the universality and non-associativity of NAND and NOR gates through physical
implementation and testing
10
Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Experiment 2
Adders in Verilog
Aim:
(a) To develop verilog modules for half adder in 3 modelling styles (dataflow/structural/behavioural).
(b) To develop verilog modules for full adder in structural modelling using half adder.
I. Half Adder
a. Gate Level Modelling
module half_adder( input a,b,output sum,carry);
xor(sum,a,b);
and(carry,a,b);
endmodule
b. Dataflow Modelling
module half_adder(input a,b,output sum,cout);
assign sum = a^b;
assign cout = a&b ;
endmodule
c. Behavioral Modelling
module half_adder(input a,b,output sum,carry);
assign {carry,sum} = a+b;
endmodule
11
Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Test bench
module check;
reg a,b;
wire sum;
wire carry;
half_adder uut (a,b,sum,carry);
initial begin a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
$finish;
end
endmodule
Simulated Result
II. FULL ADDER USING HALF ADDER (STRUCTURAL MODELING)
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
//full adder using half adder
module half_adder( input a,b,output sum,carry);
xor(sum,a,b);
and(carry,a,b);
endmodule
module full_adder(input a,b,cin,output sum,cout);
wire s1,c1,c2;
half_adder ha1(a,b,s1,c1);
half_adder ha2(s1,cin,sum,c2);
or(cout,c1,c2);
endmodule
Test bench
module full_adder_check;
reg a,b,cin;
wire sum,cout;
full_adder uut (a,b,cin,sum,cout);
initial begin
a = 0;b = 0;cin = 0; #100;
a = 0;b = 0;cin = 1; #100;
a = 0;b = 1;cin = 0; #100;
a = 0;b = 1;cin = 1; #100;
a = 1;b = 0;cin = 0; #100;
a = 1;b = 0;cin = 1; #100;
a = 1;b = 1;cin = 0; #100;
a = 1;b = 1;cin = 1; #100;
$finish;
end
endmodule
Simulated Result
13
Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
PROCEDURE
1. Write Verilog Code:
Create Verilog code for your FPGA design.
2. Testbench Creation:
Write a Verilog testbench for simulation, including stimulus generation and assertions.
3. Compile and Simulate:
Use a Verilog compiler to compile code and testbench.
Simulate the design, observing waveforms and results.
4. Functional Verification:
Verify design behavior and functionality during simulation.
5. Create UCF File:
Specify constraints in a User Constraints File (UCF) for pin assignments and I/O
standards.
//UCF
NET a LOC = P80 | IOSTANDARD = LVCMOS33; //input a
NET b LOC = P81 | IOSTANDARD = LVCMOS33; //input b
NET cin LOC = P82 | IOSTANDARD = LVCMOS33; //input cin
NET sum LOC = P22 | IOSTANDARD = LVCMOS33; //output sum driven to the port
NET cout LOC = P24 | IOSTANDARD = LVCMOS33; //output cout driven to the port
6. Synthesis:
Utilize a synthesis tool to generate a netlist from Verilog code.
7. Generate Bitstream:
Create a bitstream file containing FPGA configuration data.
8. Program FPGA:
Use a programming tool to load the bitstream onto the FPGA.
9. Verify on FPGA:
Result
Developed Verilog modules for a half adder in three modeling styles and also created Verilog modules for a
full adder using structural modeling with the assistance of the half adder.
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Experiment 3
Mux and Demux in Verilog
Aim:
To develop verilog modules for 4x1 MUX and 1x4 DEMUX
4 x 1 MUX
module mux_4to1 (input wire [3:0] data_in,input wire [1:0]
select,output reg data_out);
always @* begin
case (select)
2'b00: data_out = data_in[0];
2'b01: data_out = data_in[1];
2'b10: data_out = data_in[2];
2'b11: data_out = data_in[3];
endcase;
end
endmodule
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
Test bench
module mux_4_1;
reg [3:0] data_in;
reg [1:0] select;
wire data_out;
// Instantiate the Unit Under Test (UUT)
mux_4to1 uut (data_in,select, data_out);
initial begin
data_in = 4'b0001;select = 2'b00; #100;
data_in = 4'b0110;select = 2'b01; #100;
data_in = 4'b1001;select = 2'b10; #100;
data_in = 4'b1001;select = 2'b11; #100;
$finish;
end
endmodule
Simulated Output
1 x 4 DEMUX
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Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
module demux_1_4(output reg [3:0] Y, input [1:0] select, input din);
always @(Y, select) begin
case (select)
2'b00 : begin Y[0] = din; Y[3:1] = 0; end
2'b01 : begin Y[1] = din; Y[0] = 0; end
2'b10 : begin Y[2] = din; Y[1:0] = 0; end
2'b11 : begin Y[3] = din; Y[2:0] = 0; end
endcase
end
endmodule
Testbench
module testbench;
reg [1:0] select; reg din;wire [3:0] Y;
demux_1_4 uut (Y,select,din);
initial begin
select = 00;din = 1;#100;
select = 01;din = 1;#100;
select = 10;din = 1;#100;
select = 11;din = 1;#100;
$finish;
end
endmodule
Simulated Result
17
Bishop Jerome Institute, Kollam
Logic Design Lab Department of ECE
PROCEDURE
1. Write Verilog Code:
Create Verilog code for your FPGA design.
2. Testbench Creation:
Write a Verilog testbench for simulation, including stimulus generation and assertions.
3. Compile and Simulate:
Use a Verilog compiler to compile code and testbench.
Simulate the design, observing waveforms and results.
4. Functional Verification:
Verify design behavior and functionality during simulation.
5. Create UCF File:
Specify constraints in a User Constraints File (UCF) for pin assignments and I/O
standards.
//UCF
NET select[0] LOC = P80 | IOSTANDARD = LVCMOS33;
NET select[1] LOC = P81 | IOSTANDARD = LVCMOS33;
NET din LOC = P17 | IOSTANDARD = LVCMOS33;
NET Y[0] LOC = P22 | IOSTANDARD = LVCMOS33;
NET Y[1] LOC = P24 | IOSTANDARD = LVCMOS33;
NET Y[2] LOC = P27 | IOSTANDARD = LVCMOS33;
NET Y[3] LOC = P30 | IOSTANDARD = LVCMOS33;
6. Synthesis:
Utilize a synthesis tool to generate a netlist from Verilog code.
7. Generate Bitstream:
Create a bitstream file containing FPGA configuration data.
8. Program FPGA:
Use a programming tool to load the bitstream onto the FPGA.
9. Verify on FPGA:
Result
Developed Verilog modules for a 4x1 Multiplexer and 1x4 Demultiplexer.
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Bishop Jerome Institute, Kollam
