The 8085 Microprocessor

2.1 Features of 8085

The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1976. It is a popular

and widely used microprocessor for educational purposes and in various embedded
systems due to its simplicity and robust design. Here are some of its key features:

8-bit Microprocessor: It can process 8 bits of data at a time.

N-MOS Technology: Manufactured using N-MOS (N-type Metal-Oxide-

Semiconductor) technology.

40-pin DIP: It comes in a 40-pin Dual In-line Package.

+5V Power Supply: Requires a single +5V power supply.

3.03 MHz Clock Speed: Operates at a maximum clock frequency of 3.03 MHz.

16-bit Address Bus: It has a 16-bit address bus, allowing it to address up to 2^16
= 65,536 bytes (64 KB) of memory.

8-bit Data Bus: It has an 8-bit data bus.

Multiplexed Address/Data Bus: The lower 8 bits of the address bus (A0-A7) are
multiplexed with the data bus (AD0-AD7) to reduce the number of pins.

Six General-Purpose Registers: It has six 8-bit general-purpose registers (B, C, D,

E, H, L) that can be combined to form three 16-bit register pairs (BC, DE, HL) for
16-bit operations.

Accumulator: An 8-bit register used for arithmetic and logical operations.

Flag Register: An 8-bit register that indicates the status of various operations
(Sign, Zero, Auxiliary Carry, Parity, Carry flags).

Program Counter (PC): A 16-bit register that stores the memory address of the
next instruction to be fetched.

Stack Pointer (SP): A 16-bit register that points to the top of the stack in
memory.
 Interrupts: Supports five hardware interrupts (TRAP, RST 7.5, RST 6.5, RST 5.5,
INTR) and one software interrupt (RST n).

Serial I/O Ports: Includes two serial I/O pins (SID and SOD) for serial data
communication.

Control and Status Signals: Provides various control and status signals for
communication with peripheral devices and memory.

2.2 Pin description and internal architecture

Pin Description

The 8085 microprocessor is a 40-pin IC (Integrated Circuit) package. Each pin has a
specific function for power supply, clock signals, address/data bus, control signals,
interrupt signals, and serial I/O signals. The pins can be broadly categorized as follows:

Address Bus (A8-A15): These are the higher-order 8 bits of the address bus. They
are unidirectional and are used to send the most significant 8 bits of the memory
address or I/O address.

Multiplexed Address/Data Bus (AD0-AD7): These are the lower-order 8 bits of

the address bus and the 8 bits of the data bus. They are time-multiplexed,
meaning they carry address information during the first clock cycle (T1) of a
machine cycle and data information during the subsequent clock cycles (T2 and
T3).

Control and Status Signals:

ALE (Address Latch Enable): A positive-going pulse that indicates that the
AD0-AD7 lines are carrying address information. This signal is used to latch
the lower-order address bits.

RD (Read): A low-active signal that indicates that the selected memory or

I/O device is to be read.

WR (Write): A low-active signal that indicates that data is to be written to

the selected memory or I/O device.

IO/M (Input/Output/Memory): A status signal that indicates whether the

current operation is an I/O operation (high) or a memory operation (low).
 S0, S1 (Status Signals): These signals indicate the type of machine cycle
being executed (e.g., opcode fetch, memory read, memory write, I/O read,
I/O write).

READY: An input signal used by slower peripheral devices to synchronize

with the microprocessor. If READY is low, the microprocessor waits.

HOLD: An input signal used by external devices (e.g., DMA controllers) to

request control of the address and data buses.

HLDA (Hold Acknowledge): An output signal that indicates the

microprocessor has received the HOLD request and will relinquish control
of the buses.

Interrupt Signals:
TRAP: Non-maskable interrupt, highest priority.

RST 7.5, RST 6.5, RST 5.5: Maskable interrupts with decreasing priority.

INTR (Interrupt Request): A general-purpose maskable interrupt input.

INTA (Interrupt Acknowledge): An output signal that acknowledges an

INTR request.

Serial I/O Signals:

SID (Serial Input Data): Input pin for serial data.

SOD (Serial Output Data): Output pin for serial data.

Power Supply and Clock Signals:

VCC: +5V power supply.

VSS: Ground reference.

X1, X2: Crystal or RC network connection for the internal clock generator.

CLK OUT: Clock output signal, used to synchronize peripheral devices.

RESET IN: An input signal to reset the microprocessor.

RESET OUT: An output signal that indicates the microprocessor is being

reset.

Internal Architecture

The internal architecture of the 8085 microprocessor is designed to efficiently execute

instructions and manage data flow. It consists of several functional units:
Arithmetic and Logic Unit (ALU): Performs arithmetic operations (addition,
subtraction, increment, decrement) and logical operations (AND, OR, XOR, NOT,
compare, rotate). The ALU works with 8-bit data.

Registers: The 8085 has several registers for storing data and addresses:
Accumulator (A): An 8-bit register used for most arithmetic and logical
operations. The result of an operation is usually stored in the accumulator.

General-Purpose Registers (B, C, D, E, H, L): Six 8-bit registers that can be

used individually or paired up (BC, DE, HL) to perform 16-bit operations.
The HL pair is often used as a memory pointer.

Temporary Registers (W, Z): 8-bit registers used internally by the

microprocessor and not accessible to the programmer. They are used to
hold data during instruction execution.

Stack Pointer (SP): A 16-bit register that holds the address of the top of the
stack in memory. The stack is used for temporary storage of data and return
addresses during subroutine calls and interrupts.

Program Counter (PC): A 16-bit register that stores the memory address of
the next instruction to be fetched from memory. It is automatically
incremented after each instruction fetch.

Instruction Register: An 8-bit register that holds the opcode of the

instruction currently being executed.

Instruction Decoder and Machine Cycle Encoding: Decodes the instruction

fetched from memory and generates the necessary control signals for the
internal operations of the microprocessor.

Timing and Control Unit: Generates the necessary timing and control signals for
all internal and external operations of the microprocessor. It controls the flow of
data between the CPU and peripheral devices.

Interrupt Control: Manages the interrupt requests from external devices and
internal events, prioritizing them and directing the microprocessor to the
appropriate interrupt service routine.

Serial I/O Control: Handles serial data communication through the SID and SOD
pins.

Address Buffer and Data/Address Buffer: These buffers are used to drive the
address and data buses, respectively, providing the necessary current to external
devices.
Here is a diagram illustrating the internal architecture of the 8085 Microprocessor:

And here is the pin diagram of the 8085 Microprocessor:

2.3 Instruction and data formats

An instruction is a command given to the microprocessor to perform a specific

operation on data. In the 8085 microprocessor, instructions are typically composed of
an opcode (operation code) and an operand. The opcode specifies the operation to be
performed, while the operand provides the data or the address of the data on which
the operation is to be performed.

Instruction Formats

8085 instructions can be classified into three formats based on their byte size:

1. One-Byte Instructions: These instructions consist only of an opcode. They do

not require any additional data or address bytes. The opcode itself contains all
the necessary information for the microprocessor to execute the instruction.
These instructions typically operate on internal registers.

Examples:
MOV A, B (Move the content of register B to register A)

ADD B (Add the content of register B to the Accumulator)

HLT (Halt the processor)

2. Two-Byte Instructions: These instructions consist of an opcode followed by an

8-bit data byte or an 8-bit address. The second byte provides the immediate data
or the lower 8 bits of a memory address.

Examples:
MVI A, 32H (Move immediate data 32H to Accumulator)

ADI 05H (Add immediate data 05H to Accumulator)

OUT 20H (Output data from Accumulator to port 20H)

3. Three-Byte Instructions: These instructions consist of an opcode followed by a

16-bit data word or a 16-bit address. The second and third bytes provide the 16-
bit immediate data or the 16-bit memory address. The lower-order byte of the
16-bit value is typically stored in the second byte, and the higher-order byte in
the third byte.

Examples:
 LXI H, 2050H (Load immediate 16-bit data 2050H into HL register
pair)

LDA 4000H (Load Accumulator with the content of memory location

4000H)

JMP 1234H (Jump to memory location 1234H)

Data Formats

The 8085 microprocessor primarily handles 8-bit data. Data can be represented in
various formats:

Binary: Data is stored and processed in binary (0s and 1s). For example, an 8-bit
data can range from 00000000B to 11111111B.

Hexadecimal: For convenience, 8-bit data is often represented in hexadecimal

format (00H to FFH). Each hexadecimal digit represents 4 bits, so two
hexadecimal digits represent an 8-bit byte.

Decimal: While not directly used by the microprocessor for internal operations,
decimal values are used by programmers for input and output, which are then
converted to binary or hexadecimal.

When dealing with 16-bit operations (e.g., addresses, or data in register pairs like BC,
DE, HL, SP, PC), the 8085 handles them as two 8-bit bytes. The convention is typically
little-endian, where the lower-order byte is stored at the lower memory address and
the higher-order byte at the higher memory address.

2.4 Addressing modes and instruction set

Addressing Modes

Addressing modes refer to the different ways in which the microprocessor can specify
the operand (data or memory address) for an instruction. The 8085 microprocessor
supports five addressing modes:

1. Immediate Addressing Mode: In this mode, the operand is a part of the

instruction itself. The data is provided immediately after the opcode.

Example: MVI A, 32H (Move immediate value 32H to Accumulator)

 2. Register Addressing Mode: In this mode, the operand is located in one of the
internal general-purpose registers of the microprocessor. The instruction
specifies the register containing the data.

Example: MOV A, B (Move the content of register B to register A)

3. Direct Addressing Mode: In this mode, the instruction contains the 16-bit
memory address of the operand. The microprocessor directly accesses the
specified memory location to fetch or store data.

Example: LDA 4000H (Load Accumulator with the content of memory

location 4000H)

4. Register Indirect Addressing Mode: In this mode, the instruction specifies a

register pair (HL, BC, or DE) that contains the 16-bit memory address of the
operand. The microprocessor uses the content of the register pair as a pointer to
the memory location.

Example: MOV A, M (Move the content of the memory location pointed to

by HL pair to Accumulator)

5. Implicit/Implied Addressing Mode: In this mode, the operand is implicitly

specified by the instruction itself. The instruction operates on data that is already
known to the microprocessor, typically the Accumulator.

Example: CMA (Complement Accumulator)

Example: RAL (Rotate Accumulator Left)

Instruction Set

The 8085 instruction set is a collection of commands that the microprocessor

understands and can execute. It comprises 246 instructions, categorized into five
functional groups:

1. Data Transfer Group: These instructions are used to move data between
registers, memory, and I/O devices. They do not affect the contents of the source
location.

Examples: MOV , MVI , LDA , STA , LHLD , SHLD , XCHG , PUSH , POP , IN ,
OUT .
 2. Arithmetic Group: These instructions perform arithmetic operations like
addition, subtraction, increment, and decrement on 8-bit data. They affect the
flag register.

Examples: ADD , ADC , SUB , SBB , INR , DCR , DAA .

3. Logical Group: These instructions perform logical operations like AND, OR, XOR,
compare, and rotate. They also affect the flag register.

Examples: ANA , ORA , XRA , CMP , CPI , RLC , RRC , RAL , RAR .

4. Branch Control Group: These instructions alter the normal sequential flow of
program execution. They include jumps, calls, returns, and restarts.

Examples: JMP , CALL , RET , RST , PCHL .

5. Stack, I/O, and Machine Control Group: These instructions deal with stack
operations, input/output operations, and controlling the microprocessor's state.

Examples: PUSH , POP , IN , OUT , HLT , NOP , DI , EI , SIM , RIM .

2.5 Assembly programming examples

2.5.1 Basic data transfer operations

Data transfer instructions are fundamental to any microprocessor programming,

allowing the movement of data between registers, memory locations, and I/O ports.
These instructions simply copy the data from a source to a destination without altering
the content of the source.

Here are some common 8085 assembly programming examples for basic data transfer
operations:

1. Moving 8-bit data to a register (MVI - Move Immediate)

This instruction moves an 8-bit immediate data into a specified register.

MVI A, 45H ; Move immediate value 45H into Accumulator (Register A)

MVI B, 0AH ; Move immediate value 0AH into Register B
MVI C, FFH ; Move immediate value FFH into Register C
2. Moving data between registers (MOV - Move)

This instruction copies the content of one register to another register.

MOV B, A ; Copy content of Accumulator (A) to Register B

MOV C, H ; Copy content of Register H to Register C
MOV L, D ; Copy content of Register D to Register L

3. Loading data from a memory location to the Accumulator (LDA - Load

Accumulator Direct)

This instruction loads the content of a specified 16-bit memory address into the
Accumulator.

LDA 2000H ; Load content of memory location 2000H into Accumulator

4. Storing data from the Accumulator to a memory location (STA - Store

Accumulator Direct)

This instruction stores the content of the Accumulator into a specified 16-bit memory
address.

STA 2050H ; Store content of Accumulator into memory location 2050H

5. Loading 16-bit data to a register pair (LXI - Load Register Pair Immediate)

This instruction loads a 16-bit immediate data into a specified register pair.

LXI H, 3000H ; Load immediate value 3000H into HL register pair (H=30H,
L=00H)
LXI B, 1234H ; Load immediate value 1234H into BC register pair (B=12H,
C=34H)

6. Moving data from memory to a register using register indirect addressing (MOV
R, M)

This instruction copies the content of the memory location pointed to by the HL
register pair into a specified register.

LXI H, 2000H ; Load HL with memory address 2000H

MOV B, M ; Copy content of memory location 2000H (pointed by HL) to
Register B
7. Moving data from a register to memory using register indirect addressing (MOV
M, R)

This instruction copies the content of a specified register into the memory location
pointed to by the HL register pair.

LXI H, 2000H ; Load HL with memory address 2000H

MOV M, C ; Copy content of Register C to memory location 2000H (pointed
by HL)

8. Exchanging the contents of HL with DE register pair (XCHG - Exchange)

This instruction exchanges the 16-bit contents of the HL register pair with the DE
register pair.

XCHG ; Exchange contents of HL and DE register pairs

These examples demonstrate the basic data transfer capabilities of the 8085
microprocessor, which are essential for moving data around within the system to
facilitate various operations.

2.5.2 Basic arithmetic and logical operations

Arithmetic and logical operations are core functions of any microprocessor, enabling it
to perform calculations and manipulate data at the bit level. The 8085 provides a set of
instructions for these operations, primarily using the Accumulator as one of the
operands and often storing the result back into the Accumulator. These operations
also affect the flag register, indicating the status of the result.

Here are some common 8085 assembly programming examples for basic arithmetic
and logical operations:

Arithmetic Operations

1. Addition (ADD - Add Register to Accumulator, ADI - Add Immediate to

Accumulator)

ADD R : Adds the content of register R to the Accumulator. The result is stored in
the Accumulator.
 ADI data : Adds the 8-bit immediate data to the Accumulator. The result is
stored in the Accumulator.

MVI A, 05H ; Accumulator = 05H

MVI B, 03H ; Register B = 03H
ADD B ; A = A + B (05H + 03H = 08H). Accumulator now holds 08H.

MVI A, 10H ; Accumulator = 10H

ADI 05H ; A = A + 05H (10H + 05H = 15H). Accumulator now holds 15H.

2. Addition with Carry (ADC - Add Register with Carry to Accumulator, ACI - Add
Immediate with Carry to Accumulator)

ADC R : Adds the content of register R and the Carry flag (CY) to the Accumulator.
The result is stored in the Accumulator.

ACI data : Adds the 8-bit immediate data and the Carry flag (CY) to the
Accumulator. The result is stored in the Accumulator.

MVI A, 0FFH ; Accumulator = FFH

MVI B, 01H ; Register B = 01H
ADD B ; A = FFH + 01H = 00H, CY = 1 (Carry flag is set)
ADC C ; Assuming C = 00H, A = A + C + CY (00H + 00H + 01H = 01H).
Accumulator now holds 01H.

3. Subtraction (SUB - Subtract Register from Accumulator, SUI - Subtract

Immediate from Accumulator)

SUB R : Subtracts the content of register R from the Accumulator. The result is
stored in the Accumulator.

SUI data : Subtracts the 8-bit immediate data from the Accumulator. The result
is stored in the Accumulator.

MVI A, 0AH ; Accumulator = 0AH

MVI B, 03H ; Register B = 03H
SUB B ; A = A - B (0AH - 03H = 07H). Accumulator now holds 07H.

MVI A, 20H ; Accumulator = 20H

SUI 05H ; A = A - 05H (20H - 05H = 1BH). Accumulator now holds 1BH.

4. Subtraction with Borrow (SBB - Subtract Register with Borrow from

Accumulator, SBI - Subtract Immediate with Borrow from Accumulator)

SBB R : Subtracts the content of register R and the Borrow (Carry) flag (CY) from
the Accumulator. The result is stored in the Accumulator.
 SBI data : Subtracts the 8-bit immediate data and the Borrow (Carry) flag (CY)
from the Accumulator. The result is stored in the Accumulator.

MVI A, 05H ; Accumulator = 05H

MVI B, 0AH ; Register B = 0AH
SUB B ; A = 05H - 0AH = FB (2's complement), CY = 1 (Borrow flag is set)
SBI 01H ; A = A - 01H - CY (FBH - 01H - 01H = F9H). Accumulator now holds
F9H.

5. Increment (INR - Increment Register or Memory, INX - Increment Register Pair)

INR R : Increments the content of register R by 1.

INX RP : Increments the content of the specified register pair by 1.

MVI B, 05H ; Register B = 05H

INR B ; B = B + 1 (05H + 01H = 06H). Register B now holds 06H.

LXI H, 1000H ; HL = 1000H

INX H ; HL = HL + 1 (1000H + 0001H = 1001H). HL now holds 1001H.

6. Decrement (DCR - Decrement Register or Memory, DCX - Decrement Register

Pair)

DCR R : Decrements the content of register R by 1.

DCX RP : Decrements the content of the specified register pair by 1.

MVI C, 0AH ; Register C = 0AH

DCR C ; C = C - 1 (0AH - 01H = 09H). Register C now holds 09H.

LXI D, 2000H ; DE = 2000H

DCX D ; DE = DE - 1 (2000H - 0001H = 1FFFH). DE now holds 1FFFH.

Logical Operations

1. Logical AND (ANA - AND Register with Accumulator, ANI - AND Immediate with
Accumulator)

ANA R : Performs a bitwise AND operation between the content of register R and
the Accumulator. The result is stored in the Accumulator.

ANI data : Performs a bitwise AND operation between the 8-bit immediate data
and the Accumulator. The result is stored in the Accumulator.
 MVI A, 0F0H ; Accumulator = 11110000B
MVI B, 00FH ; Register B = 00001111B
ANA B ; A = A AND B (11110000B AND 00001111B = 00000000B = 00H).
Accumulator now holds 00H.

MVI A, 0A5H ; Accumulator = 10100101B

ANI 0F0H ; A = A AND F0H (10100101B AND 11110000B = 10100000B = A0H).
Accumulator now holds A0H.

2. Logical OR (ORA - OR Register with Accumulator, ORI - OR Immediate with

Accumulator)

ORA R : Performs a bitwise OR operation between the content of register R and

the Accumulator. The result is stored in the Accumulator.

ORI data : Performs a bitwise OR operation between the 8-bit immediate data
and the Accumulator. The result is stored in the Accumulator.

MVI A, 0F0H ; Accumulator = 11110000B

MVI B, 00FH ; Register B = 00001111B
ORA B ; A = A OR B (11110000B OR 00001111B = 11111111B = FFH).
Accumulator now holds FFH.

MVI A, 0A5H ; Accumulator = 10100101B

ORI 00FH ; A = A OR 0FH (10100101B OR 00001111B = 10101111B = AFH).
Accumulator now holds AFH.

3. Logical XOR (XRA - XOR Register with Accumulator, XRI - XOR Immediate with
Accumulator)

XRA R : Performs a bitwise XOR operation between the content of register R and
the Accumulator. The result is stored in the Accumulator.

XRI data : Performs a bitwise XOR operation between the 8-bit immediate data
and the Accumulator. The result is stored in the Accumulator.

MVI A, 0F0H ; Accumulator = 11110000B

MVI B, 0F0H ; Register B = 11110000B
XRA B ; A = A XOR B (11110000B XOR 11110000B = 00000000B = 00H).
Accumulator now holds 00H.

MVI A, 0A5H ; Accumulator = 10100101B

XRI 0FFH ; A = A XOR FFH (10100101B XOR 11111111B = 01011010B = 5AH).
Accumulator now holds 5AH.

4. Compare (CMP - Compare Register with Accumulator, CPI - Compare Immediate

with Accumulator)
 CMP R : Compares the content of register R with the Accumulator. The
comparison is done by internally subtracting R from A, and the flags are set
accordingly (Zero, Carry, Sign, Parity, Auxiliary Carry). The contents of A and R
remain unchanged.

CPI data : Compares the 8-bit immediate data with the Accumulator. Flags are
set based on the comparison.

MVI A, 05H ; Accumulator = 05H

MVI B, 03H ; Register B = 03H
CMP B ; A > B, so Carry flag = 0, Zero flag = 0

MVI A, 05H ; Accumulator = 05H

CPI 05H ; A = 05H, so Zero flag = 1, Carry flag = 0

5. Rotate (RLC - Rotate Accumulator Left, RRC - Rotate Accumulator Right, RAL -
Rotate Accumulator Left through Carry, RAR - Rotate Accumulator Right through
Carry)

These instructions shift the bits of the Accumulator to the left or right, often involving
the Carry flag.

RLC : Rotates the Accumulator left by one bit. The most significant bit (MSB)
moves to the Carry flag and also to the least significant bit (LSB).

RRC : Rotates the Accumulator right by one bit. The least significant bit (LSB)
moves to the Carry flag and also to the most significant bit (MSB).

RAL : Rotates the Accumulator left by one bit through the Carry flag. The MSB
moves to the Carry flag, and the Carry flag's old value moves to the LSB.

RAR : Rotates the Accumulator right by one bit through the Carry flag. The LSB
moves to the Carry flag, and the Carry flag's old value moves to the MSB.

MVI A, 81H ; Accumulator = 10000001B, Carry = 0

RLC ; A = 00000011B, Carry = 1

MVI A, 81H ; Accumulator = 10000001B, Carry = 0

RRC ; A = 11000000B, Carry = 1

MVI A, 81H ; Accumulator = 10000001B, Carry = 0

RAL ; A = 00000010B, Carry = 1

MVI A, 81H ; Accumulator = 10000001B, Carry = 0

RAR ; A = 01000000B, Carry = 1
These arithmetic and logical instructions form the basis for performing complex
calculations and data manipulations in 8085 assembly language programming.

2.5.3 Conditions and loops

Conditional statements and loops are essential programming constructs that allow a
program to make decisions and repeat sequences of instructions, respectively. In 8085
assembly language, these are primarily implemented using conditional and
unconditional jump instructions, which alter the flow of program execution based on
the status of the flag register.

Conditional Statements (Decision Making)

Conditional statements in 8085 are implemented using conditional jump instructions.

These instructions check the status of specific flags (Zero, Carry, Sign, Parity) and jump
to a new memory location only if the condition is met. If the condition is not met, the
program continues to the next instruction in sequence.

Here are some common conditional jump instructions:

JZ (Jump if Zero): Jumps if the Zero flag (Z) is set (Z=1), meaning the previous
operation resulted in zero.

JNZ (Jump if Not Zero): Jumps if the Zero flag (Z) is reset (Z=0), meaning the
previous operation resulted in a non-zero value.

JC (Jump if Carry): Jumps if the Carry flag (CY) is set (CY=1), meaning the
previous operation generated a carry or borrow.

JNC (Jump if No Carry): Jumps if the Carry flag (CY) is reset (CY=0), meaning the
previous operation did not generate a carry or borrow.

JP (Jump if Plus): Jumps if the Sign flag (S) is reset (S=0), meaning the result is
positive.

JM (Jump if Minus): Jumps if the Sign flag (S) is set (S=1), meaning the result is
negative.

JPE (Jump if Parity Even): Jumps if the Parity flag (P) is set (P=1), meaning the
result has an even number of set bits.

JPO (Jump if Parity Odd): Jumps if the Parity flag (P) is reset (P=0), meaning the
result has an odd number of set bits.
Example: Check if a number is zero

MVI A, 00H ; Load Accumulator with 00H

CPI 00H ; Compare Accumulator with 00H (sets Zero flag if A=00H)
JZ IS_ZERO ; Jump to IS_ZERO if A is 00H
JMP NOT_ZERO ; Jump to NOT_ZERO if A is not 00H

IS_ZERO: ; Code to execute if number is zero

; ...
HLT

NOT_ZERO: ; Code to execute if number is not zero

; ...
HLT

Example: Check if a number is greater than or equal to another

MVI A, 05H ; Load Accumulator with 05H

MVI B, 03H ; Load Register B with 03H
SUB B ; Subtract B from A (A = A - B). This sets flags.
JNC A_GTE_B ; Jump if no carry (A >= B)
JMP A_LT_B ; Jump if carry (A < B)

A_GTE_B: ; Code to execute if A >= B

; ...
HLT

A_LT_B: ; Code to execute if A < B

; ...
HLT

Loops

Loops are used to repeat a block of instructions a certain number of times or until a
specific condition is met. In 8085 assembly, loops are typically implemented using a
counter and conditional jump instructions.

1. Simple Count-Based Loop

This type of loop uses a register as a counter, which is decremented in each iteration.
The loop continues until the counter reaches zero.

Example: Sum of first N natural numbers (N stored in C register)

 MVI C, 05H ; Initialize counter (N=5)
MVI A, 00H ; Initialize Accumulator (sum) to 0

LOOP_START:
ADD C ; Add current value of C to Accumulator
DCR C ; Decrement counter
JNZ LOOP_START ; Jump back to LOOP_START if C is not zero

HLT ; Halt after loop completes (Accumulator holds sum)

Explanation:

The MVI C, 05H instruction initializes the counter register C with the value 5.
This means the loop will execute 5 times. (Note: This example sums 5, 4, 3, 2, 1
into A, not 1 to 5 directly. For summing 1 to N, a different approach would be
needed, perhaps adding 1 in each iteration and incrementing a separate
counter.)

MVI A, 00H initializes the Accumulator to 0, where the sum will be stored.

Inside the LOOP_START , ADD C adds the current value of C to the Accumulator.

DCR C decrements the counter C.

JNZ LOOP_START checks the Zero flag. If C is not zero, the program jumps back to
LOOP_START to continue the loop. If C becomes zero, the loop terminates.

2. Loop with a Delay

Loops can also be used to create time delays in programs. This is often done by
running a loop for a specific number of iterations, where each iteration takes a known
amount of time.

Example: Simple Delay Loop

DELAY_LOOP:
MVI B, FFH ; Load B with a large value (inner loop counter)
INNER_LOOP:
DCR B ; Decrement B
JNZ INNER_LOOP ; Loop until B becomes zero

DCR C ; Decrement outer loop counter (if used)

JNZ DELAY_LOOP ; Loop until C becomes zero

RET ; Return from delay subroutine

Explanation:
 This example shows a nested loop structure. The INNER_LOOP decrements
register B until it becomes zero. This creates a short delay.

The DELAY_LOOP decrements register C (assuming C was initialized before calling

this routine) and then repeats the INNER_LOOP . This creates a longer delay.

The total delay depends on the initial values loaded into B and C, and the clock
frequency of the 8085.

These examples illustrate how conditional jumps and loops are fundamental for
controlling program flow and implementing iterative processes in 8085 assembly
language.

2.5.4 Array and table processing

Array and table processing are common tasks in programming, involving operations
on sequences of data stored in contiguous memory locations. In 8085 assembly
language, these tasks are typically handled using register pairs (especially HL) as
memory pointers, combined with looping and indexing techniques.

Array Processing

Arrays are collections of data elements of the same type, stored in consecutive
memory locations. Processing an array often involves iterating through its elements to
perform operations like summation, searching, sorting, or finding the largest/smallest
element.

Example 1: Sum of N 8-bit numbers in an array

This program adds N 8-bit numbers stored in a memory array and stores the sum in a
designated memory location. Assume the number of elements (N) is at memory
location 2000H , and the array starts from 2001H .
 ORG 2000H ; Origin of the program

START:
LXI H, 2001H ; Load HL with the starting address of the array
MOV C, M ; Move the number of elements (N) from 2000H to Register C
(counter)
INR L ; Increment L to point to the first element of the array
(2001H)
MVI A, 00H ; Initialize Accumulator (sum) to 00H
MVI B, 00H ; Initialize Register B (carry) to 00H

LOOP_SUM:
ADD M ; Add the content of memory pointed by HL to Accumulator
JNC NEXT_ELEMENT ; If no carry, jump to next element
INR B ; If carry, increment Register B (carry counter)

NEXT_ELEMENT:
INR L ; Increment L to point to the next element
DCR C ; Decrement element counter
JNZ LOOP_SUM ; If C is not zero, continue loop

STA 2050H ; Store the sum (Accumulator) at 2050H

MOV A, B ; Move the final carry to Accumulator
STA 2051H ; Store the carry at 2051H

HLT ; Halt the processor

Explanation:

LXI H, 2001H sets the HL register pair to point to the first element of the array.

MOV C, M loads the count of elements (N) into register C, which acts as a loop
counter.

MVI A, 00H and MVI B, 00H initialize the sum (Accumulator) and carry
(Register B) to zero.

The LOOP_SUM iterates N times. In each iteration:

ADD M adds the current array element to the Accumulator.

JNC NEXT_ELEMENT checks for carry. If a carry occurs, INR B increments

the carry counter.

INR L moves the HL pointer to the next array element.

DCR C decrements the element counter.

JNZ LOOP_SUM continues the loop until all elements are processed.

Finally, the 16-bit sum (Accumulator and Register B) is stored in memory

locations 2050H and 2051H .
Example 2: Searching for a number in an array

This program searches for a specific 8-bit number in an array. If found, it sets a flag;
otherwise, it clears the flag. Assume the number to search is at 2000H , array size at
2001H , and array starts from 2002H . Result flag (00H for not found, FFH for found) at
2050H .

ORG 2000H

START:
LDA 2000H ; Load the number to search into Accumulator
MOV B, A ; Copy it to Register B
LXI H, 2001H ; Load HL with address of array size
MOV C, M ; Move array size to Register C (counter)
INR L ; Point HL to the first element of the array (2002H)

SEARCH_LOOP:
MOV A, M ; Load current array element into Accumulator
CMP B ; Compare with the number to search (in Register B)
JZ FOUND ; If equal, jump to FOUND
INR L ; Increment HL to next element
DCR C ; Decrement counter
JNZ SEARCH_LOOP; If C is not zero, continue search

NOT_FOUND:
MVI A, 00H ; Set flag to 00H (Not Found)
STA 2050H ; Store flag
JMP END_PROG ; Jump to end

FOUND:
MVI A, FFH ; Set flag to FFH (Found)
STA 2050H ; Store flag

END_PROG:
HLT ; Halt the processor

Table Processing

Table processing often involves looking up values in a predefined table based on an

index or a key. This is particularly useful for tasks like code conversions (e.g., BCD to 7-
segment display codes) or function lookups.

Example: 7-segment display code lookup

This program takes a BCD digit (0-9) and finds its corresponding 7-segment display
code from a lookup table. Assume the BCD digit is at 2000H , and the 7-segment codes
table starts at 2100H . The result will be stored at 2050H .
 ORG 2000H

SEVEN_SEG_TABLE:
DB 3FH ; Code for 0
DB 06H ; Code for 1
DB 5BH ; Code for 2
DB 4FH ; Code for 3
DB 66H ; Code for 4
DB 6DH ; Code for 5
DB 7DH ; Code for 6
DB 07H ; Code for 7
DB 7FH ; Code for 8
DB 6FH ; Code for 9

START:
LDA 2000H ; Load BCD digit into Accumulator (e.g., 05H)
MOV L, A ; Move BCD digit to L register (acts as offset)
MVI H, 21H ; Set H register to the high byte of table start address
(2100H)
; Now HL points to 2100H + offset (e.g., 2105H for BCD 05H)

MOV A, M ; Load the 7-segment code from the table into Accumulator
STA 2050H ; Store the 7-segment code at 2050H

HLT ; Halt the processor

Explanation:

The SEVEN_SEG_TABLE defines the 7-segment codes for digits 0-9. DB (Define
Byte) is an assembler directive to store byte data.

LDA 2000H fetches the BCD digit (e.g., 05H) into the Accumulator.

MOV L, A copies this digit to the L register. Since the table starts at 2100H , and
each entry is 1 byte, the BCD digit can directly serve as an offset from the table's
starting address.

MVI H, 21H sets the H register to the high byte of the table's base address.
Together, HL now forms the effective address of the desired 7-segment code (e.g.,
2100H + 05H = 2105H ).

MOV A, M fetches the byte from the memory location pointed to by HL (which is
the 7-segment code) into the Accumulator.

STA 2050H stores the fetched 7-segment code to the result location.

These examples illustrate how arrays and tables can be effectively processed in 8085
assembly language using indexing and direct memory access techniques.
2.5.5 8-bit and 16-bit multiplication and division operations

The 8085 microprocessor does not have dedicated hardware instructions for
multiplication and division. These operations must be implemented using software
routines, typically by repeatedly applying addition/subtraction and bit shifting
operations. This makes multiplication and division more complex and time-consuming
compared to basic arithmetic operations.

8-bit Multiplication

8-bit multiplication can be performed using repeated addition. For example, to

multiply A by B, you can add A to itself B times.

Example: Multiply two 8-bit numbers (A x B)

Assume the multiplicand is in memory location 2000H and the multiplier is in 2001H .
The 16-bit result (product) will be stored in 2050H (lower byte) and 2051H (higher
byte).

ORG 2000H

START:
LDA 2000H ; Load multiplicand into Accumulator
MOV B, A ; Move multiplicand to Register B
LDA 2001H ; Load multiplier into Accumulator
MOV C, A ; Move multiplier to Register C (counter)

MVI A, 00H ; Initialize Accumulator (lower byte of product) to 00H

MVI D, 00H ; Initialize Register D (higher byte of product) to 00H

LOOP_MUL:
ADD B ; Add multiplicand (B) to Accumulator (A)
JNC NO_CARRY ; If no carry, jump to NO_CARRY
INR D ; If carry, increment Register D (higher byte of product)

NO_CARRY:
DCR C ; Decrement multiplier (counter)
JNZ LOOP_MUL ; If C is not zero, continue loop

STA 2050H ; Store lower byte of product (Accumulator) at 2050H

MOV A, D ; Move higher byte of product (D) to Accumulator
STA 2051H ; Store higher byte of product at 2051H

HLT ; Halt the processor

Explanation:

The program initializes the Accumulator (A) and Register D to 0. A will hold the
lower 8 bits of the product, and D will hold the higher 8 bits (carry).
 The LOOP_MUL repeatedly adds the multiplicand (stored in B) to the Accumulator.
The number of additions is controlled by the multiplier (stored in C).

Each time an addition results in a carry, Register D is incremented, effectively

accumulating the higher byte of the product.

After the loop completes, the 16-bit product is formed by the contents of D
(higher byte) and A (lower byte).

16-bit Multiplication

16-bit multiplication is significantly more complex and typically involves breaking

down the 16-bit numbers into 8-bit parts and performing multiple 8-bit multiplications
and additions, similar to long multiplication taught in elementary school. This often
requires careful handling of carries and partial products. Due to its complexity and
length, a full 16-bit multiplication routine is often implemented as a subroutine.

Conceptual Approach for 16-bit Multiplication (HL x DE):

Let the two 16-bit numbers be HL (H: high byte, L: low byte) and DE (D: high byte, E:
low byte).

1. Multiply L by E (8-bit x 8-bit). This gives a 16-bit product.

2. Multiply L by D (8-bit x 8-bit). This gives a 16-bit product.

3. Multiply H by E (8-bit x 8-bit). This gives a 16-bit product.

4. Multiply H by D (8-bit x 8-bit). This gives a 16-bit product.

5. Align and add the partial products, considering their positional values (e.g., L*D
result needs to be shifted left by 8 bits before adding).

This process involves many ADD , ADC , RLC / RRC (for shifting), and DAD (Double Add)
instructions, along with careful management of intermediate results in register pairs
and memory.

8-bit Division

8-bit division can be performed using repeated subtraction. To divide a dividend by a

divisor, you repeatedly subtract the divisor from the dividend and count how many
times you can subtract before the dividend becomes less than the divisor. The count is
the quotient, and the remaining value is the remainder.
Example: Divide two 8-bit numbers (Dividend / Divisor)

Assume the dividend is in memory location 2000H and the divisor is in 2001H . The
quotient will be stored in 2050H and the remainder in 2051H .

ORG 2000H

START:
LDA 2000H ; Load dividend into Accumulator
MOV B, A ; Move dividend to Register B
LDA 2001H ; Load divisor into Accumulator
MOV C, A ; Move divisor to Register C

MVI A, 00H ; Initialize Accumulator (quotient) to 00H

CHECK_DIVISOR:
CMP C ; Compare dividend (B) with divisor (C)
JC END_DIV ; If B < C, division is complete (jump if carry)

LOOP_DIV:
SUB C ; Subtract divisor (C) from dividend (A)
INR A ; Increment quotient (Accumulator)
MOV B, A ; Update dividend in B
JMP CHECK_DIVISOR ; Check again

END_DIV:
MOV A, B ; Move remainder (from B) to Accumulator
STA 2051H ; Store remainder at 2051H
MOV A, D ; Move quotient (from D) to Accumulator (assuming D holds
quotient)
STA 2050H ; Store quotient at 2050H

HLT ; Halt the processor

Note: The above division example is a simplified conceptual one. A more robust
division algorithm would involve careful handling of the dividend and quotient
registers, and ensuring the correct remainder is left in the accumulator. A common
approach is to use the Accumulator for the current dividend, and a separate register
for the quotient, incrementing the quotient each time a subtraction is successful. The
loop continues until the dividend is less than the divisor. The final value in the
Accumulator is the remainder, and the count is the quotient.

16-bit Division

Similar to 16-bit multiplication, 16-bit division is implemented through software

routines involving repeated 8-bit subtractions and shifts. It's a more involved process,
often requiring a dedicated subroutine to handle the 16-bit dividend and divisor, and
to produce a 16-bit quotient and 8-bit remainder. This typically involves using register
pairs (like HL and DE) to hold the 16-bit numbers and carefully managing the flags and
intermediate results.

Conceptual Approach for 16-bit Division (HL / C):

To divide a 16-bit number (HL) by an 8-bit number (C), one common method is to
repeatedly subtract the divisor from the higher byte of the dividend, then combine the
remainder with the lower byte and continue the process. This is analogous to manual
long division.

Implementing full 16-bit by 16-bit division in 8085 assembly is a significant

programming challenge due to the lack of native support and the need for meticulous
bit manipulation and carry handling. It typically involves a combination of shifting,
comparing, and subtracting operations over many instructions.

2.5.6 Data conversion: bcd to binary, binary to bcd

Data conversion routines are crucial in microprocessor systems, especially when

interfacing with human-readable inputs/outputs (which often use BCD - Binary Coded
Decimal) and internal processing (which uses binary). The 8085 does not have direct
instructions for BCD-to-binary or binary-to-BCD conversion, so these are implemented
through software algorithms.

BCD to Binary Conversion

BCD (Binary Coded Decimal) represents each decimal digit with its 4-bit binary
equivalent. For example, decimal 23 is represented as 0010 0011 in BCD. To convert a
two-digit BCD number to its binary equivalent, you can multiply the higher BCD digit
by 10 (0AH in hex) and add the lower BCD digit.

Example: Convert a two-digit BCD number to Binary

Assume the two-digit BCD number is stored in memory location 2000H (e.g., 23H for
decimal 23). The binary result will be stored in 2050H .
 ORG 2000H

START:
LDA 2000H ; Load BCD number (e.g., 23H) into Accumulator
MOV B, A ; Copy BCD number to Register B

ANI 0F0H ; Mask lower nibble (A = 20H for 23H)

RRC ; Rotate right (A = 10H)
RRC ; Rotate right (A = 08H)
RRC ; Rotate right (A = 04H)
RRC ; Rotate right (A = 02H) - Higher BCD digit
MOV C, A ; Store higher BCD digit in Register C

MOV A, B ; Get original BCD number back to Accumulator (A = 23H)

ANI 0FH ; Mask higher nibble (A = 03H) - Lower BCD digit
MOV D, A ; Store lower BCD digit in Register D

MVI E, 0AH ; Load 10 (0AH) into Register E

MVI A, 00H ; Initialize Accumulator for multiplication

MULTIPLY_LOOP:
ADD C ; Add higher BCD digit (C) to Accumulator
DCR E ; Decrement counter (E)
JNZ MULTIPLY_LOOP ; Loop 10 times

ADD D ; Add lower BCD digit (D) to Accumulator

STA 2050H ; Store binary result at 2050H

HLT ; Halt the processor

Explanation:

The program first separates the two BCD digits. The higher nibble (e.g., 2 from
23H) is isolated and rotated to become a single digit. The lower nibble (e.g., 3
from 23H) is also isolated.

The higher BCD digit is then multiplied by 10 using a repeated addition loop.

Finally, the lower BCD digit is added to the result of the multiplication to get the
final binary value.

Binary to BCD Conversion

Converting a binary number to BCD is generally more complex than the reverse. A
common method is the

double-dabble algorithm (also known as shift-and-add-3). This algorithm involves

shifting the binary number left and, before each shift, checking if any BCD digit
(nibble) is greater than 4. If it is, 3 is added to that nibble to correct the BCD
representation.
Example: Convert an 8-bit Binary number to BCD

Assume the 8-bit binary number is stored in memory location 2000H (e.g., 0FH for
decimal 15). The BCD result will be stored in 2050H (lower BCD digit) and 2051H
(higher BCD digit).

ORG 2000H

START:
LDA 2000H ; Load binary number into Accumulator (e.g., 0FH)
MOV B, A ; Copy binary number to Register B

MVI C, 08H ; Initialize bit counter to 8 (for 8-bit binary)

MVI D, 00H ; Initialize Register D (higher BCD digit) to 00H
MVI E, 00H ; Initialize Register E (lower BCD digit) to 00H

LOOP_BCD:
MOV A, E ; Move lower BCD digit to Accumulator
ADD A ; Double (shift left) lower BCD digit
DAA ; Decimal Adjust Accumulator
MOV E, A ; Store back to lower BCD digit

MOV A, D ; Move higher BCD digit to Accumulator

ADD A ; Double (shift left) higher BCD digit
DAA ; Decimal Adjust Accumulator
MOV D, A ; Store back to higher BCD digit

MOV A, B ; Get binary number to Accumulator

RAL ; Rotate Accumulator Left through Carry (shifts MSB to Carry)
MOV B, A ; Store back to binary number

JNC NO_ADD_3 ; If no carry, skip adding 3

INR E ; If carry, add 1 to lower BCD digit (effectively adding 3 to
the BCD value)

NO_ADD_3:
DCR C ; Decrement bit counter
JNZ LOOP_BCD ; Loop until all 8 bits are processed

MOV A, E ; Move lower BCD digit to Accumulator

STA 2050H ; Store lower BCD digit at 2050H
MOV A, D ; Move higher BCD digit to Accumulator
STA 2051H ; Store higher BCD digit at 2051H

HLT ; Halt the processor

Explanation (Simplified Double-Dabble for 8-bit to 2-digit BCD):

This example is a simplified approach. A more accurate and general double-dabble

algorithm for binary to BCD conversion involves:

1. Initialize BCD digits to zero.

 2. Repeat 8 times (for an 8-bit binary number): a. If any BCD digit (nibble) is >= 5,
add 3 to it. b. Shift the entire BCD number left by one bit. c. Shift the binary
number left by one bit, and the MSB of the binary number becomes the LSB of
the BCD number.

The provided example attempts to implement a variation of this, where ADD A and
DAA are used to handle the doubling and decimal adjustment. The RAL instruction
shifts the binary number and its MSB into the Carry flag, which is then used to adjust
the BCD digits. This process is repeated for each bit of the binary number.

Implementing a full and robust binary to BCD conversion, especially for larger binary
numbers (e.g., 16-bit), requires careful management of multiple BCD digits and precise
application of the double-dabble algorithm. Due to the complexity, such routines are
often implemented as subroutines.

2.6 Interrupts: interrupt pins, interrupt priorities,

types of interrupts, interrupt instruction, processing
sequence of interrupt

Interrupts are mechanisms that allow external devices or internal events to

temporarily suspend the normal execution of a program and transfer control to a
special routine called an Interrupt Service Routine (ISR). After the ISR is executed, the
microprocessor returns to the point where it was interrupted and resumes normal
program execution. Interrupts are crucial for handling asynchronous events and
managing I/O operations efficiently.

Interrupt Pins

The 8085 microprocessor has five hardware interrupt pins:

1. TRAP: This is a non-maskable interrupt, meaning it cannot be disabled by

software. It has the highest priority among all interrupts. It is edge and level
triggered, making it suitable for critical events like power failure.

2. RST 7.5: This is a maskable interrupt. It is edge-triggered, meaning it responds to

a positive-going pulse. It has the second highest priority.
 3. RST 6.5: This is a maskable interrupt. It is level-triggered, meaning it responds to
a high logic level. It has the third highest priority.

4. RST 5.5: This is a maskable interrupt. It is level-triggered, meaning it responds to

a high logic level. It has the fourth highest priority.

5. INTR (Interrupt Request): This is a general-purpose, maskable interrupt. It is

level-triggered. It has the lowest priority among the hardware interrupts. When
an INTR signal is received, the 8085 responds with an INTA (Interrupt
Acknowledge) signal, prompting the interrupting device to provide the opcode of
the RST (Restart) instruction or a CALL instruction.

Interrupt Priorities

The 8085 microprocessor has a fixed priority scheme for its hardware interrupts. In
case multiple interrupts occur simultaneously, the one with the higher priority is
serviced first. The priority order from highest to lowest is:

TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR

Types of Interrupts

Interrupts in the 8085 can be broadly classified into two main types:

1. Hardware Interrupts: These are triggered by external signals applied to the

interrupt pins of the microprocessor. The 8085 has five hardware interrupt pins as
described above (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR).

2. Software Interrupts: These are triggered by executing specific instructions

within the program. The 8085 has eight software interrupt instructions, RST 0 to
RST 7 . When an RST n instruction is executed, the program counter (PC) is
saved on the stack, and the program jumps to a fixed memory location (vector
address) calculated as n * 8 . These are vectored interrupts.

Interrupts can also be classified as:

Maskable Interrupts: These interrupts can be enabled or disabled by software

instructions ( EI and DI ). RST 7.5, RST 6.5, RST 5.5, and INTR are maskable
interrupts.
 Non-Maskable Interrupts: These interrupts cannot be disabled by software.
TRAP is a non-maskable interrupt.

Vectored Interrupts: In vectored interrupts, the microprocessor automatically

knows the address of the ISR to jump to after receiving the interrupt. TRAP, RST
7.5, RST 6.5, and RST 5.5 are vectored interrupts, as they have predefined vector
addresses. Software interrupts (RST 0-7) are also vectored.

Non-Vectored Interrupts: In non-vectored interrupts, the interrupting device

must provide the address of the ISR. INTR is a non-vectored interrupt, as the
interrupting device needs to supply an RST or CALL instruction during the INTA
cycle.

Interrupt Instructions

Several instructions are used to control and manage interrupts in the 8085:

EI (Enable Interrupts): This instruction enables the maskable interrupts (RST

7.5, RST 6.5, RST 5.5, INTR). It sets the Interrupt Enable (IE) flip-flop.

DI (Disable Interrupts): This instruction disables all maskable interrupts. It

resets the Interrupt Enable (IE) flip-flop.

SIM (Set Interrupt Mask): This instruction is used to mask (disable) or unmask
(enable) individual RST 7.5, RST 6.5, and RST 5.5 interrupts. It also controls the
Serial Output Data (SOD) pin.

RIM (Read Interrupt Mask): This instruction reads the current status of the
interrupt masks and the pending interrupts into the Accumulator. It also reads
the Serial Input Data (SID) pin.

RST n (Restart): These are software interrupt instructions (RST 0 to RST 7). When
executed, they save the current PC on the stack and jump to a specific vector
address ( n * 8 ).

Processing Sequence of Interrupt

The general sequence of events when an interrupt occurs in the 8085 is as follows:

1. Interrupt Request: An external device asserts an interrupt signal on one of the

hardware interrupt pins (e.g., RST 7.5, INTR) or a software RST instruction is
executed.
 2. Interrupt Check: The 8085 continuously checks for pending interrupt requests
during the execution of each instruction (specifically, at the second T-state of the
last machine cycle of every instruction).

3. Interrupt Acknowledge (for INTR): If an INTR request is detected and interrupts

are enabled, the 8085 sends out an INTA (Interrupt Acknowledge) signal. This
signal prompts the external device to place an RST instruction's opcode (or a
CALL instruction) on the data bus.

4. Save Program Counter: The current content of the Program Counter (PC), which
points to the next instruction to be executed, is automatically pushed onto the
stack. This ensures that the microprocessor can return to the main program after
servicing the interrupt.

5. Load Interrupt Vector Address:

For TRAP, RST 7.5, RST 6.5, RST 5.5, and software RST instructions, the
microprocessor automatically loads the corresponding vector address into
the PC.

For INTR, the RST or CALL instruction provided by the interrupting device
is fetched and executed, which then directs the PC to the ISR address.

6. Execute ISR: The microprocessor starts executing the Interrupt Service Routine
(ISR) located at the vector address. The ISR contains the code to handle the
specific event that caused the interrupt.

7. Return from Interrupt: The ISR typically ends with a RET (Return) instruction.
This instruction pops the previously saved PC value from the stack back into the
Program Counter.

8. Resume Main Program: The microprocessor resumes execution of the main

program from where it was interrupted.

This interrupt mechanism allows the 8085 to respond efficiently to external events
without constantly polling devices, thus improving system responsiveness and overall
performance.