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Program

The document contains various Verilog modules and testbenches for digital circuits, including multiplexers, odd/even detectors, full adders, palindrome detectors, binary to gray converters, decoders, priority encoders, and magnitude comparators. Each section provides the module definition followed by a testbench that initializes inputs, monitors outputs, and generates simulation waveforms. The document illustrates different modeling techniques such as gate-level, dataflow, and structural modeling in Verilog.

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43 views16 pages

Program

The document contains various Verilog modules and testbenches for digital circuits, including multiplexers, odd/even detectors, full adders, palindrome detectors, binary to gray converters, decoders, priority encoders, and magnitude comparators. Each section provides the module definition followed by a testbench that initializes inputs, monitors outputs, and generates simulation waveforms. The document illustrates different modeling techniques such as gate-level, dataflow, and structural modeling in Verilog.

Uploaded by

karan2004sss
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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#2x1 mux:

Test: DUT
module mux21_test; module mux21(A,B,S,Y);
reg A,B,S;
wire Y; input A,B,S;
output Y;
mux21 dut(.A(A),.B(B),.S(S),.Y(Y)); assign Y=(A&(~S))|(B&S);

initial begin endmodule


A=1'b0;B=1'b0;S=1'b0;
#5 A=1'b0;B=1'b0;S=1'b1;
#5 A=1'b0;B=1'b1;S=1'b0;
#5 A=1'b0;B=1'b1;S=1'b1;
#5 A=1'b1;B=1'b0;S=1'b0;
#5 A=1'b1;B=1'b0;S=1'b1;
#5 A=1'b1;B=1'b1;S=1'b0;
#5 A=1'b1;B=1'b1;S=1'b1;
end

initial begin
$monitor("Simtime=%0t,A=%b,B=
%b,S=%b,
Y=%b",$time,A,B,S,Y);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,A,B,S,Y);
end

endmodule
#Odd and even detector:

Test: DUT:
module oddeven_test; module oddeven(A,B,C,O,E);
reg A,B,C; input A,B,C;
wire O,E; output O,E;

oddeven dut(.A(A),.B(B),.C(C),.O(O),.E(E)); assign O=C;


assign E=~C;
initial begin
A=1'b0;B=1'b0;C=1'b0; endmodule
#5 A=1'b0;B=1'b0;C=1'b1;
#5 A=1'b0;B=1'b1;C=1'b0;
#5 A=1'b0;B=1'b1;C=1'b1;
#5 A=1'b1;B=1'b0;C=1'b0;
#5 A=1'b1;B=1'b0;C=1'b1;
#5 A=1'b1;B=1'b1;C=1'b0;
#5 A=1'b1;B=1'b1;C=1'b1;
end

initial begin
$monitor("Simtime=%0t,A=%b,B=
%b,C=%b,O=%b, E=%b",$time,A,B,C,O,E);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,A,B,C,O,E);
end

endmodule
#Full adder:

Testbench: DUT:
module FA_tb; module FA(A,B,C,S,Co);

reg A,B,C; input A,B,C;


wire S,Co; output S,Co;
wire w1,w2,w3;
FA
dut(.A(A),.B(B),.C(C),.S(S),.Co(Co)); xor x1(S,A,B,C);
and a1(w1,A,B);
initial begin and a2(w2,B,C);
A=1'b0;B=1'b0;C=1'b0; and a3(w3,C,A);
#5 A=1'b0;B=1'b0;C=1'b1; or o1(Co,w1,w2,w3);
#5 A=1'b0;B=1'b1;C=1'b0;
#5 A=1'b0;B=1'b1;C=1'b1; endmodule
#5 A=1'b1;B=1'b0;C=1'b0;
#5 A=1'b1;B=1'b0;C=1'b1;
#5 A=1'b1;B=1'b1;C=1'b0;
#5 A=1'b1;B=1'b1;C=1'b1;
end

initial begin
$monitor("Simtime=%0t,A=
%b,B=%b, C=%b ,S=%b, Co=%b",
$time,A,B,C,S,Co);
end

initial begin
initial begin
$dumpfile("dump.vcd");
$dumpvars(0,A,B,C,S,Co);
end

endmodule
#Palindrome number detector

module palin_detect(b,y);

input [2:0]b;

output y;

xnor xn1(y,b[2],b[0]);

endmodule

#Binary to gray number conversion

module b2g_converter(b,g);

input [2:0]b;

output [2:0]g;

//g[2]=b[2] buffer can be used

buf b1(g[2],b[2]);

xor x1(g[1],b[2],b[1]);

xor x2(g[0],b[1],b[0]);

endmodule

#Decoder in gate-level modelling

module decoder2_4(i,d);

input [1:0]i;

output [3:0]d;

//intermediate signals

wire w1,w0;

//output signals

not n1(w1,i[1]);

not n2(w0,i[0]);

and a1(d[0],w1,w0);

and a2(d[1],w1,i[0]);

and a3(d[2],w2,i[1]);

and a4(d[3],i[1],i[0]);
endmodule

#Priority Encoder

module my_prio_enc(d,i);

input [3:0]d;

output [1:0]i;

wire w0,w1;

not n1(w0,d[2]);

and a1(w1,w0,d[1]);

or o1(i[0],w1,d[2]);

or o2(i[1],d[3],d[2]);

endmodule

#4:1 multiplexer using dataflow modelling

module mux41_gate(i,s,y);

input [3:0]i;

input [1:0]s;

output y;

//data flow execution

assign y =

(i[0]&(~s[1])&(~s[1]))|(i[1]&(~s[1])&s[0])|(i[2]&(~s[0])&s[1])|
(i[3]&(s[1])&s[

0]);

endmodule

#testbench code for above design

// Code your testbench here

// or browse Examples

module tb_mux41_gate;

reg [3:0] i;
reg [1:0] s;

wire y;

// Instantiate the MUX 4:1 module

mux41_gate uut (.i(i),.s(s),.y(y));

// Test stimulus

initial begin

// Monitor values

$monitor("Time = %0t | i = %b | s = %b | y = %b", $time, i, s, y);

// Apply test cases

i = 4'b0; s = 2'b00; #10;

i = 4'b1; s = 2'b01; #10;

i = 4'b10; s = 2'b10; #10;

i = 4'b11; s = 2'b11; #10;

end

initial begin

$dumpfile("dump_mux41.vcd");

$dumpvars(1,tb_mux41_gate);

end

endmodule

gate level

// 2:1 multiplexer using tristate inv

and buffer.

//multiplexer using tristate buffer

module mux21_tib(a,b,s,y);

input a,b,s;

output y;

bufif0 bi1(y,a,s); //active low

state buffer
bufif1 bi2(y,b,s); // active high

state buffer

endmodule

Data flow

module mux21(a,b,s,y);

input a,b,s;

output y;

assign y = s ? b : a; // if s=1 →

// y=b else y=a

endmodule
#2x1 mux using ternary operators:

Testbench: DUT:
module mux21_tb; module mux21(I,S,Y);

reg [1:0]I; input [1:0]I;


reg S; input S;
wire Y; output Y;

mux21 dut(.I(I),.S(S),.Y(Y)); assign Y=(S)?I[1]:I[0];

initial begin endmodule


{I,S}=3'b000;
#5 {I,S}=3'b001;
#5 {I,S}=3'b010;
#5 {I,S}=3'b011;
#5 {I,S}=3'b100;
#5 {I,S}=3'b101;
#5 {I,S}=3'b110;
#5 {I,S}=3'b111;
#5 {I,S}=3'b011;
#5;
end

initial begin
$monitor("Simtime=%0t,I[0]=%b,I[1]=
%b,S=%b,Y=%b", $time,I[0],I[1],S,Y);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,I,S,Y);
end

endmodule
#4x1 mux using ternary operators:

Testbench: DUT:
module mux41_tb; module mux41(I,S,Y);

reg [3:0]I; input [3:0]I;


reg [1:0]S; input [1:0]S;
wire Y; output Y;

mux41 dut(.I(I),.S(S),.Y(Y)); assign Y=(S[1])?


((S[0])?I[3]:I[2]):
initial begin ((S[0])?I[1]:I[0]);
{I,S}=6'b000000;
#5 {I,S}=6'b000001; endmodule
#5 {I,S}=6'b000010;
#5 {I,S}=6'b000011;
#5 {I,S}=6'b000100;
#5 {I,S}=6'b000101;
#5 {I,S}=6'b000110;
#5 {I,S}=6'b000111;
#5 {I,S}=6'b001000;
#5 {I,S}=6'b001001;
#5 {I,S}=6'b001010;
#5 {I,S}=6'b001011;
#5 {I,S}=6'b001100;
#5 {I,S}=6'b001101;
#5 {I,S}=6'b001110;
#5 {I,S}=6'b001111;
#5 {I,S}=6'b010000;
#5 {I,S}=6'b010001;
#5 {I,S}=6'b010010;
#5 {I,S}=6'b010011;
#5 {I,S}=6'b010100;
#5 {I,S}=6'b010101;
#5 {I,S}=6'b010110;
#5 {I,S}=6'b010111;
#5 {I,S}=6'b011000;
#5 {I,S}=6'b011001;
#5 {I,S}=6'b011010;
#5 {I,S}=6'b011011;
#5 {I,S}=6'b011100;
#5 {I,S}=6'b011101;
#5 {I,S}=6'b011110;
#5 {I,S}=6'b011111;
#5 {I,S}=6'b100000;
#5 {I,S}=6'b100001;
#5 {I,S}=6'b100010;
#5 {I,S}=6'b100011;
#5 {I,S}=6'b100100;
#5 {I,S}=6'b100101;
#5 {I,S}=6'b100110;
#5 {I,S}=6'b100111;
#5 {I,S}=6'b101000;
#5 {I,S}=6'b101001;
#5 {I,S}=6'b101010;
#5 {I,S}=6'b101011;
#5 {I,S}=6'b101100;
#5 {I,S}=6'b101101;
#5 {I,S}=6'b101110;
#5 {I,S}=6'b101111;
#5 {I,S}=6'b110000;
#5 {I,S}=6'b110001;
#5 {I,S}=6'b110010;
#5 {I,S}=6'b110011;
#5 {I,S}=6'b110100;
#5 {I,S}=6'b110101;
#5 {I,S}=6'b110110;
#5 {I,S}=6'b110111;
#5 {I,S}=6'b111000;
#5 {I,S}=6'b111001;
#5 {I,S}=6'b111010;
#5 {I,S}=6'b111011;
#5 {I,S}=6'b111100;
#5 {I,S}=6'b111101;
#5 {I,S}=6'b111110;
#5 {I,S}=6'b111111;

#5 {I,S}=6'b000011;
#5;
end

initial begin
$monitor("Simtime=%0t,I=%b,S=%b,Y=
%b",$time,I,S,Y);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,I,S,Y);
end

endmodule

#2-bit magnitude comparator:

Testbench: DUT:
module magcomp_tb; module
magcomp(A,B,
reg [1:0]A,B; G,E,L);
wire G,E,L;
input [1:0]A,B;
magcomp dut(.A(A),.B(B),.G(G),.E(E),.L(L)); output G,E,L;

initial begin assign


G=(A>B)?
{A,B}=4'b0000; 1'b1:1'b0;
#5 {A,B}=4'b0001; assign
#5 {A,B}=4'b0010; E=(A==B)?
#5 {A,B}=4'b0011; 1'b1:1'b0;
#5 {A,B}=4'b0100; assign
#5 {A,B}=4'b0101; L=(A<B)?
#5 {A,B}=4'b0110; 1'b1:1'b0;
#5 {A,B}=4'b0111;
#5 {A,B}=4'b1000; endmodule
#5 {A,B}=4'b1001;
#5 {A,B}=4'b1010;
#5 {A,B}=4'b1011;
#5 {A,B}=4'b1100;
#5 {A,B}=4'b1101;
#5 {A,B}=4'b1110;
#5 {A,B}=4'b1111;
#5;
end

initial begin
$monitor("Simtime=%0t,A=%b,B=%b,G=%b,E=
%b,L=%b",$time,A,B,G,E,L);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,A,B,G,E,L);
end

endmodule
#3-bit palindrome detector:

Testbench: DUT:
module palin_tb; module palin(A,Y);

reg [2:0]A; input [2:0]A;


wire Y; output Y;

palin dut(.A(A),.Y(Y)); assign Y=(A[0]===A[2])?


1'b1:1'b0;
initial begin
endmodule
A=3'b000;
#5 A=3'b001;
#5 A=3'b010;
#5 A=3'b011;
#5 A=3'b100;
#5 A=3'b101;
#5 A=3'b110;
#5 A=3'b111;
#5 A=3'b000;

#5;
end

initial begin
$monitor("Simtime=%0t,A=
%b,Y=%b", $time,A,Y);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,A,Y);
end

endmodule
#Full adder using structural modelling:

Testbench: DUT:
module FA_tb; `include
"halfadd.sv"
reg a,b,cin;
wire sum,cout; module
FA(a,b,cin,sum,cout
FA );
dut(.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
input a,b,cin;
initial begin output sum,cout;
wire w[2:0];
for(integer i=0;i<2**3;i=(i+1))
HA
begin h1(.a(a),.b(b),.s(w[0
{a,b,cin}=i; ]),.c(w[1]));
#5; HA
end h2(.a(w[0]),.b(cin),.
s(sum),.c(w[2]));
a=1'b0;
#5; assign cout=w[1]|
w[2];
end
endmodule
initial begin
module HA(a,b,s,c);
$monitor("Simtime=%0t,a=%b,b=%b,cin=
%b,sum=%b,cout=%b",$time,a,b,cin,sum,cout); input a,b;
output s,c;
end assign s=a^b;
assign c=a&b;
initial begin
endmodule
$dumpfile("dump.vcd");
$dumpvars(0,a,b,cin,sum,cout);

end

endmodule

Result:
#4-bit adder:

Testbench: DUT:
module adder4bit_tb; `include "fulladd.sv"

reg [3:0]a,b; module


reg cin; adder4bit(a,b,cin,s,cout);
wire [3:0]s;
wire cout; input [3:0]a,b;
input cin;
adder4bit output [3:0]s;
dut(.a(a),.b(b),.cin(cin),.s(s),.cout(cout)); output cout;
wire [2:0]c;
initial begin
FA
for(integer i=0;i<2**9;i=(i+1)) f1(.a(a[0]),.b(b[0]),.cin(cin)
,.sum(s[0]),.cout(c[0]));
begin FA
{a,b,cin}=i; f2(.a(a[1]),.b(b[1]),.cin(c[0
#5; ]),.sum(s[1]),.cout(c[1]));
end FA
f3(.a(a[2]),.b(b[2]),.cin(c[1
a=1'b0; ]),.sum(s[2]),.cout(c[2]));
#5; FA
f4(.a(a[3]),.b(b[3]),.cin(c[2
end ]),.sum(s[3]),.cout(cout));

initial begin endmodule

$monitor("Simtime=%0t,a=%b,b=
%b,cin=%b,s=%b,cout=%b",
$time,a,b,cin,s,cout);

end

initial begin

$dumpfile("dump.vcd");
$dumpvars(0,a,b,cin,s,cout);

end

endmodule
#Generic adder:

Testbench: DUT:
module genadd_tb; module genadd
#(parameter N=4)
reg [dut.N-1:0]a,b; (a,b,s);
wire [dut.N:0]s;
input [N-1]a,b;
genadd dut(.a(a),.b(b),.s(s)); output [N:0] s;

initial begin assign s=a+b;


repeat(20)
begin endmodule
{a,b}=$random
end
end

initia begin
$monitor("Simtime=%0t,a=%b,b=%b,s=%b",
$time,a,b,s);
end

initial begin
$dumpfile("dump.vcd");
$dumpvars(0,a,b,s);
end

endmodule

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