Power Electronics III -I

(R23) UNIT-I
POWER SWITCHING DEVICES
Topics:-
Diode, Thyristor, MOSFET, IGBT: I-V Characteristics; Firing circuit for thyristor;
Voltage and current commutation of a thyristor; Gate drive circuits for MOSFET, IGBT
and GTO. Introduction to Galium Nitride and Silicon carbide Devices.

DIODE:
Power Semiconductor Diodes
Introduction:
Power semiconductor diode is the “power level” counter part of the “low power signal diodes”
with which most of us have some degree of familiarity. These power devices, however, are
required to carry up to several KA of current under forward bias condition and block up to
several KV under reverse biased condition. These extreme requirements call for important
structural changes in a power diode which significantly affect their operating characteristics.
These structural modifications are generic in the sense that the same basic modifications are
applied to all other low power semiconductor devices (all of which have one or more p-n
junctions) to scale up their power capabilities. It is, therefore, important to understand the nature
and implication of these modifications in relation to the simplest of the power devices, i.e., a
power semiconductor diode.
Review of Basic p-n Diode Characteristics
A p-n junction diode is formed by placing p and n type semiconductor materials in intimate
contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type
silicon crystal or by the opposite sequence. In an open circuit p-n junction diode, majority
carriers from either side will defuse across the junction to the opposite side where they are in
minority. These diffusing carriers will leave behind a region of ionized atoms at the immediate
vicinity of the metallurgical junction. This region of immobile ionized atoms is called the space
charge region. This process continues till the resultant electric field (created by the space charge
density) and the potential barrier at the junction builds up to sufficient level to prevent any
further migration of carriers. At this point the p-n junction is said to be in thermal equilibrium
condition. Variation of the space charge density, the electric field and the potential along the
device is shown in Fig

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When an external voltage is applied with p side move negative then the n side the junction is said
to be under reverse bias condition. This reverse bias adds to the height of the potential barrier.
The electric field strength at the junction and the width of the space change region (also called
“the depletion region” because of the absence of free carriers) also increases. On the other hand,
free minority carrier densities (np in the p side and pn in the n side) will be zero at the edge of
the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density causes a
small flux of minority carriers to defuse towards the deletion layer where they are swept
immediately by the large electric field into the electrical neutral region of the opposite side. This
will constitute a small leakage current across the junction from the n side to the p side. There will
also be a contribution to the leakage current by the electron hole pairs generated in the space
change layer by the thermal ionization process. These two components of current together is
called the “reverse saturation current Is” of the diode. Value of Is is independent of the reverse
voltage magnitude (up to a certain level) but extremely sensitive to temperature variation. When
the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current
increases rapidly. The diode is said to have undergone “reverse break down”. Reverse break
down is caused by "impact ionization" as explained below. Electrons accelerated by the large
depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy
to liberate another electron from the covalent bonds when it strikes a silicon atom. The liberated
electron in turn may repeat the process. This cascading effect (avalanche) may produce a large
number of free electrons very quickly resulting in a large reverse current. The power dissipated
in the device increases manifold and may cause its destruction. Therefore, operation of a diode in
the reverse breakdown region must be avoided.
When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is
lowered and a very large number of minority carriers are injected to both sides of the junction.

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The injected minority carriers eventually recombines with the majority carries as they defuse
further into the electrically neutral drift region. The excess free carrier density in both p and n
side follows exponential decay characteristics. The characteristic decay length is called the
"minority carrier diffusion length" Carrier density gradients on either side of the junction are
supported by a forward current IF (flowing from p side to n side) which can be expressed as
IF = IS exp qv/kT -1
Where Is = Reverse saturation current ( Amps)
v = Applied forward voltage across the device (volts)
q = Change of an electron
k = Boltzman’s constant
= Temperature in Kelvin From the foregoing discussion the i-v characteristics of a p-n junction
diode can be drawn as shown in Fig 2.2. While drawing this characteristics the ohmic drop in the
bulk of the semiconductor body has been neglected.

Construction and Characteristics of Power Diodes

As mention in the introduction Power Diodes of largest power rating are required to conduct
several kilo amps of current in the forward direction with very little power loss while blocking
several kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer in
order to restrict the maximum electric field strength below the “impact ionization” level. Space
charge density in the depletion layer should also be low in order to yield a wide depletion layer
for a given maximum Electric fields strength. These two requirements will be satisfied in a
lightly doped p-n junction diode of sufficient width to accommodate the required depletion layer.
Such a construction, however, will result in a device with high resistively in the forward
direction. Consequently, the power loss at the required rated current will be unacceptably high.
On the other hand if forward resistance (and hence power loss) is reduced by increasing the
doping level, reverse break down voltage will reduce. This apparent contradiction in the
requirements of a power diode is resolved by introducing a lightly doped “drift layer” of required
thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b)
shows the circuit symbol and the photograph of a typical power diode respectively

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Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross section.
To arrive at the structure shown in Fig 2.3 (c) a lightly doped n- epitaxial layer of specified width
(depending on the required break down voltage) and donor atom density (NdD) is grown on a
heavily doped n+ substrate (NdK donor atoms.Cm -3) which acts as the cathode. Finally the p-n
junction is formed by defusing a heavily doped (NaA acceptor atoms.Cm-3) p+ region into the
epitaxial layer. This p type region acts as the anode. Impurity atom densities in the heavily doped
cathode (Ndk .Cm -3) and anode (NaA.Cm -3) are approximately of the same order of magnitude
(10 19 Cm -3) while that of the epitaxial layer (also called the drift region) is lower by several
orders of magnitude (NdD ≈ 10 14 Cm-3). In a low power diode this drift region is absent. The
Implication of introducing this drift region in a power
Power Diode under Reverse Bias Conditions
As in the case of a low power diode the applied reverse voltage is supported by the depletion
layer formed at the p+ n- metallurgical junction. Overall neutrality of the space change region
dictates that the number of ionized atoms in the p+ region should be same as that in the n- region.
However, since NdD << NaA, the space charge region almost exclusively extends into the n-
drift region. Now the physical width of the drift region (WD) can be either larger or smaller than
the depletion layer width at the break down voltage. Consequently two type of diodes exist, (i)
non punch through type, (ii) punch through type. In “non-punch through” diodes the depletion
layer boundary doesn’t reach the end of the drift layer. On the other hand in “punch through”
diodes the depletion layer spans the entire drift region and is in contact with the n+ cathode.
However, due to very large doping density of the cathode, penetration of drift region inside

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cathode is negligible. Electric field strength inside the drift region of both these type of diodes at
break down voltage is shown in Fig 2.4.

In non-punch through type diodes the electric field strength is maximum at the p+ n- junction
and decrease to zero at the end of the depletion region. Where as, in the punch through
construction the field strength is more uniform. In fact, by choosing a very lightly doped n- drift
region, Electric field strength in this region can be mode almost constant. Under the assumption
of uniform electric field strength it can be shown that for the same break down voltage, the
“punch through” construction will require approximately half the drift region width of a
comparable “ non - punch through” construction. Lower drift region doping in a “punch through”
diode does not carry the penalty of higher conduction lasses due to “conductivity modulation” to
be discussed shortly. In fact, reduced width of the drift region in these diodes lowers the on-state
voltage drop for the same forward current density compared to a non-punch through diode.
Under reverse bias condition only a small leakage current (less than 100mA for a rated forward
current in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). This
reverse current is independent of the applied reverse voltage but highly sensitive to junction
temperature variation. When the applied reverse voltage reaches the break down voltage, reverse
current increases very rapidly due to impact ionization and consequent avalanche multiplication
process. Voltage across the device dose not increase any further while the reverse current is
limited by the external circuit. Excessive power loss and consequent increase in the junction
temperature due to continued operation in the reverse brake down region quickly destroies the
diode. Therefore, continued operation in the reverse break down region should be avoided. A
typical I-V characteristic of a power diode under reverse bias condition is shown in Fig 2.5.

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A few other important specifications of a power Diode under reverse bias condition usually
found in manufacturer’s data sheet are explained below.
DC Blocking Voltage (VRDC): Maximum direct voltage that can be applied in the reverse
direction (i.e cathode positive with respect to anode) across the device for indefinite period of
time. It is useful for selecting free-wheeling diodes in DC-DC Choppers and DC-AC voltage
source inverter circuits.
RMS Reverse Voltage (VRMS): It is the RMS value of the power frequency (50/60 HZ) since
wave voltage that can be directly applied across the device. Useful for selecting diodes for
controlled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given by
the manufacturer under the assumption that the supply voltage may rise by 10% at the most. This
rating is different for resistive and capacitive loads.
Peak Repetitive Reverse Voltage (VRRM): This is the maximum permissible value of the
instantiations reverse voltage appearing periodically across the device. The time period between
two consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZ
supply). This type of period reverse voltage may appear due to “commutation” in a converter.
Peak Non-Repetitive Reverse Voltage (VRSM): It is the maximum allowable value of the
instantaneous reverse voltage across the device that must not recur. Such transient reverse
voltage can be generated by power line switching (i.e circuit Breaker opening / closing) or
lightning surges.

Transistors:
Bipolar Junction Transistors (BJT)
General configuration and definitions

The transistor is the main building block “element” of electronics. It is a semiconductor device
and it comes in two general types: the Bipolar Junction Transistor (BJT) and the Field Effect
Transistor (FET). Here we will describe the system characteristics of the BJT configuration and
explore its use in fundamental signal shaping and amplifier circuits.

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The BJT is a three terminal device and it comes in two different types. The npn BJT and the pnp
BJT. The BJT symbols and their corresponding block diagrams are shown on Figure 1. The BJT
is fabricated with three separately doped regions. The npn device has one p region between two n
regions and the pnp device has one n region between two p regions.
The BJT has two junctions (boundaries between the n and the p regions). These junctions are
similar to the junctions we saw in the diodes and thus they may be forward biased or reverse
biased. By relating these junctions to a diode model the pnp BJT may be modeled as shown on
Figure 2.

The three terminals of the BJT are called the Base (B), the Collector (C) and the Emitter (E).

Since each junction has two possible states of operation (forward or reverse bias) the BJT with
its two junctions has four possible states of operation.
Here it is sufficient to say that the structure as shown on Figure 1 is not symmetric. The n and p
regions are different both geometrically and in terms of the doping concentration of the regions.
For example, the doping concentrations in the collector, base and emitter may be, , and
respectively. Therefore the behavior of the device is not electrically symmetric and the two ends
cannot be interchanged.
Before proceeding let’s consider the BJT npn structure shown on Figure 3.

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Transistor Operation and Characteristic i-v curves

The three terminals of the transistors and the two junctions, present us with multiple operating
regimes. In order to distinguish these regimes we have to look at the i-v characteristics of the
device.
The most important characteristic of the BJT is the plot of the collector current, CI, versus the
collector-emitter voltage, , for various values of the base current, CEVBI as shown on the circuit
of Figure 6.

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Figure 6. Common emitter BJT circuit for determining output characteristics

Figure 7 shows the qualitative characteristic curves of a BJT. The plot indicates the four regions
of operation: the saturation, the cutoff, the active and the breakdown. Each family of curves is
drawn for a different base current and in this plot.

The characteristics of each region of operation are summarized below.

1. cutoff region: Base-emitter junction is reverse biased. No current flow

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Basic BJT Applications

Switch

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Equation (1.8) is the load line equation for this circuit. In graphical form it is shown on
Figure 9.

As the base current increases the transistor may operate at points along the load line (thick
dashed line on Figure 9). In the limit, the base current IB3 results in the largest current IC. This is

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the saturation current and when the transistor operates at this point it is said to be biased in the
saturation mode. In saturation, the base-collector junction is forward biased and the relationship
between the base and the collector current is not linear.
Therefore the collector current at saturation is

MOSFET
MOSFET I-V CHARACTERISTICS
1. MOSFET Cross Section ,layout and Symbol.
2. Operation
3. I-V Characteristics

Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc)
have been the front runners in the quest for an ideal power electronic switch. Ever since the
invention of the transistor, the development of solid-state switches with increased power
handling capability has been of interest for expending the application of these devices. The BJT
and the GTO thyristor have been developed over the past 30 years to serve the need of the power
electronic industry. Their primary advantage over the thyristors have been the superior switching
speed and the ability to interrupt the current without reversal of the device voltage. All bipolar
devices, however, suffer from a common set of disadvantages, namely, (i) limited switching
speed due to considerable redistribution of minority charge carriers associated with every
switching operation; (ii) relatively large control power requirement which complicates the
control circuit design. Besides, bipolar devices can not be paralleled easily.
The reliance of the power electronics industry upon bipolar devices was challenged by the
introduction of a new MOS gate controlled power device technology in the 1980s. The power
MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The
new device promised extremely low input power levels and no inherent limitation to the
switching speed. Thus, it opened up the possibility of increasing the operating frequency in
power electronic systems resulting in reduction in size and weight. The initial claims of infinite
current gain for the power MOSFET were, however, diluted by the need to design the gate drive
circuit to account for the pulse currents required to charge and discharge the high input
capacitance of these devices. At high frequency of operation the required gate drive power
becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area
of the device cross section which increases with the blocking voltage rating of the device.
Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts)
applications where the ON state resistance reaches acceptable values. Inherently fast switching
speed of these devices can be effectively utilized to increase the switching frequency beyond
several hundred kHz.
From the point of view of the operating principle a MOSFET is a voltage controlled
majority carrier device. As the name suggests, movement of majority carriers in a
MOSFET is controlled by the voltage applied on the control electrode (called gate) which

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is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric
field produced by the gate voltage modulate the conductivity of the semiconductor
material in the region between the main current carrying terminals called the Drain (D)
and the Source (S). Power MOSFETs, just like their integrated circuit counterpart, can be
of two types (i) depletion type and (ii) enhancement type. Both of these can be either n-
channel type or p-channel type depending on the nature of the bulk semiconductor. Fig
6.1 (a) shows the circuit symbol of these four types of MOSFETs along with their drain
current vs gate-source voltage characteristics (transfer characteristics).

From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type
switches i.e, with the gate terminal open a nonzero drain current can flow in these
devices. This is not convenient in many power electronic applications. Therefore, the
enhancement type MOSFETs (particularly of the n-channel variety) is more popular for
power electronics applications. This is the type of MOSFET which will be discussed in
this lesson. Fig 6.1 (b) shows the photograph of some commercially available n-channel
enhancement type Power MOSFETs.

Constructional Features of a Power MOSFET

As mentioned in the introduction section, Power MOSFET is a device that evolved from
MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs
were by redesigning lateral MOSFET to increase their voltage blocking capacity. The
resulting technology was called lateral double deffused MOS (DMOS). However it was
soon realized that much larger breakdown voltage and current ratings could be achieved
by resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS)
structure has been adapted by virtually all manufacturers of Power MOSFET. A power
MOSFET using VDMOS technology has vertically oriented three layer structure of
alternating p type and n type semiconductors as shown in Fig 6.2 (a) which is the
schematic representation of a single MOSFET cell structure. A large number of such cells
are connected in parallel (as shown in Fig 6.2 (b)) to form a complete device.

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+
The two n end layers labeled “Source” and “Drain” are heavily doped to approximately
the same level. The p type middle layer is termed the body (or substrate) and has
+
moderate doping level (2 to 3 orders of magnitude lower than n regions on both sides).
-
The n drain drift region has the lowest doping density. Thickness of this region
-
determines the breakdown voltage of the device. The gate terminal is placed over the n
and p type regions of the cell structure and is insulated from the semiconductor body be a
thin layer of silicon dioxide (also called the gate oxide). The source and the drain region
of all cells on a wafer are connected to the same metallic contacts to form the Source and

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the Drain terminals of the complete device. Similarly all gate terminals are also
connected together. The source is constructed of many (thousands) small polygon shaped
areas that are surrounded by the gate regions. The geometric shape of the source regions,
to same extent, influences the ON state resistance of the MOSFET.

Parasitic BJT in a MOSFET cell.

+ - +
One interesting feature of the MOSFET cell is that the alternating n n p n structure
embeds a parasitic BJT (with its base and emitter shorted by the source metallization)
into each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base
and the emitter of the parasitic npn BJT arises due to the body spreading resistance of the
p type substrate. In the design of the MOSFET cells special care is taken so that this
resistance is minimized and switching operation of the parasitic BJT is suppressed. With
an effective short circuit between the body and the source the BJT always remain in cut
off and its collector-base junction is represented as an anti parallel diode (called the body
diode) in the circuit symbol of a Power MOSFET.
Operating principle of a MOSFET
At first glance it would appear that there is no path for any current to flow between the
source and the drain terminals since at least one of the p n junctions (source – body and
body-Drain) will be reverse biased for either polarity of the applied voltage between the
source and the drain. There is no possibility of current injection from the gate terminal
either since the gate oxide is a very good insulator. However, application of a positive
voltage at the gate terminal with respect to the source will covert the silicon surface
beneath the gate oxide into an n type layer or “channel”, thus connecting the Source to
the Drain as explained next.
The gate region of a MOSFET which is composed of the gate metallization, the gate
(silicon) oxide layer and the p-body silicon forms a high quality capacitor. When a small
voltage is application to this capacitor structure with gate terminal positive with respect
to the source (note that body and source are shorted) a depletion region forms at the
interface between the SiO2 and the silicon as shown in Fig 6.4 (a).

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The positive charge induced on the gate metallization repels the majority hole carriers from the
interface region between the gate oxide and the p type body. This exposes the negatively
charged acceptors and a depletion region is created.
Further increase in VGS causes the depletion layer to grow in thickness. At the same time the
electric field at the oxide-silicon interface gets larger and begins to attract free electrons as
shown in Fig 6.4 (b). The immediate source of electron is electron-hole generation by
thermal ionization. The holes are repelled into the semiconductor bulk ahead of the
depletion region. The extra holes are neutralized by electrons from the source.
As V increases further the density of free electrons at the interface becomes equal to the free
GS
hole density in the bulk of the body region beyond the depletion layer. The layer of free
electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The
inversion layer has all the properties of an n type semiconductor and is a conductive path or
“channel” between the drain and the source which permits flow of current between the
drain and the source. Since current conduction in this device takes place through an n- type
“channel” created by the electric field due to gate source voltage it is called “Enhancement
type n-channel MOSFET”.
The value of VGS at which the inversion layer is considered to have formed is called the
“Gate – Source threshold voltage VGS (th)”. As VGS is increased beyond VGS(th) the
inversion layer gets some what thicker and more conductive, since the density of free
electrons increases further with increase in V . The inversion layer screens the depletion
GS
layer adjacent to it from increasing VGS. The depletion layer thickness now remains
constant.
Steady state output i-v characteristics of a MOSFET
The MOSFET, like the BJT is a three terminal device where the voltage on the gate
terminal controls the flow of current between the output terminals, Source and Drain. The
source terminal is common between the input and the output of a MOSFET. The output
characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain
–Source voltage (vDS) with gate source voltage (vGS) as a parameter. Fig 6.5 (a) shows
such a characteristics.

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With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET operates in
the cut-off mode. No drain current flows in this mode and the applied drain–source voltage
(vDS) is supported by the body-collector p-n junction. Therefore, the maximum applied
voltage should be below the avalanche break down voltage of this junction (V DSS) to avoid
destruction of the device.
When VGS is increased beyond vGS(th) drain current starts flowing. For small values of
vDS (vDS < (vGS – vGS(th)) iD is almost proportional to vDS. Consequently this mode of
operation is called “ohmic mode” of operation. In power electronic applications a
MOSFET is operated either in the cut off or in the ohmic mode. The slope of the vDS – iD
characteristics in this mode is called the ON state resistance of the MOSFET (r DS (ON)).
Several physical resistances as shown in Fig 6.5 (b) contribute to r DS (ON). Note that rDS
(ON) reduces with increase in vGS. This is mainly due to reduction of the channel
resistance at higher value of
v . Hence, it is desirable in power electronic applications, to use as large a gate-source voltage
GS
as possible subject to the dielectric break down limit of the gate-oxide layer.
At still higher value of vDS (vDS > (vGS – vGS (th)) the iD – vDS characteristics deviates from
the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with
increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state
that, at higher drain current the voltage drop across the channel resistance tends to
decrease the channel width at the drain drift layer end. In addition, at large value of the
electric field, produced by the large Drain – Source voltage, the drift velocity of free
electrons in the channel tends to saturate as shown in Fig 6.5 (c). As a result the drain
current becomes independent of VDS and determined solely by the gate – source voltage
v . This is the active mode of operation of a MOSFET.
GS

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At this point the similarity of the output characteristics of a MOSFET with that of a BJT should
be apparent. Both of them have three distinct modes of operation, namely, (i)cut off, (ii)
active and (iii) ohmic (saturation for BJT) modes. However, there are some important
differences as well.
• Unlike BJT a power MOSFET does not undergo second break down.

• The primary break down voltage of a MOSFET remains same in the cut off and in the
active modes. This should be contrasted with three different break down voltages
(V , V & V ) of a BJT.
SUS CEO CBO

• The ON state resistance of a MOSFET in the ohmic region has positive temperature
coefficient which allows paralleling of MOSFET without any special arrangement
for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature
coefficient making parallel connection of BJTs more complicated.

As in the case of a BJT the operating limits of a MOSFET are compactly represented in a
Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of
a
BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is
restricted by the absolute maximum permissible value of the drain current (I DM) which
should not be exceeded even under pulsed operating condition. To the left, operating
restriction arise due to the non zero value of r DS(ON) corresponding to vGS = vGS(Max).
To the right, the first operating restriction is due to the limit on the maximum permissible
junction temperature rise which depends on the power dissipation inside the MOSFET.
This limit is different for DC (continuous) and pulsed operation of different pulse widths.
As in the case of a BJT the pulsed safe operating areas are useful for shaping the
switching trajectory of a MOSFET. A MOSFET does not undergo “second break down”
and no corresponding operating limit appears on the SOA. The final operation limit to the
extreme right of the SOA arises due to the maximum permissible drain source voltage
(VDSS) which is decided by the avalanche break down voltage of the drain -body p-n
junction. This is an instantaneous limit. There is no distinction between the forward
biased and the reverse biased SOAs for the MOSFET. They are identical.

Safe operating area of a MOSFET.

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Due to the presence of the anti parallel “body diode”, a MOSFET can not block any reverse
voltage. The body diode, however, can carry an RMS current equal to I DM. It also has a
substantial surge current carrying capacity. When reverse biased it can block a voltage
equal to VDSS.
For safe operation of a MOSFET, the maximum limit on the gate source voltage (V GS
(Max)) must be observed. Exceeding this voltage limit will cause dielectric break down
of the thin gate oxide layer and permanent failure of the device. It should be noted that
even static charge inadvertently put on the gate oxide by careless handling may destroy it.
The device user should ground himself before handling any MOSFET to avoid any static
charge related problem.

IGBT
IGBT is a relatively new device in power electronics and before the advent of IGBT, Power
MOSFETs and Power BJT were common in use in power electronic applications. Both of these
devices possessed some advantages and simultaneously some disadvantages. On one hand, we
had bad switching performance, low input impedance, secondary breakdown and current
controlled Power BJT and on the other we had excellent conduction characteristics of it.
Similarly, we had excellent switching characteristics, high input impedance, voltage controlled
PMOSFETs, which also had bad conduction characteristics and problematic parasitic diode at
higher ratings. Though the unipolar nature of PMOSFETs leads to low switching times, it also
leads to high ON-state resistance as the voltage rating increases.
Thus the need was for such a device which had the goodness of both PMOSFETs and Power BJT
and this was when IGBT was introduced in around the early 1980s and became very popular
among power electronic engineers because of its superior characteristics. IGBT has PMOSFET
like input characteristics and Power BJT like output characteristics and hence its symbol is also
an amalgamation of the symbols of the two parent devices. The three terminals of IGBT are
Gate, Collector and Emitter. The figure below shows the symbol of IGBT.

IGBT is known by various other names also, such as- Metal Oxide Insulated Gate Transistor
(MOSIGT), Gain Modulated Field Effect Transistor (GEMFET), Conductively Modulated Field
Effect Transistor (COMFET), Insulated Gate Transistor (IGT).

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The structure of IGBT is very much similar to that of PMOSFET, except one layer known as
injection layer which is p+ unlike n+ substrate in PMOSFET. This injection layer is the key to the
superior characteristics of IGBT. Other layers are called the drift and the body region. The two
junctions are labeled J1 and J2. Figure below show the structure of n-channel IGBT.

Upon careful observation of the structure, we’ll find that there exists an n-channel MOSFET and
two BJTs- Q1 and Q2 as shown in the figure. Q1 is p+n–p BJT and Q2 is n–pn + BJT. Rd is the
resistance offered by the drift region and R b is the resistance offered by p body region. We can
observe that the collector of Q1 is same as base of Q2 and collector of Q2 is same as base of Q1.
Hence we can arrive at an equivalent circuit model of IGBT as shown in the figure below

The two transistor back to back connection forms a parasitic thyristor as shown in the above
figure.

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N-channel IGBT turns ON when the collector is at a positive potential with respect to emitter and
gate also at sufficient positive potential (>VGET) with respect to emitted. This condition leads to
the formation of an inversion layer just below the gate, leading to a channel formation and a
current begins to flow from collector to emitter.
The collector current Ic in IGBT constitutes of two components- Ie and Ih. Ie is the current due to
injected electrons flowing from collector to emitter through injection layer, drift layer and finally
the channel formed. Ih is the hole current flowing from collector to emitter through Q1 and body
resistance Rb. Hence

Although Ih is almost negligible and hence Ic ≈ Ie.

A peculiar phenomenon is observed in IGBT known as Latching up of IGBT. This occurs when
collector current exceeds a certain threshold value (ICE). In this the parasitic thyristor gets latched
up and the gate terminal loses control over collector current and IGBT fails to turn off even when
gate potential is reduced below VGET. For turning OFF of IGBT now, we need typical
commutation circuitry as in the case of forced commutation of thyristors. If the device is not
turned off as soon as possible, it may get damaged.
Characteristics of IGBT
Static I-V Characteristics of IGBT
The figure below shows static i-v characteristics of an n-channel IGBT along with a circuit
diagram with the parameters marked.

The graph is similar to that of a BJT except that the parameter which is kept constant for a plot is
VGE because IGBT is a voltage controlled device unlike BJT which is a current controlled
device. When the device is in OFF mode (VCE is positive and VGE < VGET) the reverse voltage is
blocked by J2 and when it is reverse biased, i.e. VCE is negative, J1 blocks the voltage.
Transfer Characteristics of IGBT
Figure below shows the transfer characteristic of IGBT, which is exactly same as PMOSFET.
The IGBT is in ON-state only after VGE is greater than a threshold value VGET.

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Switching Characteristics of IGBT

The figure below shows the typical switching characteristic of IGBT

Turn on time ton is composed of two components as usual, delay time (t dn) and rise time (tr).
Delay time is defined as the time in which collector current rises from leakage current I CE
to 0.1 IC (final collector current) and collector emitter voltage falls from V CE to 0.9VCE. Rise
time is defined as the time in which collector current rises from 0.1 IC to IC and collector
emitter voltage falls from 0.9VCE to 0.1 VCE.

The turn off time toff consists of three components, delay time (t df), initial fall time (tf1) and
final fall time (tf2). Delay time is defined as time when collector current falls from IC to 0.9
IC and VCE begins to rise. Initial fall time is the time during which collector current falls

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from 0.9 IC to 0.2 IC and collector emitter voltage rises to 0.1 VCE. The final fall time is
defined as time during which collector current falls from 0.2 IC to 0.1 IC and 0.1VCE rises to
final value VCE.

Advantages and Disadvantages of IGBT

Advantages:-
Advantages of IGBT are showing below
 Lower gate drive requirements
 Low switching losses
 Small snubber circuitry requirements
 High input impedance
 Voltage controlled device
 Temperature coefficient of ON state resistance is positive and less than PMOSFET,
hence less On-state voltage drop and power loss.
 Enhanced conduction due to bipolar nature
 Better Safe Operating Area
Disadvantages:-
Disadvantages of IGBT are showing below
 Cost
 Latching-up problem
 High turn off time compared to PMOSFET

THYRISTOR
A Thyristor is basically an on-off switch to control the output power of an electrical circuit by
switching on and off the load circuit in intervals of time. In this post, we will try to understand
what is it, How it works, its Voltage Ampere (VI) characteristics, modes of operation,
applications, advantages and disadvantages.
A Thyristor is a unidirectional semiconductor solid state device with four layers of alternating P
and N type material. It consist of three electrodes i.e. Anode, Cathode and a Gate. Anode is the
positive terminal and Cathode is the negative terminal.
The Gate controls the flow of current between anode and cathode. It is used in electronic devices
and equipment to control the electric power or current. It acts as a rectifier and can only transmits
current in one direction.
The first Thyristor was produced in the year 1956. The most common type of Thyristor is silicon
Controlled Rectifier (SCR).

Symbol of Thyristor
How Thyristor Works
A Thyristor acts like a diode. It has two layers of semiconductors namely p-type and n-type
sandwiched together to form a junction. The anode is connected to the outer p-layer, cathode to

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the outer n-layer and gate to the internal p-layer. It has 3 junctions namely J1, J2, J3 as shown in
the Figure 2 below.
When the anode is at positive potential with respect to cathode, no voltage is applied to the gate.
The junctions J1, J3 is forward biased and J2 is reverse biased. So no conduction takes place
here.

Layer Diagram of Thyristor

Now, when the positive potential is increased beyond the breakdown voltage, breakdown of
junction J2 takes place and it starts conducting. Once the breakdown has occurred, it continues to
conduct irrespective of the gate voltage, until the potential at the anode is removed or current
through the device is made less than the holding current.
Now when a positive potential is applied at the gate terminal with respect to cathode, the
breakdown of junction J2 takes place. To switch on the Thyristor quickly, an appropriate
potential value has to be selected.
The gate acts as a controlling electrode. When a small voltage known as gate pulse is applied to
its gate , the device is triggered into conduction state .This continues until the voltage across the
device is reversed or removed.
The gate trigger current varies inversely with the gate voltage and a minimum gate charge is
required to trigger it. Thus the switching of Thyristors can be controlled through its gate pulse.
Two Transistor Analogy of Thyristor

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The collector current from the NPN transistor is fed directly to the base of PNP transistor, while
the collector current of PNP transistor is fed to the base of NPN. These interconnected transistors
rely on each other for conduction.
So for one of the transistors to conduct, a base current is required. When the Thyristor’s anode
terminal is negative with respect to cathode, the NP junction becomes forward biased and the PN
junction becomes reverse biased.
Here, the flow of reverse current is blocked until a breakdown voltage is applied. After
breakdown voltage, it starts to conduct without the application of gate signal. This is one of the
negative characteristics of Thyristors as it triggers into conduction by a reverse break over
voltage.
When the anode terminal is made positive with respect to cathode, the outer junctions are
forward biased and the centre NP junction is reverse biased and blocks the forward current. So to
trigger it into conduction, a positive current is applied to the base of transistors.
The two transistors are connected in a regenerative loop and this force the transistor to conduct to
saturation. Thus, it can be said that a Thyristors block current in both the direction of an AC
supply in its OFF state and can be turned ON by the application of positive current to the base of
transistor.
Voltage Ampere (VI) Characteristics of Thyristor
Thyristors can either be forward biased or reverse biased. We will see how it works in both
states.
Thyristors in Forward Biased State
When anode is made positive, the PN junctions at the ends are forward biased and center
junction (NP) becomes reverse biased. It will stay in blocked (OFF) mode (also known as
Forward Blocking Stage) till the time it is triggered by Gate current pulse or the applied voltage
reaches the forward breakover voltage.
Triggering by Gate Current Pulse – When it is triggered by the gate current pulse, it starts
conducting and will act as a close switch. The Thyristors remains in the ON-state, i.e. it remains
in the latched state. Here the gate loses its control to turn off the device.
Triggering by Forward Breakover Voltage – When a forward voltage is applied, a leakage
current starts to flow through the blocking (J2) in the middle junction of Thyristors. When

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voltage exceeds the forward break over voltage or critical limit, then J2 breaks down and it
reaches to the ON state.
When the Gate current (Ig) is increased, it reduces the blocking area and so the forward break
over voltage is reduced. It will turn ON when a minimum current called latching current is
maintained.
When the gate current Ig=0 and anode current falls below a certain value called holding current
during the ON state, it again reaches to its forward blocking state.

V-I Characteristics of Thyristor.

Firing circuit for thyristor;
Different turn ON methods for SCR
1. Forward voltage triggering
2. Gate triggering
3. 𝑑𝑣𝑑𝑡 triggering
4. Light triggering
5. Temperature triggering

1. Forward voltage triggering

A forward voltage is applied between anode and cathode with gate circuit open.

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Junction 𝐽1 and 𝐽3 is forward biased.

Juntion 𝐽2 is reverse biased.
As the anode to cathode voltage is increased breakdown of the reverse biased junction 𝐽2
occurs. This is known as avalanche breakdown and the voltage at which this phenomena occurs
is called forward breakover voltage.
The conduction of current continues even if the anode cathode voltage reduces below 𝑉𝐵𝑂till
𝐼𝑎 will not go below𝐼ℎ. Where 𝐼ℎ is the holding current for the thyristor.

2. Gate triggering
This is the simplest, reliable and efficient method of firing the forward biased SCRs. First SCR is
forward biased. Then a positive gate voltage is applied between gate and cathode. In practice the
transition from OFF state to ON state by exceeding 𝑉𝐵𝑂 is never employed as it may destroy the
device. The magnitude of 𝑉𝐵𝑂, so forward breakover voltage is taken as final voltage rating of
the device during the design of SCR application.
First step is to choose a thyristor with forward breakover voltage (say 800V) higher than the
normal working voltage. The benefit is that the thyristor will be in blocking state with normal
working voltage applied across the anode and cathode with gate open. When we require the
turning ON of a SCR a positive gate voltage between gate and cathode is applied. The point to be
noted that cathode n- layer is heavily doped as compared to gate p-layer. So when gate supply is
given between gate and cathode gate p-layer is flooded with electron from cathode n-layer. Now
the thyristor is forward biased, so some of these electron reach junction 𝐽2 .As a result width of
𝐽2 breaks down or conduction at 𝐽2 occur at a voltage less than 𝑉𝐵𝑂.As 𝐼𝑔 increases 𝑉𝐵𝑂
reduces which decreases then turn ON time. Another important point is duration for which the
gate current is applied should be more then turn ON time. This means
that if the gate current is reduced to zero before the anode current reaches a minimum value
known as holding current, SCR can’t turn ON.
In this process power loss is less and also low applied voltage is required for triggering.
3. dv/dt triggering

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This is a turning ON method but it may lead to destruction of SCR and so it must be avoided.
When SCR is forward biased, junction 𝐽1 and 𝐽3 are forward biased and junction 𝐽2 is reversed
biased so it behaves as if an insulator is place between two conducting plate. Here 𝐽1 and 𝐽3 acts
as a conducting plate and 𝐽2 acts as an insulator. 𝐽2 is known as junction capacitor. So if we
increase the rate of change of forward voltage instead of increasing the magnitude of voltage.
Junction 𝐽2 breaks and starts conducting. A high value of changing current may damage the
SCR. So SCR may be protected from high𝑑𝑣𝑑𝑡.
𝑞=𝑐𝑣
𝐼𝑎=𝑐𝑑𝑣𝑑𝑡
𝐼𝑎 𝛼 𝑑𝑣𝑑𝑡
4. Temperature triggering

During forward biased, 𝐽2 is reverse biased so a leakage forward current always associated with
SCR. Now as we know the leakage current is temperature dependant, so if we increase the
temperature the leakage current will also increase and heat dissipitation of junction 𝐽2occurs.
When this heat reaches a sufficient value 𝐽2 will break and conduction starts.
Disadvantages
This type of triggering causes local hot spot and may cause thermal run away of the device.
This triggering cannot be controlled easily.
It is very costly as protection is costly.
5. Light triggering

First a new recess niche is made in the inner p-layer. When this recess is irradiated, then free
charge carriers (electron and hole) are generated. Now if the intensity is increased above a
certain value then it leads to turn ON of SCR. Such SCR are known as Light activated SCR
(LASCR).
Some definitions:
Latching current
The latching current may be defined as the minimum value of anode current which at must attain
during turn ON process to maintain conduction even if gate signal is removed.
Holding current
It is the minimum value of anode current below which if it falls, the SCR will turn OFF.
Switching characteristics of thyristors
The time variation of voltage across the thyristor and current through it during turn on and turn
off process gives the dynamic or switching characteristic of SCR.
Switching characteristic during turn on
Turn on time
It is the time during which it changes from forward blocking state to ON state. Total turn on time
is divided into 3 intervals:
1. Delay time
2. Rise time
3. Spread time

Delay time

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If 𝐼𝑔and 𝐼𝑎 represent the final value of gate current and anode current. Then the delay time can
be explained as time during which the gate current attains 0.9 𝐼𝑔 to the instant anode current
reaches 0.1 𝐼𝑔 or the anode current rises from forward leakage current to 0.1 𝐼𝑎.
1. Gate current 0.9 𝐼𝑔 to 0.1 𝐼𝑎.
2. Anode voltage falls from 𝑉𝑎 to 0.9𝑉𝑎.
3. Anode current rises from forward leakage current to 0.1 𝐼𝑎.
Rise time (𝒕𝒓)
Time during which
1. Anode current rises from 0.1 𝐼𝑎 to 0.9 𝐼𝑎
2. Forward blocking voltage falls from 0.9𝑉𝑎 to 0.1𝑉𝑎. 𝑉𝑎 is the initial forward blocking
voltage.

Spread time (𝒕𝒑)

1. Time taken by the anode current to rise from 0.9𝐼𝑎 to𝐼𝑎.
2. Time for the forward voltage to fall from 0.1𝑉𝑜 to on state voltage drop of 1 to 1.5V. During
turn on, SCR is considered to be a charge controlled device. A certain amount of charge is
injected in the gate region to begin conduction. So higher the magnitude of gate current it
requires less time to inject the charges. Thus turn on time is reduced by using large magnitude of
gate current.
How the distribution of charge occurs?
As the gate current begins to flow from gate to cathode with the application of gate signal. Gate
current has a non uniform distribution of current density over the cathode surface. Distribution of
current density is much higher near the gate. The density decrease as the distance from the gate
increases. So anode current flows in a narrow region near gate where gate current densities are
highest. From the beginning of rise time the anode current starts spreading itself. The anode
current spread at a rate of 0.1mm/sec. The spreading anode current requires some time if the rise
time is not sufficient then the anode current cannot spread over the entire region of cathode. Now
a large anode current is applied and also a large anode current flowing through the SCR. As a
result turn on losses is high. As these losses occur over a small conducting region so local hot
spots may form and it may damage the device.
Switching Characteristics During Turn Off
Thyristor turn off means it changed from ON to OFF state. Once thyristor is oON there is no role
of gate. As we know thyristor can be made turn OFF by reducing the anode current below the
latching current. Here we assume the latching current to be zero ampere. If a forward voltage is
applied across the SCR at the moment it reaches zero then SCR will not be able to block this
forward voltage. Because the charges trapped in the 4-layer are still favourable for conduction
and it may turn on the device. So to avoid such a case, SCR is reverse biased for some time even
if the anode current has reached to zero.
So now the turn off time can be different as the instant anode current becomes zero to the instant
when SCR regains its forward blocking capability.
𝑡𝑞=𝑡𝑟𝑟+𝑡𝑞𝑟
Where,
𝑡𝑞 is the turn off time, is the reverse recovery time, 𝑡𝑞𝑟 is the gate recovery time
At 𝑡1 anode current is zero. Now anode current builds up in reverse direction with same 𝑑𝑣𝑑𝑡
slope. This is due to the presence of charge carriers in the four layers. The reverse recovery
current removes the excess carriers from 𝐽1 and 𝐽3 between the instants 𝑡1 and𝑡3. At instant 𝑡3

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the end junction 𝐽1 and 𝐽3 is recovered. But 𝐽2 still has trapped charges which decay due to
recombination only so the reverse voltage has to be maintained for some more time. The time
taken for the recombination of charges between 𝑡3 and 𝑡4 is called gate recovery time 𝑡𝑞𝑟.
Junction 𝐽2 recovered and now a forward voltage can be applied across SCR.
The turn off time is affected by:
1. Junction temperature
2. Magnitude of forward current 𝑑𝑖𝑑𝑡 during commutation.
Turn off time decreases with the increase of magnitude of reverse applied voltage.

Turn on methods of SCR

The turning on Process of the SCR is known as Triggering. In other words, turning the SCR from
Forward-Blocking state to Forward-Conduction state is known as Triggering. The
various methods of SCR triggering are discussed here.
The various SCR triggering methods are
Forward Voltage Triggering
Thermal or Temperature Triggering
Radiation or Light triggering
dv/dt Triggering
Gate Triggering
(a) Forward Voltage Triggering:-
In this mode, an additional forward voltage is applied between anode and cathode.
When the anode terminal is positive with respect to cathode (VAK), Junction J1 and J3 is
forward

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biased and junction J2 is reverse biased.
No current flow due to depletion region in J2 is reverse biased (except leakage current).
As VAK is further increased, at a voltage VBO (Forward Break Over Voltage) the junction J2
undergoes avalanche breakdown and so a current flows and the device tends to turn ON(even
when gate is open)
(b) Thermal (or) Temperature Triggering:-
The width of depletion layer of SCR decreases with increase in junction temperature.
Therefore in SCR when VAR is very near its breakdown voltage, the device is triggered by
increasing
the junction temperature.
By increasing the junction temperature the reverse biased junction collapses thus the device
starts to
conduct.
(c) Radiation Triggering (or) Light Triggering:-
For light triggered SCRs a special terminal niche is made inside the inner P layer instead of
gate
terminal.
When light is allowed to strike this terminal, free charge carriers are generated.
When intensity of light becomes more than a normal value, the thyristor starts conducting.
This type of SCRs are called as LASCR
(d) dv/dt Triggering:-
When the device is forward biased, J1 and J3 are forward biased, J2 is reverse biased.
Junction J2 behaves as a capacitor, due to the charges existing across the junction.
If voltage across the device is V, the charge by Q and capacitance by C then,
ic =dQ/dt
Q=CV
ic =d(CV)/dt
=CdV/dt+VdC/dt
as dC/dt = 0
ic = CdV/dt
Therefore when the rate of change of voltage across the device becomes large, the device may
turn
ON, even if the voltage across the device is small.
(e) Gate Triggering:-
This is most widely used SCR triggering method.
Applying a positive voltage between gate and cathode can Turn ON a forward biased thyristor.
When a positive voltage is applied at the gate terminal, charge carriers are injected in the inner
P-
layer, thereby reducing the depletion layer thickness.
As the applied voltage increases, the carrier injection increases, therefore the voltage at which
forward break-over occurs decreases.

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Three types of signals are used for gate triggering.

1. DC gate triggering:-
A DC voltage of proper polarity is applied between gate and cathode ( Gate terminal is
positive with
respect to Cathode).
When applied voltage is sufficient to produce the required gate Current, the device starts
conducting.
One drawback of this scheme is that both power and control circuits are DC and there is no
isolation
between the two.
Another disadvantage is that a continuous DC signal has to be applied. So gate power loss is
high.
2. AC Gate Triggering:-
Here AC source is used for gate signals.
This scheme provides proper isolation between power and control circuit.
Drawback of this scheme is that a separate transformer is required to step down ac supply.
There are two methods of AC voltage triggering namely (i) R Triggering (ii) RC
triggering
(i) Resistance triggering:
The following circuit shows the resistance triggering.

Resistance triggering circuit of SCR

In this method, the variable resistance R is used to control the gate current.
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Depending upon the value of R, when the magnitude of the gate current reaches the sufficient
value(latching current of the device) the SCR starts to conduct.
The diode D is called as blocking diode. It prevents the gate cathode junction from getting
damaged
in the negative half cycle.
By considering that the gate circuit is purely resistive, the gate current is in phase with the
applied
voltage.
By using this method we can achieve maximum firing angle up to 90°.
(ii) RC Triggering
The following circuit shows the resistance-capacitance triggering.

Resistance Capacitance triggering circuit of SCR

By using this method we can achieve firing angle more than 90°.
In the positive half cycle, the capacitor is charged through the variable resistance R up to the
peak
value of the applied voltage.
The variable resistor R controls the charging time of the capacitor.
Depends upon the voltage across the capacitor, when sufficient amount of gate current will
flow in
the circuit, the SCR starts to conduct.
In the negative half cycle, the capacitor C is charged up to the negative peak value through the
diode D2.
Diode D1 is used to prevent the reverse break down of the gate cathode junction in the
negative half
cycle.
3. Pulse Gate Triggering:-
In this method the gate drive consists of a single pulse appearing periodically (or) a sequence
of
high frequency pulses.
This is known as carrier frequency gating.
A pulse transformer is used for isolation.
The main advantage is that there is no need of applying continuous signals, so the gate losses
are
reduced.
Advantages of pulse train triggering:
Low gate dissipation at higher gate current.

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Small gate isolating pulse transformer
Low dissipation in reverse biased condition is possible. So simple trigger circuits are possible
in
some cases
When the first trigger pulse fails to trigger the SCR, the following pulses can succeed in
latching
SCR. This important while
Triggering inductive circuits and circuits having back emf's.
Turn off methods of SCR:
SCR can be turned ON by applying appropriate positive gate voltage between the gate and
cathode
terminals, but it cannot be turned OFF through the gate terminal. The SCR can be
brought back to the
forward blocking state from the forward conduction state by reducing the anode or forward
current below
the holding current level.
The turn OFF process of an SCR is called commutation. The term commutation means the
transfer of
currents from one path to another. So the commutation circuit does this job by reducing the
forward
current to zero so as to turn OFF the SCR or Thyristor.
To turn OFF the conducting SCR the below conditions must be satisfied.
The anode or forward current of SCR must be reduced to zero or below the level of holding
current and then,
A sufficient reverse voltage must be applied across the SCR to regain its forward blocking
state.
When the SCR is turned OFF by reducing forward current to zero there exist excess charge
carriers in
different layers. To regain the forward blocking state of an SCR, these excess carriers must be
recombined. Therefore, this recombination process is accelerated by applying a reverse voltage
across the
SCR.
SCR Turn OFF Methods
The reverse voltage which causes to commutate the SCR is called commutation voltage.
Depending on
the commutation voltage located, the commutation methods are classified into two major types.
Those are 1) Forced commutation and 2) Natural commutation. Let us discuss in brief about
these
methods.
Forced Commutation
In case of DC circuits, there is no natural current zero to turn OFF the SCR. In such circuits,
forward
current must be forced to zero with an external circuit to commutate the SCR hence named as
forced
commutation.

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This commutating circuit consists of components like inductors and capacitors called as
commutating
components. These commutating components cause to apply a reverse voltage across the SCR
that
immediately bring the current in the SCR to zero.
Based on the manner in which the zero current achieved and arrangement of the commutating
components, forced commutation is classified into different types such as class A, B, C, D, and
E. This
commutation is mainly used in chopper and inverter circuits.
Class A Commutation
This is also known as self commutation, or resonant commutation, or load commutation. In this
commutation, the source of commutation voltage is in the load. This load must be an under
damped R-L-
C supplied with a DC supply so that natural zero is obtained.
The commutating components L and C are connected either parallel or series with the load
resistance R as
shown below with waveforms of SCR current, voltage and capacitor voltage.

Class A Commutation circuit and waveforms

The value of load resistance and commutating components are so selected that they forms a
under damped
resonant circuit to produce natural zero. When the thyristor or SCR is triggered, the forward
currents
starts flowing through it and during this the capacitor is charged up to the value of E.
Once the capacitor is fully charged (more than the supply source voltage) the SCR becomes
reverse
biased and hence the commutation of the device. The capacitor discharges through the load
resistance to
make ready the circuit for the next cycle of operation. The time for switching OFF the SCR
depends on
the resonant frequency which further depends on the L and C components.
This method is simple and reliable. For high frequency operation which is in the range above
1000 Hz,

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this type of commutation circuits is preferred due to the high values of L and C components.

Class B Commutation
This is also a self commutation circuit in which commutation of SCR is achieved automatically
by L and
C components, once the SCR is turned ON. In this, the LC resonant circuit is connected across
the SCR
but not in series with load as in case of class A commutation and hence the L and C components
do not
carry the load current.

Class B Commutation circuit and waveforms

When the DC supply is applied to the circuit, the capacitor charges with an upper plate positive
and lower
plate negative up to the supply voltage E. When the SCR is triggered, the current flows in two
directions,
one is through E+ – SCR – R – E- and another one is the commutating current through L and C
components.
Once the SCR is turned ON, the capacitor is starts discharging through C+ – L – T – C-. When
the
capacitor is fully discharged, it starts charging with a reverse polarity. Hence a reverse voltage
applied
across the SCR which causes the commutating current IC to oppose load current IL.
When the commutating current Ic is higher than the load current, the SCR will automatically turn
OFF
and the capacitor charges with original polarity.

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In the above process, the SCR is turned ON for some time and then automatically turned OFF for
some
time. This is a continuous process and the desired frequency of ON/OFF depends on the values
of L and
C. This type of commutation is mostly used in chopper circuits.
Class C Commutation
In this commutation method, the main SCR is to be commutated is connected in series with the
load and
an additional or complementary SCR is connected in parallel with main SCR. This method is
also called
as complementary commutation.
In this , SCR turns OFF with a reverse voltage of a charged capacitor. The figure below shows
the
complementary commutation with appropriate waveforms

Class C Commutation circuit and waveforms

Initially, both SCRs are in OFF state so the capacitor voltage is also zero. When the SCR1 or
main SCR is
triggered, current starts flowing in two directions, one path is E+ – R1 – SCR1 – E- and another
path is
the charging current E+ – R2- C+ – C- SCR1 – E- . Therefore, the capacitor starts charging up to
the
value of E.
When the SCR2 is triggered, SCR is turned ON and simultaneously a negative polarity is applied
across
the SCR1. So this reverse voltage across the SCR1 immediately causes to turn OFF the SCR1.
Now the

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capacitor starts charging with a reverse polarity through the path of E+ – R1- C+ – C- SCR2 – E-
. And
again, if the SCR 1 is triggered, discharging current of the capacitor turns OFF the SCR2.
This commutation is mainly used in single phase inverters with a centre tapped transformers. The
Mc
Murray Bedford inverter is the best example of this commutation circuit. This is a very reliable
method of
commutation and it is also useful even at frequencies below 1000Hz.
Class D Commutation
This is also called as auxiliary commutation because it uses an auxiliary SCR to switch the
charged
capacitor. In this, the main SCR is commutated by the auxiliary SCR. The main SCR with load
resistance
forms the power circuit while the diode D, inductor L and SCR2 forms the commutation
circuit

Class D Commutation circuit and waveforms

When the supply voltage E is applied, both SCRs are in OFF state and hence the capacitor
voltage is zero.
In order to charge the capacitor, SCR2 must be triggered first. So the capacitor charges through
the path
E+ – C+ – C- – SCR2- R- E-.
When the capacitor is fully charged the SCR2 becomes turned OFF because no current flow
through the

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SCR2 when capacitor is charged fully. If the SCR1 is triggered, the current flows in two
directions; one is
the load current path E+ – SCR1- R- E- and another one is commutation current path C+ –
SCR1- L- D-
C.
As soon as the capacitor completely discharges, its polarities will be reversed but due to the
presence of
diode the reverse discharge is not possible. When the SCR2 is triggered capacitor starts
discharging
through C+ – SCR2- SCR1- C-. When this discharging current is more than the load current the
SCR1
becomes turned OFF.
Again, the capacitor starts charging through the SCR2 to a supply voltage E and then the SCR2
is turned
OFF. Therefore, both SCRs are turned OFF and the above cyclic process is repeated. This
commutation
method is mainly used in inverters and also used in the Jones chopper circuit.
Class E Commutation
This is also known as external pulse commutation. In this, an external pulse source is used to
produce the
reverse voltage across the SCR. The circuit below shows the class E commutation circuit which
uses a
pulse transformer to produce the commutating pulse and is designed with tight coupling between
the
primary and secondary with a small air gap.
If the SCR need to be commutated, pulse duration equal to the turn OFF time of the SCR is
applied.
When the SCR is triggered, load current flows through the pulse transformer. If the pulse is
applied to the
primary of the pulse transformer, an emf or voltage is induced in the secondary of the pulse
transformer.
This induced voltage is applied across the SCR as a reverse polarity and hence the SCR is turned
OFF.
The capacitor offers a very low or zero impedance to the high frequency pulse.

Class E Commutation circuit and waveforms

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Natural Commutation
In natural commutation, the source of commutation voltage is the supply source itself. If the SCR
is
connected to an AC supply, at every end of the positive half cycle the anode current goes through
the
natural current zero and also immediately a reverse voltage is applied across the SCR. These are
the
conditions to turn OFF the SCR.
This method of commutation is also called as source commutation, or line commutation, or class
F
commutation. This commutation is possible with line commutated inverters, controlled rectifiers,
cyclo
converters and AC voltage regulators because the supply is the AC source in all these
converters.

Natural Commutation circuit and waveforms

Dynamic Turn OFF Switching Characteristics
The transition of an SCR from forward conduction state to forward blocking state is called as
turn OFF or
commutation of SCR. As we know that once the SCR starts conducting, the gate has no control
over it to
bring back to forward blocking or OFF state.
To turn OFF the SCR, the current must be reduced to a level below the holding current of SCR.
We have
discussed various methods above to turn OFF the SCR in which SCR turn OFF is
achieved by reducing
the forward current to zero. But if we apply the forward voltage immediately after the current
zero of
SCR, it starts conducting again even without gate triggering.
This is due to the presence of charge carriers in the four layers. Therefore, it is necessary to apply
the

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reverse voltage, over a finite time across the SCR to remove the charge carriers.
Hence the turn OFF time is defined as the time between the instant the anode current becomes
zero and
the instant at which the SCR retains the forward blocking capability. The excess charge carriers
from the
four layers must be removed to bring back the SCR to forward conduction mode.
This process takes place in two stages. In a first stage excess carriers from outer layers are
removed and in
second stage excess carriers in the inner two layers are to be recombined. Hence, the total turn
OFF time
tq is divided into two intervals; reverse recovery time trr and gate recovery time tgr.
tq = trr + tgr
The figure below shows the switching characteristics of SCR during turn ON and OFF. The time
t1 to t3 is
called as reverse recovery time; at the instant t1the anode current is zero and builds up in the
reverse
direction which is called as reverse recovery current. This current removes the excess charge
carriers from
outer layers during the time t1 to t3.
At instant t3, junctions J1 and J3 are able to block the reverse voltage but, the SCR is not yet able
to block
the forward voltage due to the presence of excess charge carriers in junction J2. These carriers
can be

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disappeared only by the way of recombination and this could be achieved by maintaining a
reverse voltage across the SCR.

Dynamic characteristics of SCR

Hence , during the time t3 to t4, the recombination of charges takes place and at the instant t4,
junction
J2 completely recovers. This time is called gate recovery time tgr.
From the figure the turn OFF time is the time interval between the t4 and t1. Generally, this
time
varies from 10 to 100 microseconds. This turn OFF time tq is applicable to the individual SCR.
The time required by the commutation circuit to apply the reverse voltage to commutate the
SCR
is called the circuit turn OFF time (tc). For a safety margin or reliable commutation, this tc must

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be greater than the tq otherwise commutation failure occurs.
The SCRs which have slow turn OFF time as in between 50 to 100 microseconds are called as
converter grade SCRs. These are used in phase controlled rectifiers, cyclo converters, AC
voltage
regulators, etc.
The SCRs which have fast turn OFF time as in between 3 to 50 microseconds are inverter
grade
SCRs. These are costlier compared to converter grade and are used in choppers, force
commutated converters and inverters.

GTO:

Symbol of GTO
Overall switching speed of GTO is faster than thyristor (SCR) but voltage drop of GTO is larger.
The
power range of GTO is better than BJT, IGBT or SCR.
The static voltage current characteristics of GTO are similar to SCR except that the latching
current of
GTO is larger (about 2 A) as compared to SCR (around 100-500 mA).

Gate Drive Circuit for GTO

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Switching characteristics for GTO

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COMPARISION TABLE:

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NEED OF GATE/BASE DRIVE CIRCUITS :

DRIVE CIRCUITS FOR BJT:

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GTO gate drive circuit

A GTO gate drive has to fulfill the following functions.

• Turn the GTO on by means of a high current pulse (IGM)

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• Maintain conduction through provision of a continuous gate current (IG, also known
asthe “back-porch current”).

• Turn the GTO off with a high negative gate current pulse.
• Reinforce the blocking state of the device by a negative gate voltage.

WHAT IS GALLIUM NITRIDE?

Gallium Nitride is a binary III/V direct bandgap semiconductor that is well-suited for high-power transistors
capable of operating at high temperatures. Since the 1990s, it has been used commonly in light emitting diodes
(LED). Gallium nitride gives off a blue light used for disc-reading in Blu-ray. Additionally, gallium nitride is
used in semiconductor power devices, RF components, lasers, and photonics. In the future, we will see GaN in
sensor technology.

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In 2006, enhancement-mode GaN transistors, sometimes referred to as GaN FETs, started being manufactured
by growing a thin layer of GaN on the AIN layer of a standard silicon wafer using metal organic chemical
vapor deposition (MOCVD). The AIN layer acts as a buffer between the substrate and GaN.
This new process enabled gallium nitride transistors to be producible in the same existing factories as silicon,
using almost the same manufacturing processes. By using a known process, this allows for similar, low
manufacturing costs and reduces the barrier to adoption for smaller transistors with much improved
performance.

To further explain, all semiconductor materials have what is called a bandgap. This is an energy range in a
solid where no electrons can exist. Simply put, a bandgap is related to how well a solid material can conduct
electricity. Gallium nitride has a 3.4 eV bandgap, compared to silicon’s 1.12 eV bandgap. Gallium nitride’s
wider band gap means it can sustain higher voltages and higher temperatures than silicon MOSFETs. This
wide bandgap enables gallium nitride to be applied to optoelectronic high-power and high-frequency devices.

The ability to operate at much higher temperatures and voltages than gallium arsenide (GaAs) transistors also
makes gallium nitride ideal power amplifiers for microwave and terahertz (ThZ) devices, such as imaging and
sensing, the future market mentioned above

THE MAJOR OF ADVANTAGES OF GAN:

 Reduced Weight

 Reduced Size

 Reduced Costs

 Increased Energy Efficiency

ADVANTAGES OF GALLIUM NITRIDE

The value proposition for GaN devices consists of four major points:
1. Reduced energy costs – Because GaN semiconductors are inherently more efficient than silicon, less
energy is expended as heat, resulting in smaller system sizes and material costs.
2. Higher power density (smaller volume) – Higher switching frequencies and operational
temperatures than silicon result in lower cooling requirements, smaller heat sinks, conversion from liquid-
cooling to air cooling, eliminating fans and reduced magnetics.
3. Higher switching frequency – The higher switching frequencies for GaN devices allows smaller
inductors and capacitors to be used in power circuits. The inductance and capacitance scale down in
proportion to the frequency – a 10X increase in frequency produces a 10X decrease in the capacitance and
inductance. This can result in an enormous decrease in weight and volume, as well as cost. In addition,
higher frequency can result in less acoustic noise in motor drive applications. High frequency also enables
wireless power transfer at higher powers, more spatial freedom and bigger transmit to receive airgaps.
4. Lower system cost – While GaN semiconductors are generally higher cost than silicon, system level
cost reductions result through the use of GaN by reducing the size/costs of other components such as
passive inductive and capacitive circuit elements, filters, cooling, etc. Savings range from 10-20%.

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Gallium Nitride is a wide-bandgap semiconductor that possesses exceptional material

properties, such as its high breakdown electric field and high electron mobility, that make it
suitable for use in power switching devices. For medium voltage applications (roughly
defined here as 1.2 to 20 kV), vertical device architectures may be the most suitable.

What is silicon carbide devices?

Silicon carbide (SiC) is a semiconductor material with a high electric breakdown field, saturated
electron velocity, and thermal conductivity, compared to silicon (Si).

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What are the advantages of SiC power devices over the Si power devices?
SiC will soon overtake Si as the dominant semiconductor material for power devices with voltage rating
higher than 600V. Its key benefits include delivering higher voltage operation, wider temperature
ranges and increased switching frequencies when compared to existing Si technology.

What is the advantage of GaN over SiC?

GaN's switching energy is more than 50% lower than SiC, which directly translates to lower losses in
the PFC stage. It is possible to achieve switching frequencies greater than 1 MHz in critical model totem-
pole applications. Faster switching speeds.

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