OBJECTIVE:
The objective of this project is to design and implement a fully functional digital clock using
Verilog hardware description language (HDL). The digital clock will display hours, minutes, and
seconds in a 24-hour format. The design should accurately keep time, using a clock signal as a
timing reference. Key features include the ability to reset the clock to an initial time and increment
the time with each clock pulse. The primary aim is to explore how sequential logic and finite state
machines (FSM) can be employed in Verilog to create a real-time clock, demonstrating proficiency
in digital design techniques and HDL coding. This project also serves to provide insights into the
synthesis and simulation of Verilog code for real-world timekeeping applications.
SOFTWARE DETAILS:
The software used here Xilinx Ise 14.7. Xilinx ISE is a design suite for FPGA (Field Programmable
Gate Array) and CPLD (Complex Programmable Logic Device) development.It is used for
designing, simulating, and synthesizing digital circuits using HDL (Hardware Description
Languages) such as Verilog and VHDL. It supports the complete design flow from RTL design
and functional simulation to synthesis, implementation, and timing simulation.
Some of the features are :
• HDL Support: Full support for Verilog and VHDL coding.
• Synthesis and Implementation: Converts HDL code into a gate-level netlist for FPGAs and
CPLDs.
• Design Simulation: Integrated simulation tools such as ISim for functional and timing
simulation.
• Timing Analysis: Tools for timing constraint checking and optimization to meet design
requirements.
• Device Support: Supports older Xilinx FPGA families (Spartan, Virtex, and some Kintex and
Artix series).
• IP Cores: Access to a variety of Intellectual Property (IP) cores for adding predefined
functionalities to FPGA designs.
Abstract:
This project presents the design and implementation of a digital clock using Verilog, a hardware
description language (HDL) widely used for digital circuit design. The clock is designed to display
real-time hours, minutes, and seconds in a 24-hour format. The system leverages the principles of
sequential logic, dividing the input clock signal to generate time units and using counters to track
seconds, minutes, and hours. The design includes reset functionality and the ability to accurately
update the time with every clock pulse. Verilog’s modular structure is utilized to create components
such as dividers, counters, and multiplexers to build the clock. This project demonstrates how
Verilog can be used to implement complex digital systems on FPGA platforms, showcasing
simulation, synthesis, and testing of the digital clock in a hardware environment. The digital clock
serves as a practical application of FSMs (Finite State Machines) and clock signal manipulation,
providing insights into the development of real-time embedded systems using HDL.
Block Diagram/Logic Diagram:
Code:
module clock(
input Clk_1sec, // Clock with 1 Hz frequency
input reset, // Active high reset
output reg [5:0] seconds,
output reg [5:0] minutes,
output reg [4:0] hours
);
// Execute the always block on the positive edge of the clock or reset
always @(posedge Clk_1sec or posedge reset)
begin
if (reset) begin // Check for active high reset
// Reset the time
seconds <= 0;
minutes <= 0;
hours <= 0;
end else begin
// At the beginning of each second
seconds <= seconds + 1;
if (seconds == 60) begin // Check for max value of sec
seconds <= 0; // Reset seconds
minutes <= minutes + 1; // Increment minutes
if (minutes == 60) begin // Check for max value of min
minutes <= 0; // Reset minutes
hours <= hours + 1; // Increment hours
if (hours == 24) begin // Check for max value of hours
hours <= 0; // Reset hours
end
end
end
end
end
endmodule
Testbench:
module clock_tb_v;
// Inputs
reg Clk_1sec;
reg reset;
// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
// Instantiate the Unit Under Test (UUT)
clock uut (
.Clk_1sec(Clk_1sec),
.reset(reset),
.seconds(seconds),
.minutes(minutes),
.hours(hours)
);
// Clock generation
initial begin
Clk_1sec = 0;
forever #5 Clk_1sec = ~Clk_1sec; // 100MHz clock
end
// Test stimulus
initial begin
// Initialize reset
reset = 1; // Assert reset
#10;
reset = 0; // Deassert reset
// Run the simulation for a while
#100000; // Run for 100 ms (simulate for a while)
// Finish the simulation
$finish;
end
// Monitor outputs
initial begin
$monitor("Time: %0t | Hours: %d | Minutes: %d | Seconds: %d",
$time, hours, minutes, seconds);
end
endmodule
Wave form:
Result:
A 24 hour digital clock is successfully programmed and implemented.
Conclusion:
The design and implementation of a digital clock using Verilog successfully demonstrate the
capability of hardware description languages for creating real-time embedded systems. Through
the use of modular components such as clock dividers, counters, and a 7-segment display
controller, we were able to design a functional clock that accurately tracks and displays hours,
minutes, and seconds in a 24-hour format. This project provides hands-on experience with
sequential logic, finite state machines (FSMs), and clock signal management, which are essential
concepts in digital design. The successful simulation and synthesis of the clock design show the
effectiveness of Verilog for creating complex digital systems that can be implemented on FPGA
hardware. This project lays the foundation for further exploration into more advanced timing
systems and embedded applications.
