Lecture 3
Lithography, Part-II
GCE 6601: Micro and Nano Fabrication of Ceramics
Dr. Redwan Noor Sajjad
Associate Professor
Department of Nanomaterials and Ceramic Engineering
Bangladesh University of Engineering and Technology
[email protected] sites.google.com/view/redwansajjad
July 6, 2025
1
Microprocessor technology overview
Integrated Circuit (IC)/Microprocesor technology
Microprocessors perform operations using boolean logic (binary).
Logic gates, such as inverters, NAND, NOR implement all
operations.
Transistors - which are basically ON/OFF switches - are the
building blocks of logic gates
Transistors are logic gates are fabricated on silicon wafer, which is
a single crystal
The production of IC technology - from sand to chip - is a
multi-disciplinary field involving EE, MSE, CSE, CHE/chemistry,
physics, IPE.
2
Microprocessor technology overview
CMOS inverter
Only one transistor is turned ON at a time - low power consumption
compared to previous technology. Hence the name Complementary-
MOS or CMOS technology.
3
Microprocessor technology overview
CMOS inverter
4
CMOS process flow
Initial steps before active region formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Wafer cleaning (substrate about 500 µm.
Thermal oxidation (about 40 nm, 15 min at 900 o C in H2 0
atmosphere)
Nitride deposition using LPCVD (80 nm, 800 o C).
3SiH4+4NH3 - > Si3N4+12H2.
Photoresist spinning (about 1 µm). 5
CMOS process flow
How photoresists work
These are organic materials (example: PMMA -polymethylmethacrylate) that
change their chemical structure upon the exposure with UV light.
Positive photoresists become soluble to developing solution after exposure.
Unexposed areas remain insensitive to the solution.
After exposure, the wafer is submersed in the developing solution which washes
away the soluble parts. The pattern in the mask is now transferred onto the
wafer (right figure).
At this stage, certain areas (where the photoresist have been washed away) of
the wafer is ready to be etched/doped/deposition or any other processes.
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CMOS process flow
Active region formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Pattern the active areas
Nitride is etched with the resist as a mask. Si3N4+12F - >
3SiF4+2N2
Remaining photoresist is removed by sulfuric acid, which does not
attack Si3N4 or SiO2 layers. 7
CMOS process flow
Active region formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Oxide is grown to isolate two devices - p and n.
Oxidation takes place in a furnace - 1000 o C for 90 min in H2O will
grow about 500 nm of SiO2.
Nitride layer prohibits growth of oxide in the areas where we do
not want the oxide. Local oxidation or LOCOS process.
Nitride layer then stripped using the reaction shown before. 8
CMOS process flow
N and P well formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Photoresist is spun
Mask is used to expose photoresist in certain areas, then stripped
away
Remaining photoresist blocks implanation
Boron implantation to create p-well. Phosphorous implantation to
create n-well. Required doping density around 1016 -1017 cm 3 .
Optimum implantation energy 9
CMOS process flow
Implant repair
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Temperature at 1000-1100 o C, 4-6 hours.
Produce final well depth (diffusion of dopants), 2-3 µm
Repairs implant damage by recreating bonds, restores substrate
crystallinity.
10
CMOS process flow
Threshold voltage adjust
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Doping the channel region for adjustment of carrier density for
both n and p wells
Boron for p doping and arsenic for n doping
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CMOS process flow
Gate oxide growth
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Thin oxide layer is stripped with selective etching (HF solution)
HF will stop etching at silicon
Need to time properly so that it does not etch the field oxide too
much
New oxide layer (gate oxide) is grown (10 nm range, needs to be
precise), 1-2 hours at 800 o C in O2. 12
CMOS process flow
Polysilicon deposition
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Polysilicon acts as the gate electrode, which makes good
interface with the underlying SiO2
Using LPCVD, a layer of polysilicon is deposited over the entire
wafer. Thermal decomposition of silane (SiH4) produces 0.3-0.5
um thick at 600 o C.
Polysilicon doped n type by an unmasked ion implant. Doping
density - 5⇥1015 cm 2 to lower resistivity. 13
CMOS process flow
Polysilicon etching
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Need to keep the polysilicon layer only over the gate region. Need
to etch away the remaining.
Two desired properties of etching - selectivity and degree of
anisotropy. Need to etch poly-Si, not SiO2. Plasma/dry etching
using ionized gases provides the best solution.
14
CMOS process flow
LDD formation
Reduced N gradient – smaller electric field near drain – fewer “hot” elec-
trons into oxide.
15
CMOS process flow
LDD formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Lightly doped regions are produced to avoid short channel effects.
Region near the channel is doped with n- for p well and p- for n
well.
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CMOS process flow
Sidewall space formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Goal is to push the heavily doped regions (source and drain) away
from the channel
SiH4+O2 will deposit SiO2 layer to form the sidewall spacer in at
400 o C a furnace configured as LPCVD.
Anisotropic etching leaves sidewall spacers along the edges of
the poly gates
Anisotropic vertical etching using flourine based plasma.
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CMOS process flow
Source and drain region formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Mask protects the pmos devices as n+ implant forms the nmos
source and drain regions (with as implantation) and similarly p+
source and drain regions.
Sidewall ensures n+ regions are slightly moved away from the
channel region (p- region for the nmos)
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CMOS process flow
Final device formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
A final high temperature annealing drives-in the junctions and
repairs implant caused damages - typically 30 min at 900 o C or 1
min RTA at 1000 - 1050 o C.
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CMOS process flow
Contact formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
An unmasked oxide etch removes oxide from the gate, source and
drain regions for the contacts to be deposited.
A short dip in HF solution will etch the oxide layer.
20
CMOS process flow
Contact formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Ti (for contact) is deposited using sputtering, typical thickness
around 50-100 nm.
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CMOS process flow
Contact formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
The wafers are heated in an N2 ambient at about 600-700 o C for a
short time (about 1 minute). Two chemical reactions follow.
Ti+Si2 - > TiS2 (black in this figure) consumes some silicon
underneath Ti and forms excellent contact to both N+ and P+
silicon.
Ti+N2 - > TiN (orange dot) - a good conductor but not as good as
metals. 22
CMOS process flow
Contact formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Mask is used to etch the TiN forming local interconnects/co
Etched in NH4OH:H2O2:H2O (1:1:5).
After photoresist removal, the wafer is heated in an Ar amb
about 800 o C for about a minute to reduce resistivity of TiN
———– 23
CMOS process flow
Contact formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
SiO2 layer deposited using LPCVD followed by chemical
mechanical polishing (CMP).
Planarization (CMP) is needed since metal deposition is not
possible with discontinuities in the topography.
Mask used to define contact holes where we want contacts to be
made.
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CMOS process flow
Contact formation
Ref: Silicon VLSI Technology, Plummer and Griffin (2000)
Deposition of thin TiN (for adhesion) followed by W deposition
using CVD. This metal (pink) acts as a via.
CMP to planarize the wafer. Prepares the surface for the
deposition of level 1 metal.
Metal 1, usually Al is deposited using sputtering in places defined
by another mask.
Multiple levels of metal interconnects necessary to connect all
devices in the wafer. Each level of metallization involves
deposition of oxide, followed by CMP and hole creation using
mask, via deposition and finally another level of metallization. 25
CMOS process flow
Multi-level wiring
26
FinFET structure
Fin-FET
Planar devices do not work well for sub-20 nm channel length
Fins serve as channel in FinFET structure where the gate
surrounds the channel for better gate control
Additional steps necessary to complete fabrication
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FinFET structure
Ref: Yanambaka, Venkata Prasanth
FinFET structure
Assignment-1
Sketch a process flow for the fabrication of FinFET. Provide brief but
sufficient description for each step.
Deadline: July 21, 2025.
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FinFET structure
Reading
Reading
Readingassignment:
Silicon VLSI Technology - Plummer and Griffin (1999)
CMOS process flow - Chapter 2
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