Solved Verification Test Papers
Solved Verification Test Papers
Paper - 1 - Part A
Question 1
Question 2
Question 3
Question 4 // parameter
Paper - 1 - Part B
Question 1
Question 2
Question 3
Question 4
Paper - 2 - Part A
Question 1
Question 2
Question 3
Question 4
Question 5
Paper - 2 - Part B
Question 1
Question 2
Question 3
Paper - 3 - Part A
Question 1
Question 2
Question 3
Question 4
Paper - 3 - Part B
Question 1
Question 2
Question 3
Paper - 4 - Part A
Question 1
Question 2
Question 3
Question 4
Question 5
Paper - 4 - Part B
** Question 1
Question 2
Question 3
Paper - 5 - Part A
Question 1
Paper - 6 - Part A
Question 1
Question 2
Question 3
Question 4
Paper - 7 - Part A
Question 1
Question 2
Question 3
Question 4
Paper - 1 - Part A
Question 1
● This code is actually wrong, when you use $display, it should be within begin end too
after initial.
● Output will be:
● Now, you’d normally expect, since it’s in a fork-join, for the output to be #2 then #3. But
since it’s within a begin-end INSIDE the fork-join, it’s executing sequentially. If we add
time to check timing, we’ll get the following:
● Join_none means the thread will execute irrespective of fork-join threads.
● First, the thread outside the block will execute irrespective of threads inside fork-join
● Then inside fork-join, thread 3 at time 3 (not 1+3=4 as it also starts as 0 simulation time)
will sequentially execute after which thread 2 at time 5 (3+2) will execute.
● Here, after one thread executes, other will.
Question 2
run_test();
Question 3
module
Default clocking;
@posedge (clock);
Endclocking; //applies to all sequences by default
Sequence s1;
$rose(a) |=> b
Endsequence
Sequence s2;
b[*1:$] throughout $fell(c));
Endsequence
Property p1;
@(posedge clock)
s1|->s2;
endproperty
endmodule
Question 4 // parameter
● You can call just the mailbox as an argument but not feasible to call even parameter.
Because mailbox doesn’t act as a datatype, instead give something like int mbx etc.
● Rewrite the code and try to get the item too from the mailbox.
Paper - 1 - Part B
Question 1
● Can’t iterate
● Can’t use distribution
● Can we randomize i value as randc and use it in foreach? [repeat(3) A[i] = 5]
Directly specify three indices of your own and assign 5 for b. Etc….
Question 2
1. First write the interface file with clock declaration, clocking blocks for each agent’s
components and then declare modports.
2. In config file for agent, create a handle for physical interface using virtual keyword.
3. Create handle in driver too using respective driver modport.
4. Get config file and then make connection with local vif and vif in the config file to connect
all signals.
1.
2.
3.
4.
Question 3
Question 4
Paper - 2 - Part A
Question 1
● Declare and give size to the array. Dynamic.
● Randomize data.
● [Link]()
● Display a[i]=data.
Question 2
● Property p;
@(posedge clock)
$stable(a);
@(negedge clock)
$changed(a);
Endproperty
Write two sequences and call in property.
Put them in two diff sequences and call in property.
Question 3
Question 4
Wm, rm and sb. Env build and agent build. Tlmcodes. collect_data() of monitors and
check_phase() in sb.
Read Monitor
Write monitor
Same as read but hand;e for collect data is of wr xtn type.
Scoreboard
Environment
Question 5
[Link]
Paper - 2 - Part B
Question 1
class trans;
rand bit[7:0] data [];
function trans_copy(int data);
copy = new();
$cast(data, data); //(source,destination)
[Link] = [Link];
endfunction
endclass
class packet;
rand int addr;
rand trans t = new();
function packet_copy(int t, addr);
copy = new();
$cast(t, t);
[Link] = [Link];
copy.t = this.t;
endfunction
endclass
packet p1,p2;
initialbegin
p1 = new;
assert([Link]());
p2 = [Link];
end
Question 2
But make it 16 bytes.
interface fifo_intf(input logic clk,rst);
logic [15:0]data_in;
logic wr_en,rd_en;
logic [15:0]data_op;
logic full,empty;
clocking driver_cb@(posedge clk);
default input #1 output #1;
output data_in;
output wr_en,rd_en;
input data_op;
input full,empty;
endclocking
clocking monitor_wcb@(posedge clk);
default input #1 output #1;
input data_in;
input wr_en,rd_en;
input data_op;
input full,empty;
endclocking
clocking monitor_rcb@(posedge clk);
default input #1 output #1;
input data_in;
input wr_en,rd_en;
input data_op;
input full,empty;
endclocking
modport DRIVER (clocking driver_cb,input clk,rst);
modport MONITOR_W (clocking monitor_wcb,input clk,rst);
modport MONITOR_R (clocking monitor_rcb,input clk,rst);
endinterface
Question 3
A) Producer as an initiator and consumer as the target. //general method w/o analogy
class producer extends uvm_component;
uvm_blocking_port #(write_xtn)put_port;
function new (string name,uvm_component parent);
put_port = new ("put_port",this);
endfunction
virtual task run_phase (uvm_phase phase);
write_xtn t;
for (int i=0; i<N; i++)
begin
put_port.put(t);
endtask
endclass
class consumer extends uvm_component;
uvm_blocking_put_imp #(write_xtn,producer) put_imp;
function new(string name,uvm_component parent);
put_imp = new ("put_imp",this);
Endfunction
task put_imp();
write_xtn t;
for (int i=0; i<N; i++)
Begin
put_imp.put(t);
....
.....
endtask
B)Both the consumer and producer as initiators
class consumer extends uvm_component;
`uvm_component_utils(consumer)
uvm_blocking_get_port #(write_xtn)get_port;
function new (string name,uvm_component parent);
get_port = new ("get_port",this);
endfunction
virtual task run_phase(uvm_phase phase);
write_xtn t;
for ( int i=0 ; i<N ; i++)
begin
...
get_port.get(t);
end
endtask
endclass
class producer extends uvm_component;
`uvm_component_utils(producer)
uvm_blocking_put_port #(write_xtn)put_port;
virtual task run_phase(uvm_phase phase);
write_xtn t;
for (int i=o; i<N ; i++)
begin
put_port.put(t);
end
endtask
endclass
class top extends uvm_component;
`uvm_component_utils (top)
producer pro.h;
consumer con.h;
uvm_tlm_fifo #(write_xtn)fifo h;
function new (string new, uvm_component parent);
fifo h = new ("fifo h",this);
endfunction
function void connect_phase(uvm_phase phase);
proh.put_port.connect(fifoh.put_export);
conh.get_port.connect(fifoh.get_export);
endfunction
endclass
Paper - 3 - Part A
Question 1
Do_copy like we did in write xtn?
We have extra one wr_copy_xtnh to check if value is copied correctly or not because while
analysing output, you’ll first only see the randomized data as you’re performing copy after
printing randomized dara.
Question 2
Write direct constraints for both.
Then, in virtual seq and drivers and all, write the code for get next item, send_to_dut, item done,
etc and for seq side also
Write driver where req is created in sequence i assume
Same for read side too.
Sequence
Base sequence
Single Address Sequence
Virtual Sequence
Virtual Sequencer
Just call instances of both sequences so you can call them in virtual seqs class.
Question 3
auto_bin_max= bins anywhere from 1 to 4 but not more than 4 bins.
Coverpoint z one bin
So check accordingly
Question 4
● Property p1;
@(posedge clock)
Paper - 3 - Part B
Question 1
class DIV 1;
uvm_put_port #(DIV1) put_port;
task run_phase();
write_xtn wxtn;
repeat(10)begin
wxtn = new();
put_port.put(wxtn);
end
endtask
endclass
class DIV2 extends uvm_component;
`uvm_put_imp # (write_xtn,DIV2) put_imp;
`uvm_put_port # (DIV2) put_port;
function void put(write_xtn,wrxtnh);
forever begin
Extract data from wrxtn object
end
endfunction
endclass
class producer extends uvm_component;
DIV1 DIV1h;
DIV2 DIV2h;
function new (string name,uvm_component parent);
[Link](name,parent);
div1h = new("div1h",this);
div2h = new ("div2h",this);
endfunction
function void connect_phase (uvm_phase phase);
[Link](phase);
div1h.put_port.connect(div2h.put_imp);
endfunction
DIV2 & DIV3 are initiators
so place TLM_FIFO in between them
class Top();
uvm_tlm_fifo #(write_xtn)fifoh;
producer prdh;
consumer consh;
function new();
[Link](name);
prdh = new();
consh = new ();
endfunction
function void connect_phase(uvm_phase phase);
prdh.div2h.put_port.connect(fifoh.put_export)
consh.div3h.get_port.connect(fifoh.get_export)
endfunction
Question 2
● Transaction class: class def, factory reg, new, constraints, extern functions, do_print,
post randomize etc.
class min_transaction extends uvm_sequence_item
bit one_min;
bit[3:0] ls_min, ms_min, ls_hr,ms_hr;
bit[3:0] ls_min_out, ms_min_out, ls_hr_out, ms_hr_out;
constraint C1 { if (one_min)
begin
ls_min_out == ls_min;
ms_min_out == ms_min;
ls_hr_out = ls_hr;
ms_hr_out = ms_hr;
end
else
begin
Count++ //count variable declare.
end;}
Question 3
class transaction;
rand bit [31:0] addr,data;
constraint C1 {addr inside {[0:100],[1000:2000]};}
endclass
transaction t;
initial
begin
t = new();
assert([Link]()with(addr inside{[50:100],[1000:1500]};
data < 10;))
drive bus(t);
assert ([Link]()with(addr==2000;data >10;));
drivebus(t);
End
Paper - 4 - Part A
Question 1
Question 2
Question 3
Question 4
Question 5
Paper - 4 - Part B
** Question 1
Complete the program
//Define a packet with two random properties of type integers for addr and data
// addr range is 5 to 10
// data range is 20 to 50
class packet;
endclass
class generator;
//Define two packet handles pkt and pkt2drv
//declare Generator to driver Mailbox gen2drv
//Define constructor to use mailbox and packet objects
function new();
endfunction
// Define this task
task gen_packet;
// Generate 100 packets and send it driver mailbox
//Use the handles pkt and pkt2drv
endtask
endclass
Answer -
class packet;
rand bit [3:0] add_range;
rand bit [3:0] data_range;
constraint addr {add_range inside {[5:10]}; }
constraint datar {data_range inside {[20:50]}; } //question about bit size.
endclass
class generator;
packet pkt;
packet pkt2drv;
mailbox#(packet) gen2drv=new();
//Define constructor to use mailbox and packet objects
function new(); //Ask doubt
mailbox #(packet) gen2drv = new();
this.gen2drv=gen2drv;
endfunction
// Define this task
task gen_packet;
fork
begin
for(int i=0; i<=100; i++);
begin
assert([Link]());
pkt=new();
pkt2drv=new pkt;
//if we use handles to put and get, separate objects/memories must be created for both
classes (ie putting and getting). Or else, directly use the in-built methods.
[Link](pkt2drv); //Explain
end
end
join|_none
endtask
endclass
Question 2
class Transaction extends uvm_sequence_item;
`uvm_object_utils(transaction)
rand bit [7:0] header;
rand bit [7:0] payload[];
bit [7:0] parity;
constraint C1 { header[1:0] != 3;}
constraint C2 ( header[7:2] == [Link];}
constraint C3{header[7:2]!= 0;}
function void post_randomize();
parity = header;
foreach (payload[i])
parity = parity^payload[i];
endfunction
function new (string name = "transaction");
[Link](name);
endfunction
endclass
Question 3
class agent_config extends uvm_object;
uvm_active_passive_enum is_active;
endclass
class env_config extends uvm_object;
agent_config agt[];
int no_of_agents = 3;
endclass
class test extends uvm_test;
env_config ecfg;
agt_config agt[];
env envh;
int no_of_agents = 3;
function void build_phase(uvm_phase phase);
ecfg = env_config::type_id::create("ecfg");
agt = new [ no_of_agents];
[Link] = new[ no_of_agents];
foreach (agt[i])
begin
agt[i] = agent_config::type_id::create($sformatf("agt[%0d]",i));
if (i ==0)
agt[i].is_active = uvm_PASSIVE;
else
agt[i].is_passive = uvm_ACTIVE;
[Link][i]=agt[i];
ecfg.no_of_agents=no_of_agents;
end
uvm_config_db#(env_config)::set(this,"*","env_config",ecfg);
envh = env::typ_id::create("envh");
endfunction
endclass
class env extends uvm_env;
agent agth[];
env_config ecfg;
agent_config agt[];
function void build_phase(uvm_phase phase);
if(!uvm_config_db#(env_config)::get (this," ","env_config",ecfg))
`uvm_fatal("CONFIG","Failed")
agth = new[ecfg.no_of_agents];
agt = new[ecfg.no_of_agents];
foreach(agt[i])
begin
agth[i] = agent::type_id::create($sformatf("agt[%0d]",i));
uvm_config_db#(agent_config)::set(this,$sformatf("agth[%0d]",i,)"agent_config",agt[i]);
end
class agent extends uvm_agents;
driver drvh;
sequencer seqh;
monitor monh;
agent_config agt;
function void build_phase(uvm_phase phase);
if(!uvm_config_db#(agent_config)::get(this," ","agent_config",agt))
`uvm_fatal("CONFIG","Failed")
monh = monitor::typ_id::create();
if(agt.is_active == UVM_Active)
begin
drvh = create();
seqh = create();
end
endfunction
endclass
Paper - 5 - Part A
Question 1
Da = new(10);
Paper - 6 - Part A
Question 1
Question 2
Question 3
Question 4
Paper - 7 - Part A
Question 1
Question 2
Question 3
Question 4
