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SD Lab Syllabus

The System Design Laboratory course (EI2506) focuses on applying HDL codes for simulating and designing digital circuits, with a practical component consisting of at least 10 experiments. Students will learn to implement various circuits using VHDL/Verilog, including adders, multiplexers, and ALUs, and will gain skills in designing MSI circuits with FPGA. The course outcomes align with program outcomes, emphasizing high correlation in applied knowledge and skills.

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26 views2 pages

SD Lab Syllabus

The System Design Laboratory course (EI2506) focuses on applying HDL codes for simulating and designing digital circuits, with a practical component consisting of at least 10 experiments. Students will learn to implement various circuits using VHDL/Verilog, including adders, multiplexers, and ALUs, and will gain skills in designing MSI circuits with FPGA. The course outcomes align with program outcomes, emphasizing high correlation in applied knowledge and skills.

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gayatripattnaik13
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SUBJECT NAME SUBJECT CODE L-T-P CREDIT

SYSTEM DESIGN LABORATORY EI2506 0-0-3 1.5

Prerequisite: Basic programming skills


Course Outcomes:
At the end of the course, a student will be able to:
CO1 : Apply HDL codes in simulating gate level logic circuits and verify the waveforms.
CO2 : Design combinational circuits using MUX/ Decoder using structural and dataflow modeling.
CO3 : Design code convertors and verify the RTL/ Elaborated design.
CO4 : Implement synchronous sequential logic circuits using behavioral modeling.
CO5 : Design simple MSI circuits and implement using FPGA.
List of Experiments: (At least 10 experiments should be done)
EXP 1 : Simulate and verify basic, extended, and universal gate implementation using VHDL/Verilog.
EXP 2 : Simulate and verify basic adders and subtractors implementation using VHDL/Verilog.
Simulate and verify parallel Adders and Adder/ Subtractor circuits implementation using
EXP 3 :
VHDL/Verilog.
EXP 4 : Simulate and verify code converters implementation using VHDL/Verilog.
EXP 5 : Simulate and verify a 4-bit Magnitude Comparator implementation using VHDL/Verilog.
EXP 6 : Simulate and verify Multiplexer, Demultiplexer implementation using VHDL/Verilog.
EXP 7 : Simulate and verify Decoder and Encoder implementation using VHDL/Verilog.
EXP 8 : Simulate and verify an ALU implementation using VHDL/Verilog.
EXP 9 : Simulate and verify different Flip-Flop implementation using VHDL/Verilog.
EXP 10 : Simulate and verify different shift registers operations implementation using VHDL/Verilog.
EXP 11 : Simulate and verify different counter implementation using VHDL/Verilog.
Simulate and verify a Pseudo-Random Binary Sequence generator/ ALU/ Barrel Shifter/
EXP 12:
Multiplier implementation using VHDL/Verilog.

Text Book:
1. Joseph Cavanagh, Verilog HDL Design Examples, CRC Press, 2018.
2. Volnei A. Pedroni, Circuit Design with VHDL, Third Edition, MIT Press, 2020.
Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition
3.
Wiley, 2011
Reference Book:
1. J. Bhasker, Verilog HDL Synthesis, A Practical Primer, Addison Wesley Longman, 2018
2. Douglas L. Perry, VHDL: Programming by Example, Mc Graw Hill, 2002
3. Botros Nazeih M., Hdl Programming VHDL and Verilog, Dreamtech Press India Pvt. Ltd, 2014
ODISHA UNIVERSITY OF TECHNOLOGY AND RESEARCH
Techno Campus, Mahalaxmi Vihar, Ghatikia, Bhubaneswar-751029.
Syllabus (Admission Batch: 2023-24)

CO-PO-PSO MAPPING
SYSTEM DESIGN LABORATORY
Program Specific
Program Outcomes
Course Outcomes
outcome PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO
1 2 3 4 5 6 7 8 9 10 11 12 l 2 3
CO1 3 3 3 3 3 1 - 1 3 3 2 1 3 3 -
CO2 3 3 3 3 3 1 - 1 3 3 2 1 3 3 -
CO3 3 3 3 3 3 1 - 1 3 3 2 1 3 3 -
CO4 3 3 3 3 3 1 - 1 3 3 2 1 3 3 -
CO5 3 3 3 3 3 1 - 1 3 3 2 1 3 3 -
Average 3 3 3 3 3 1 - 1 3 3 2 1 3 3 -
Level of Correlation: 3 - High 2 - Medium 1 - Low

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