COA ASSIGNMENT II
1. Discuss the Organization of 1K X 1 memory organized on a chip and find the
number of external connections required to connect it to Processor
2. List the various mapping functions that map the main memory and Cache.
For a main memory having 4K blocks and Cache with 128 blocks, detail how
the Direct mapping function maps them.
3. Enumerate the process of transferring data directly between main memory
and secondary devices. Detail all the registers involved in the data transfer.
What is its advantage?
4. Discuss the Virtual memory organization. How is the virtual address
translated into Physical address by the MMU?
5. Sketch a Static RAM cell and a Dynamic RAM cell and discuss how Read and
write operations can be performed by the cell?
6. Outline the memory hierarchy of different types of memory used in a memory
system.
7. A main memory having 4K blocks and Cache with 128 blocks have to be
mapped using Set associative mapping function. Two adjacent blocks of the
Cache form a set. Detail the mapping function scheme that performs the
mapping task.
8. Show the Organization of 2M X 8 memory organized using memory chips of
size 512K X 8 that can be used for performing 32-bit Read/Write operations
9. List the various mapping functions that map the main memory and Cache.
For a main memory having 4K blocks and Cache with 128 blocks, detail how
the Associative mapping function maps them.
10. Enumerate the process of transferring data directly between main memory
and secondary devices. Detail all the registers involved in the data transfer.
What is its advantage?
11. Outline the memory hierarchy of different types of memory used in a memory
system.
12. Discuss the Virtual memory organization. How is the virtual address
translated into Physical address by the MMU
13. Sketch a Static RAM cell and a Dynamic RAM cell and discuss how Read and
write operations can be performed by the cell?
14. Show the Organization of 32m X 8 memory that uses Synchronous
DRAMS. When do the cells get refreshed?
15. Discuss the Set Associative Mapping function that maps a main memory
having 4K blocks and Cache with 128 blocks and 2 sets per block
16. Outline the organization of 2M X 8 memory that can be built using
512K X 8 memory chips.
17. Develop Set associative mapping function that maps 128 blocks of
Cache with 2 blocks per set and a main memory having 4k blocks.
18. Show the Memory hierarchy of computer memory system
19. Outline the organization of a 1K X 1 memory chip using static
memory cells. How many external connections does it provide?
20. Outline the translation of Virtual address to Physical address by
the MMU in Virtual memory system
21. What is page fault? How is it handled by Operating System?
Unit-4:
1. Explain with a neat sketch the working of a single bus structure
2. Illustrate between parallel and serial interface circuits
3. List down the interconnection networks and explain any two with
suitable examples
4. Illustrate between synchronous and asynchronous bus in detail
5. Explain how data transfer takes place between I/O device and processor
in a program controlled I/O.
6. Describe in detail about inter connection standards
7. Define hardware multithreading. Explain in detail about vector
processing.
8. Illustrate the concept of Arbitration with a suitable example
9. Define USB and explain about USB serial bus structure in detail
10. Explain how data transmission done in PCI bus
11. Explain with the help of neat diagram the working of PCI express
12. Define vector processing and explain about shared memory
multiprocessors
13. Explain in detail about Ring based inter connection networks
14. Explain in detail about Crossbar inter connection networks
15. Outline the Bus Arbitration scheme with the aid of a timing diagram
for a case where 3 masters’ assigned priorities by the arbiter
contend for the common bus.
16. Outline the read operation performed on a PCI bus for a 32-bit word
transfer from memory.
17. Demonstrate the serial interfacing of processor and I/O devices
with the aid of a block diagram
18. Outline the concept of hardware multi threading
19. Outline the PCI Interconnection standard and show the PCI express
connections.
