IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 71, NO.

3, MARCH 2024 1057

A Mixed-Signal Integrator-Differentiator-TIA
David-Peter Wiens , Graduate Student Member, IEEE, Markus Sporer , Graduate Student Member, IEEE,
Björn Driemeyer , Graduate Student Member, IEEE, and Maurits Ortmanns , Senior Member, IEEE

this feedback is inactive during the gain passband, i.e., introducing H(z) distinguishes it from a CM-DSM!
Abstract—Various implementations of transimpedance ampli-
fiers (TIAs) are used for current sensing applications and
they allow for low noise and wide bandwidth (BW). The pro-
cess of digitization is usually not implicitly discussed. Though,
BW limitation, sampling and quantization obviously add addi-
tional circuit complexity and have a strong influence on the CT-DSM
minimum achievable spot-noise in low noise TIAs. We intro-
duce a mixed-signal topology for the integrator-differentiator
TIA (I-D-TIA), which introduces the analog-to-digital converter
(ADC) before differentiation, thereby avoiding the implementa-
tion of the usually wideband and power-dominating analog differ-
entiator. The proposed topologies are compared by circuit-level
simulations. I-DAC, i.e., converts digital voltage input to a continuous current
Index Terms—Current sensing, low noise, I-D-TIA, ADC,
mixed-signal.
Fig. 1. (a) I-D-TIA [5] and (b) the proposed MS-TIA.

I. I NTRODUCTION
RECISE current sensing frontends are used in a large vari- GBW, whereas the differentiator realizes the high frequency
P ety of biomedical and electrochemical sensing application.
E.g., in electrical impedance spectroscopy such current sensing
√
gain (high GBW), but with relaxed noise requirements.
Almost exclusively, sensor frontends are followed by
frontends require low noise-floor in the range of ∼fA/ Hz, digitization at some point. Directly digitizing low noise
while concurrently reported BWs of those applications have analog frontends, such as current-mode delta-sigma modula-
increased into the ∼MHz range [1]. The most prominent struc- tors (CM-DSMs), have been variously reported [6], [7], [8].
ture is the resistive TIA (R-TIA) using a shunt feedback While the digitization is implicitly embedded, they require
resistor Rfb . In order to achieve a low noise-floor, a large Rfb – a large oversampling ratio (OSR) for high resolution,
often implemented as pseudo resistor (PR) – must be used which becomes very power hungry for large signal
[2], [3]. The TIA is inevitably loaded by a parasitic input BW [9].
capacitor Cp . Rfb and Cp create a parasitic pole, leading to Alternatively, we propose to move the ADC into the signal
instability, and moreover to a square-law dependency of the chain of an I-D-TIA, cf. Fig. 1(b). By adding the ADC sub-
required unity gain bandwidth product (GBW) of the opera- sequent to the integrator, the differentiator can be realized in
tional amplifier (OA) and the maximum operating frequency the digital domain, resulting in a mixed-signal topology. This
fmax [4]. The demands in the OA for low noise and high concept is further referred to as mixed-signal TIA (MS-TIA).
BW R-TIAs become – especially under the influence of big Optionally, the DC servo loop can also be implemented in
Cp – unpractical. Multistage R-TIA are alternatively used, to a mixed-signal fashion [10]. Even though this resembles a
increase the gain. However since the noise is set by the input CM-DSM, the DC servo loop only feeds back the (close
stage, their noise performance is inferior compared to single to) DC signals, not influencing the AC signal path, thus
stage R-TIA with similar gain [4]. the outermost integrator is not included into any quantiza-
As an alternative, the I-D-TIA was introduced in [5], cf. tion noise-shaping loop and the MS-TIA does not require
Fig. 1(a). By cascading an integrator and a differentiator, the oversampling.
inband transfer function (TF) is flat. A noiseless capacitor is This brief is organized as follows: Section II shortly reviews
used as feedback element in the input stage, which alleviates the operating principle of the I-D-TIA and Section III intro-
the gain-noise trade-off compared to R-TIAs. Thus, the task duces and analyzes the idea of the MS-TIA. Section IV shows
of achieving high BW and concurrently low noise is split into circuit level simulation results and derives suitable operating
two operations: the integrator defines the noise and needs low scenarios. Section V concludes the work.

Manuscript received 31 July 2023; accepted 20 September 2023. Date

of publication 25 September 2023; date of current version 5 March 2024.
II. I NTEGRATOR -D IFFERENTIATOR TIA
This work was supported by the German Federal Ministry of Education The transimpedance of the I-D-TIA in Fig. 1(a) is given by
and Research through the Project VE-FIDES under Grant 16ME0258. This
Cd
brief was recommended by Associate Editor Q. Liu. (Corresponding author: RI-D-TIA = · Rd . (1)
David-Peter Wiens.) Ci
The authors are with the Institute of Microelectronics, University of Ulm, To avoid integrator saturation from a DC input current, a DC
89069 Ulm, Germany (e-mail: [email protected]).
Color versions of one or more figures in this article are available at servo loop is used [5], [11], [12], cf. H(s) with Rdc in Fig. 1(a);
https://doi.org/10.1109/TCSII.2023.3318725. Rdc is set by the maximum expected DC input current; H(s)
Digital Object Identifier 10.1109/TCSII.2023.3318725 sets the minimum operating frequency fmin of the I-D-TIA.
1549-7747 
c 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1058 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 71, NO. 3, MARCH 2024

A. TF of I-D-TIAs at High Frequencies idea to move the power hungry analog differentiation into the
The required GBW of the OA used to implement both digital domain, as shown in Fig. 1(b).
the integrator and differentiator can be found in several Such a mixed-signal implementation also implicitely allows
publications [5], [12]. However, we have to derive them in a digitally reconfigurable DC servo loop: e.g., [10] proposed
detail here, as they are required in the later sections. At first an I-D-TIA with a mixed-signal DC servo loop to accom-
we assume that fmin  fmax , therefore the integrator TF is not plish a drastically reduced settling time in the integrator; [8]
affected by the DC servo loop near fmax . Additionally, it is achieved a sub-Hz cut-off frequency, without requiring large
assumed that the employed OAs have infinite DC gain and components, as they would be needed in analog RC filters.
a single-pole transfer characteristic. Therewith, the TF of the Note that unlike in CM-DSM the feedback digital-to-analog
I-D-TIA can be expressed as converter (DAC) operates at a much lower frequency, com-
pared to the signal BW, thus the integrator is not employed in
Cd −ωi −ωd2 s an oversampled loop and does not require excessive BW [9].
HI-D-TIA (s) = Rd ,
Ci s(s + ωi ) (s2 + αωd s + ωd2 ) Since the DAC is not operating in the AC signal path and as
         the MS-TIA’s DC servo loop can also be implemented in a
RI-D-TIA Int. poles Diff. poles and zero pure analog fashion, like in [5], [11], [12], further discussions
2π GBWOA,int 2π GBWOA,diff on the DAC properties are omitted.
with ωi = , ωd2 = ,
1+
Cp Rd (Cd + Cc ) For low noise TIAs the minimum spot-noise and the total
Ci
  integrated noise are important characteristics. In the follow-
1 ing, the influences of sampling and quantization on the noise
and α = ωd + Rd Cc , (2)
GBWOA,diff behavior of I-D-TIAs is discussed and compared to MS-TIAs.
where GBWOA,int and GBWOA,diff are the GBW of the inte- Thereby, it is assumed that Cd /Ci and Cp /Ci are large; than
grator and differentiator OA, respectively. Integrator pole the noise of the integrator OA dominates the overall integrated
pint,1 = 0 and differentiator zero zdiff = 0 cancel, which results noise, and Rdc sets the minimum spot-noise, see Section II-B.
in a low-pass transfer characteristic. To achieve, e.g., a
3rd -order butterworth transfer characteristic the coefficients are A. Noise Folding Due to Sampling: MS-TIA vs. I-D-TIA
set to ωd = ωi = ωmax = 2π fmax and α = 1 [13]. Since To estimate the influence of sampling on the noise properties
a high gain is targeted for the whole TIA, the assumptions of I-D-TIAs and MS-TIAs, the power spectral density (PSD)
Cc  Cd and fmax  GBWOA,diff can be made. Using Eq. (1),
of both TIAs is considered. Using Eq. (2) and (5) the noise
GBWOA,int and GBWOA,diff are given by
  PSD at the output of the integrator is
Cp  
GBWOA,int = 1 + fmax , (3) ωmax
2 Cp 2
Ci SV 2 ≈ ŜV 2 with Ŝ 2 = S 2 1 + . (7)
n,int OA,int ω 2 + ω 2 VOA,int VOA,int
Ci
max
1
GBWOA,diff = 2π RI-D-TIA Ci fmax
2
with Rd Cc = , (4) The OA noise is amplified by the capacitive feedback
2π fmax network, consisting of Ci and Cp . Further the limited
Eq. (3) shows the linear dependency of GBWOA,int from GBWOA,int leads to a first order roll-off. Using Eq. (2) and (7)
fmax and Cp /Ci . Eq. (4) shows the linear dependency of the noise PSD at the output of the differentiator in the I-D-TIA
GBWOA,diff from Ci and RI-D-TIA , and the disadvantageous is given by
quadratic dependency from fmax . ω6 ω2
SV 2 ≈ ŜV 2 (Rd Cd )2 ω6max+ω6 . (8)
n,diff OA,int max
B. Noise in I-D-TIAs Due to the zero in the nominator the noise has a second-
Noise in I-D-TIAs stems from integrator noise (including order roll-off above fmax .
DC servo loop) SI 2 , and differentiator noise SI 2 [5]: 1) Influences of Sampling on the Total Noise: The noise
n,int n,diff power at the output of the respective stage is derived by
 2
4kT Cp integrating the PSD over a given frequency range fl . . . fh :
SI 2 ≈ + ω2 Ci2 1 + SV 2 , (5)  fh
n,int Rdc Ci OA,int
f 
  PV 2 = ŜV 2 fmax arctan  , (9)
4kT Ci 2 n,int OA,int fmax fl
SI 2 ≈ + ω2 Ci2 SV 2 , (6)
n,diff Rd Cd n,diff  3 fh
4π 2 f 
where k is the Boltzmann constant, T the absolute temperature, PV 2 = ŜV 2 (Rd Cd ) fmax arctan
2 3  . (10)
n,diff OA,int 3 fmax 
SV 2 the integrator OA noise and SV 2 the input referred fl
OA,int n,diff
noise of the differentiator due to its OA noise. By choosing a With this the amount of out-of-band noise aliased back into
large Cd /Ci -ratio the noise due to Rd can be suppressed and the the signal-band can be calculated and the impact of sam-
minimum spot-noise is set by Rdc . When choosing a small Ci pling on the total noise can be estimated. One can expect less
the noise of the differentiator OA can be neglected. However noise aliasing for the I-D-TIA than in the MS-TIA due to the
Ci cannot be made arbitrarily small, since it leads to clipping stronger roll-off.
of low frequency input signals to the integrator. Due to the 2) Influence of Sampling on the Minimum Spot Noise: First
high-pass shaping of the integrator OA noise, it dominates the looking at the I-D-TIA, the sampling happens at the output of
total integrated noise in high BW I-D-TIAs [12]. the differentiator. The noise at the output of the differentia-
tor is – when input referred – divided by the flat TIA gain.
III. M IXED -S IGNAL TIA Therefore, the noise PSD of the I-D-TIA at multiples of the
State-of-the-art (SoA) I-D-TIA designs show that the sampling frequency fS must be significantly smaller than the
differentiator dominates the power consumption, requiring inband noise spectral density set by Rdc times the TIA gain.
more than half of the total power in [12]. This motivates the Assuming the aliased noise around ±1 · fS dominant, and by
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WIENS et al.: MIXED-SIGNAL I-D-TIA 1059

TABLE I
using Eq. (1), (5), and (8) the relation PARAMETERS U SED IN THE S IMULATION OF THE I-D-TIA AND
Cd 4kT (2πfS )2 MS-TIA. R EFERENCE D ESIGN I S [12]
Rd ·  2ŜV 2 (Rd Cd )
Ci Rdc   
OA,int 1 + (fS /fmax )6
±fS folding
4kT
(fS /fmax )6 1 π2 1
−−−−−−−→  SV 2 (Ci + Cp )2 fmax
2
(11)
fS =2OSRfmax Rdc OA,int 2 (2OSR)4
can be derived for the I-D-TIA. It needs a certain oversampling
in order to not detrimentally worsen the inband spot-noise
performance. In contrast to the I-D-TIA, the minimum inband
spot-noise is not influenced by sampling after the integrator
in the case of the MS-TIA. Even though the flat inband OA
noise of the integrator SV 2 aliases by sampling, it is high-
OA,int
pass shaped when input referred. Thus, the Rdc dominated
spot-noise is not affected.

B. ADC Resolution: MS-TIA vs. I-D-TIA

1) Influences of Finite ADC Resolution on the Total Noise:
In order to not dominate the integrated noise by the (quanti-
zation) noise of the ADC, its total noise must be significantly
smaller than the total noise at the output of the respective TIA,
calculated by using Eq. (9) and (10), with a frequency range
of 0 . . . fmax . In the MS-TIA, noise added by the ADC is –
input referred – high-pass shaped. Therefore, the integrated
noise power is dominated at frequencies close to fmax . Since
the I-D-TIA has a second gain stage, being the analog differ-
entiator, it is expected that the required ADC noise is relaxed
compared to the MS-TIA.
2) Influences of Finite ADC Resolution on the Minimum
Spot Noise: The input referred quantization noise added by
the ADC is high-pass shaped in the MS-TIA; therefore it
does not affect the minimum spot-noise. In contrast, for the
I-D-TIA the noise-floor of the ADC has to be significantly Fig. 2. Input referred noise PSD of I-D-TIA (top) and MS-TIA (bottom)
smaller than the minimum spot-noise set by Rdc . Assuming a sampled with different OSR and compared to unsampled CT √ spectrum. Total
integrated noise given in pA and minimum spot-noise in fA/ Hz.
flat inband noise of the ADC and using Eq. (1), and (5), the
relation TABLE II
Pn,ADC,I-D-TIA 4kT 2 I NTEGRATED AND S POT N OISE I NCREASE D UE TO S AMPLING W ITH
 R (12) D IFFERENT OSR FOR MS-TIA AND I-D-TIA. C ALCULATED VALUES
fmax Rdc TIA W HERE O BTAINED U SING E Q . (9), (10), AND (11)
can be derived by referring the noise-floor set by Rdc to the
output of the differentiator of the I-D-TIA, with Pn,ADC,I-D-TIA
being the noise power of the ADC. Thus, even if the
ADC noise influences the integrated noise only minor, it
can significantly worsen the minimum spot noise in the
I-D-TIAs.
noise voltage PSD at the C-TIA output

IV. S IMULATION R ESULTS

To validate the findings, circuit simulations were performed A. Influence of Ideal Sampling on MS- and I-D-TIA
using VerilogA models for amplifiers and ADCs including The input referred noise PSD of the I-D- and MS-TIA for
their respective noise sources, finite GBW and finite resolution. different OSR are plotted in Fig. 2. As this investigates solely
The modeled ADC has a conversion rate of one clock cycle the influence of aliased noise by sampling, the subsequent
and for quantization the additive white noise model is used. ADC resolution is assumed ideal. In Tab. II the calculated and
For comparison the SoA design from [12] served as a reference simulated increase in overall integrated inband and spot-noise
and similar component values were used. For the MS-TIA the due to sampling is given, showing a good agreement of theory
same integrator and DC servo loop as in the I-D-TIA were and simulation results.
used. Tab. I summarizes the specified values for the reference Proving the discussion from Section III-A, the minimum
I-D-TIA; its simulated input referred √ noise is 440 pArms with inband spot-noise in the I-D-TIA increases drastically if the
a minimum spot-noise of ∼4 fA/ Hz, acquired at 10 kHz. OSR is too small, whereas the MS-TIA is largely insensi-
Considering a supply voltage of 1.8 V and a TIA gain of tive to this, cf. Fig. 2. Concluding, large oversampling of
RI-D-TIA = 153 dB (45 M), this yields a maximum input cur- OSR = 8· · · 10 is necessary in I-D-TIAs, when low spot-noise
rent signal amplitude of about 21 nA, achieving an overall has to be achieved, while no oversampling is necessary in
signal-to-noise ratio (SNR) of ∼30 dB. MS-TIAs for the same result.
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1060 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 71, NO. 3, MARCH 2024

TABLE III
T OTAL N OISE P OWER I NCREASE IN MS-TIA AND S POT N OISE P OWER
I NCREASE IN I-D-TIA D UE TO L IMITED ADC R ESOLUTION .
C ALCULATED VALUES A RE O BTAINED U SING E Q . (9) AND (12)

Looking at Fig. 2, the total integrated noise is dominated by

the band-edge noise and not by the minimum spot-noise. By
sampling at Nyquist-rate, the total integrated noise increases
by a factor of 2 for both TIAs. By going to higher OSR,
the additional aliased noise in the I-D-TIA decreases faster
compared to the MS-TIA, due to the stronger roll-off in the
noise TF, as predicted in Section III-A. Thus oversampling of Fig. 3. Input referred noise PSD of I-D-TIA (top) and MS-TIA (bottom)
2· · · 4 is necessary for the I-D- and MS-TIA, respectively, if for different SNRADC and √reference. Total integrated noise given in pA and
the total integrated inband noise shall remain rather unaffected. minimum spot-noise in fA/ Hz.

As the I-D-TIA has a flat inband response, the differentiator

B. Influence of Quantization Noise on MS- and I-D-TIA
output can swing at full-scale at every inband frequency. Thus,
For the following simulations, the limited SNR of the ADC the harmonic distortion (HD) caused by the ADC is indepen-
is calculated based on the assumed supply voltage in Tab. I dent of input frequency and adds directly to the distortion of
(limiting the full-scale range) and the inband quantization the overall digitized I-D-TIA.
noise power. In order to eliminate the influence of sam- In contrast, the scenario is frequency dependent for the MS-
pling and aliasing in these simulations, according to Fig. 2 TIA; here, the worst case input signal is at low frequencies,
an OSR = 16 is chosen. where the integrator output swings at full-scale. Then, HD
By using Eq. (9), (10) and the parameters from Tab. I, the from ADC becomes worst, and moreover the usually dominant
noise power at the output of the integrator in the MS-TIA and HD3 is 10 dB amplified by the digital differentiator. Since the
of the differentiator in the I-D-TIA are calculated. This results SNR of ADCMS-TIA is 18 dB better compared to ADCI-D-TIA ,
in an rms-noise of Vrms,int = 64 µV and Vrms,diff = 17 mV, even then the output distortion is expected effectively lower
respectively. ADCs adding the same amount of integrated as in the digitized I-D-TIA. At higher input frequencies, the
quantization inband noise require SNRMS-TIA >80 dB and output swing of the integrator decreases due to its TF, and
SNRI-D-TIA >31 dB, respectively. The much larger required thus HD strongly decreases, too. Consequently, no visible HD
SNRMS-TIA for the same integrated inband noise is due to is observable at high input frequencies.
the lack of the second stage amplifier (differentiator in the
I-D-TIA). On the contrary, the SNR of the ADC, which is
required to not deteriorate the minimum inband spot-noise of D. Discussion on Power and Area: MS-TIA vs. I-D-TIA
the I-D-TIA, is much higher. Using Eq. (12), it needs better The above calculation and simulation results, cf. Tab. II
than SNRI-D-TIA >62 dB. and Tab. III, show that, for similar noise performance, the
Consequently, when the ADCs should not deteriorate both MS-TIA requires an ADC with half the sampling rate but
the inband spot-noise as well as the total integrated noise, ∼3 Bit more resolution compared to the I-D-TIA. Then, the
the ADC for the MS-TIA requires effectively 18 dB more MS-TIA omits the analog, but requires a digital differentiator.
resolution than that of the I-D-TIA. Fig. 3 shows the respec- These differences are compared in area and power.
tive simulations, where the input referred noise PSD of The reference work in [12] (180 nm technology) reveals
the I-D-TIA and MS-TIA are shown for different SNRADC . the area of the integrator and analog DC servo loop to be
Tab. III lists the increase in both spot- and total noise for dif- ∼0.33 mm2 , with a total power consumption of 12.2 mW.
ferent SNRADC , where simulation well matches calculation: These blocks are assumed to be the same in MS- and I-D-TIA.
SNRI-D-TIA =62 dB and SNRMS-TIA =80 dB achieve the above 1) Estimations for the I-D-TIA: Following [12], the ana-
calculated noise penalties of about x2 in spot-noise of the log differentiator occupies an area of ∼0.1 mm2 and power
I-D-TIA and total integrated noise of the MS-TIA. of 14.4 mW. The ADC for the I-D-TIA would need a
In order to reduce the integrated and spot noise penalties by SNR ≥ 68 dB, see Tab. III, at a sampling rate of ≥ 123 MS/s
the ADCs below the contribution of the analog frontends, both (OSR = 8), see Tab. II. A SoA ADC at a similar technol-
ADCs are given 1 Bit more resolution for the following con- ogy node (130 nm) and with fitting specifications was found
siderations, i.e., SNRMS-TIA =86 dB and SNRI-D-TIA =68 dB. in [14]: it consumes an area of 0.22 mm2 and 1.32 mW of
power, and it achieves SNDR = 69.1 dB at 50 MS/s. An ADC
buffer is further included, where [15] reports an ADC buffer
C. Influence of ADC Non-Linearity on MS- and I-D-TIA at similar speed and resolution range consuming ∼1.4 mW.
The effect of ADC non-linearity in both TIA-ADCs is In sum, this results an ADC Schreier SNDR figure of merit
shortly discussed next. We assume non-linearity to be equal (FoMSch ) of 169 dB. Applying this FoMSch to the ADC of
to the above required ADC resolution (SNDR = SNR−3 dB). the I-D-TIA extrapolates an ADC power consumption of
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WIENS et al.: MIXED-SIGNAL I-D-TIA 1061

≈0.6 mW. Concluding, we can estimate that the I-D-TIA performance specification of a SoA TIA, highlighting that the
from [12] including its ADC would require an area of drawback of higher ADC resolution is outnumbered by the
0.65 mm2 , 34% occupied by the ADC, and a power of potential power savings. Further revealing that by moving to
27.2 mW, 2% required by the ADC. a smaller technology node the MS-TIA would benefit more,
2) Estimations for the MS-TIA: The required ADC for compared to the I-D-TIA.
the MS-TIA needs SNR ≥ 86 dB, cf. Tab. III at a sampling
rate ≥ 62 MS/s (OSR = 4), cf. Tab. II. Allowing the same R EFERENCES
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