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DV Syllabus

The Design Verification Course spans three months, covering Digital Electronics and Verilog HDL in the first month, SystemVerilog in the second, and Universal Verification Methodology (UVM) in the third. Each month consists of multiple modules that delve into topics such as digital design basics, Verilog and SystemVerilog fundamentals, and advanced UVM concepts. The course aims to equip participants with the necessary skills for effective design verification and testbench development.

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25 views2 pages

DV Syllabus

The Design Verification Course spans three months, covering Digital Electronics and Verilog HDL in the first month, SystemVerilog in the second, and Universal Verification Methodology (UVM) in the third. Each month consists of multiple modules that delve into topics such as digital design basics, Verilog and SystemVerilog fundamentals, and advanced UVM concepts. The course aims to equip participants with the necessary skills for effective design verification and testbench development.

Uploaded by

sudharsanleo.r2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Design Verification Course

Month 1: Digital Electronics + Verilog HDL

Module 1: Digital Basics


 Number Systems, Binary Arithmetic
 Boolean Algebra, Logic Gates
 K-Maps, SOP/POS Forms
 Adders, Subtractors, Multiplexers, Demultiplexers

Module 2: Sequential Digital Design


 Encoders, Decoders, Comparators, Parity Generators
 Flip-Flops (SR, D, JK, T), Latches, Timing Diagrams
 Counters, Shift Registers

Module 3: Introduction to Verilog


 Verilog Intro, Modules, Data Types, Operators
 Initial vs Always Blocks, Combinational & Sequential Circuits
 Blocking vs Non-blocking Assignments, Parameterized Modules

Module 4: Verilog Testbenches


 Testbench Basics, Stimulus Generation
 Tasks and Functions, Timescales and Delays

Month 2: SystemVerilog (SV)

Module 1: SV Language Fundamentals


 SV Data Types (2-state, 4-state), Packed/Unpacked Arrays
 Structures, Unions, Enumerations, Typedef
 Control Flow Enhancements, Loops

Module 2: Advanced Constructs


 Interfaces and Modports
 Randomization (simple and constrained)
 Queues, Dynamic & Associative Arrays
 Functional Coverage (covergroups, bins), Assertions

Module 3: Object-Oriented SV
 Classes, Objects, Constructors, Inheritance, Polymorphism
 Virtual Methods, Mailboxes, Semaphores, Factory Pattern
Module 4: Testbench Environment
 Transaction-level Modeling (TLM), Stimulus Generation
 Connecting Testbench with DUT, Assertion-Based Verification

Month 3: Universal Verification Methodology (UVM)

Module 1: UVM Basics


 UVM Overview, Class Hierarchy, Phases
 Macros, Factory, Component Structure: Agent, Env, Test

Module 2: UVM Testbench Architecture


 Sequence, Sequencer, Driver, Monitor, Scoreboard
 Agent Creation (active/passive), Virtual Interfaces, Config DB
 Transaction and TLM Communication

Module 3: Advanced UVM Concepts


 Factory Overrides, Reporting, Callbacks
 Analysis Ports and Exports, Objection Mechanism
 UVM Messaging and Debugging

Module 4: Additional Concepts


 Code Coverage vs Functional Coverage
 Assertions in UVM, Register Layer Introduction
 Best Practices in Verification

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