1) What is the difference between Latch And Flip-flop?

The difference between latches and Flip-flop is that the latches are level
triggered and flip-flops are edge triggered. In latches level triggered
means that the output of the latches changes as we change the input and
edge triggered means that control signal only changes its state when goes
from low to high or high to low.

Latches are fast whereas flip-flop is slow.

2) What is the binary number system?

The system which has a base 2 is known as the binary system and it
consists of only two digits 0 and 1.

22.5M
475
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For Example: Take decimal number 625

625 = 600 + 20 + 5
That means,
6×100 + 2×10 + 5
6 ×102 + 2×101 + 5×100

In this 625 consist of three bits, we start writing the numbers from the
rightmost bit power as 0 then the second bit as power 1 and the last as
power 2. So, we can represent a decimal number as

∑digit × 10corresponding position or bit

Here 10 is the total number of digits from 0 to 9.

3) State the De Morgan's Theorem?

De Morgan's Theorem stated two theorems:

[Link] complement of a product of two numbers is the sum of the

complements of those numbers.

(A. B)' = A' + B'

Truth Table:
2. The complement of the sum of two numbers is equal to the product of
the complement of two numbers.

(A + B)' = A'B'

Truth Table:

4) Define Digital System?

Digital systems are the system that processes a discrete or digital signal.

5) What is meant by a bit?

Bits are the binary digits like 0 and 1.

6) What is the best Example of Digital system?

Digital Computer.
7) How many types of number system are there?

There are four types of number system:

1. Decimal Number System.

2. Binary Number System.
3. Octal Number System.
4. Hexadecimal Number System.

8) What is a Logic gate?

The basic gates that make up the digital system are called a logic gate.
The circuit that can operate on many binary inputs to perform a particular
logic function is called an electronic circuit.

9) What are the basic Logic gates?

There are three basic logic gates-

1. AND gate.
2. OR gate.
3. NOT gate.

10) Which gates are called as Universal gate and what are its advantages?

The Universal gates are NAND and NOR. The advantages of these gates
are that they can be used for any logic calculation.

11) What are the applications of the octal number system?

The applications of the octal number system are as follows:

1. For the efficient use of microprocessors.

2. For the efficient use of digital circuits.
3. It is used to enter binary data and display of information.
12) What are the fundamental properties of Boolean algebra?

The basic properties of Boolean algebra are:

1. Commutative Property.
2. Associative Property.
3. Distributive Property.

13) What are Boolean algebra and Boolean expression?

14) What is meant by K-Map or Karnaugh Map?

K-Map is a pictorial representation of truth table in which the map is made

up of cells, and each term in this represents the min term or max term of
the function. By this method, we can directly minimize the Boolean
function without following various steps.

15) Name the two forms of Boolean expression?

The two forms of Boolean expression are:

1. Sum of products (SOP) form.

2. The Product of sum (POS) form.

16) What are Minterm and Maxterm?

A minterm is called Product of sum because they are the logical AND of
the set of variables and Maxterm are called sum of product because they
are the logical OR of the set of variables.

17) Write down the Characteristics of Digital ICs?

The characteristics of digital ICs are -

 1. Propagation delay.
2. Power Dissipation.
3. Fan-in.
4. Fan-out.
5. Noise Margin.

18) What are the limitations of the Karnaugh Map?

The limitations of Karnaugh Map are as follows:

1. It is limited to six variable maps which means more than six variable
involving expressions are not reduced.
2. These are useful for only simplifying Boolean expression which is
represented I standard form.

19) What are the advantages and disadvantages of the K-Map Method?

The advantages of the K-Map method are as follows-

1. It is an excellent method for simplifying expression up to four

variables.
2. For the logical simplification, it gives us a visual method.
3. It is suitable for both SOP and POS forms of reduction.
4. It is more suitable for classroom teachings on logic simplification.

The disadvantages of the K-Map method are as follows:

1. It is not suitable when the number of variables exceeds more than

four.
2. For Computer reduction, it is not suitable.
3. We have to take while entering the numbers in the cell-like 0, 1 and
don't care terms.

20) What are the advantages and disadvantages of Quine-MC Cluskey method?
21) Define Pair, Quad, and Octet?

Pair: Two adjacent cell of karnaugh map is called as Pair. It cancels one
variable in a K-Map simplification.

Quad: A Pair of Four adjacent pairs in a karnaugh map is called a quad. It

cancels two variables in a K-Map simplification.

Octet: A Pair of eight adjacent pair in a karnaugh map is called an octet.

It cancels four variables in a K-map simplification.

22) Define Fan-in and Fan-out?

Fan-in- The Fan-in of the gate means that the number of inputs that are
connected to the gate without the degradation of the voltage level of the
system.

Fan-out- The Fan-out is the maximum number of same inputs of the

same IC family that a gate can drive maintaining its output levels within
the specified limits.

23) Write the definition of the Duality Theorem?

Duality Theorem states that we can derive another Boolean expression

with the existing Boolean expression by:

1. Changing OR operation (+ Sign) to AND operation (. Dot Sign) and

vice versa.
2. Complimenting 0 and 1 in the expression by changing 0 to 1 and 1
to 0 respectively.

24) What is Half-Adder?

Half-adder is the circuits that perform the addition of two bits. It has two
inputs A and B and two outputs S (sum) and C (carry). It is represented by
XOR logic gate and an AND logic gate.
Truth Table of Half adder:

25) What is Full-Adder?

Full-adder is the circuits that perform the addition of three bits. It has
three inputs A, B and a carry bit. Full adders are represented with AND,
OR and XOR logic gate.

Truth Table of Full-Adder

26) What is power dissipation?

Period time is the electrical energy used by the logic circuits. It is

expressed in milliwatts or nanowatts.

Power dissipation = Supply voltage * mean current taken from

the supply.

27) What is a Multiplexer?

The multiplexer is a digital switch which combines all the digital

information from several sources and gives one output.

28) What are the applications of Multiplexer (MUX)?

The applications of the multiplexer are as follows:

1. It is used as a data selector from many inputs to get one output.

2. It is used as A/D to D/A Converter.
3. These are used in the data acquisition system.
4. These are used in time multiplexing system.

29) What is a Demultiplexer?

The demultiplexer is a circuit that receives the input on a single line and
transmits this onto 2n possible output line. A Demultiplexer of 2n outputs
has n select lines, which are used to select which output line is to be sent
to the input. The demultiplexer is also called as Data Distributor.

30) What are the applications of Demultiplexer?

The applications of the demultiplexer are as follows:

1. It is used in the data transmission system with error detection.

2. It is used as a decoder for the conversion of binary to decimal.
3. It is used as a serial to parallel converter.

31) What are the differences between Combinational Circuits and Sequential
Circuits?

The differences between combinational and sequential circuits are as

follows:
S.N Combinational Circuits Sequential Circuits
o

1. These are faster in speed. These are slower.

2. These are easy to design. These are difficult to design.

3. The clock input is not required. The clock input is required.

4. In this, the memory units are not In this, the memory units are required to
required. store the previous values of inputs.

5. Example: Mux, Demux, encoder, Example: Shift registers, counters.

decoder, adders, subtractors.

32) Define Rise Time?

Rise time is the time that is required to change the voltage level from 10%
to 90%.

33) Define fall time?

Fall time is the time that is required to change the voltage level from 90%
to 10%.

34) Define Setup time?

The minimum time that is required to maintain the constant voltage levels
at the excitation inputs of the flip-flop device before the triggering edge of
the clock pulse for the levels to be reliably clocked in the flip flop is called
the Setup time. It is denoted as tsetup.

35) Define Hold time?

The minimum time at which the voltage level becomes constant after
triggering the clock pulse in order to reliably clock into the flip flop is
called the Hold time. It is denoted by thold.
36) What is the difference between Synchronous and Asynchronous Counters?

S.N Asynchronous Counters Synchronous Counters

o

1. These are low-speed These are high-speed Counters.

Counters.

2. The Flip flops of these In these counters, the flip-flops are c

counters are not clocked simultaneously.
simultaneously.

3. Simple logic circuits are Complex logic circuits are there when the num
there for more number of states increases.
states.

The difference between Synchronous and Asynchronous Counters are as

follows:

37) What are the applications of Flip-Flops?

The applications of flip-flops are:

1. Flip-flops are used as the delay element.

2. These are used for Data transfer.
3. Flip-flops are used in Frequency Division and Counting.
4. Flip-Flops are used as the memory element.
38) What is the difference between D-latch and D Flip-flop?

D-latch is level sensitive whereas flip-flop is edge sensitive. Flip-flops are

made up of latches.

39) What are the applications of Buffer?

Applications of buffer are as follows:

1. Buffer helps to introduce small delays.

2. Buffer helps for high Fan-out.
3. Buffer are used to eliminate cross talks.

1. Question 1. What Is Difference Between Latch And Flip-

flop?
Answer :
The main difference between latch and FF is that latches are level
sensitive while FF is edge sensitive. They both require the use of
clock signal and are used in sequential logic. For a latch, the
output tracks the input when the clock signal is high, so as long
as the clock is logic 1, the output can change if the input also
changes.

FF on the other hand, will store the input only when there is a
rising/falling edge of the clock. Latch is sensitive to glitches on
enable pin, whereas flip-flop is immune to glitches. Latches take
fewer gates (also less power) to implement than flip-flops.
Latches are faster than flip-flops

2. Question 2. Given Only Two Xor Gates One Must Function

As Buffer And Another As Inverter?
Answer :
Tie one of xor gates input to 1 it will act as inverter.
Tie one of xor gates input to 0 it will act as buffer.
Electronics and Communications Engineering Interview Questions
3. Question 3. Difference Between Mealy And Moore State
Machine?
Answer :
A) Mealy and Moore models are the basic models of state
machines. A state machine which uses only Entry Actions, so that
its output depends on the state, is called a Moore model. A state
machine which uses only Input Actions, so that the output
depends on the state and also on inputs, is called a Mealy model.
The models selected will influence a design but there are no
general indications as to which model is better. Choice of a model
depends on the application, execution means (for instance,
hardware systems are usually best realized as Moore models) and
personal preferences of a designer or programmer
B) Mealy machine has outputs that depend on the state and input
(thus, the FSM has the output written on edges) Moore machine
has outputs that depend on state only (thus, the FSM has the
output written in the state itself.
Advantage and Disadvantage
•In Mealy as the output variable is a function both input and
state, changes of state of the state variables will be delayed with
respect to changes of signal level in the input variables, there are
possibilities of glitches appearing in the output variables.

•Moore overcomes glitches as output dependent on only states

and not the input signal level.
•All of the concepts can be applied to Moore-model state
machines because any Moore state machine can be implemented
as a Mealy state machine, although the converse is not true.
•Moore machine: the outputs are properties of states
themselves... which means that you get the output after the
machine reaches a particular state, or to get some output your
machine has to be taken to a state which provides you the
output. The outputs are held until you go to some other state
Mealy machine:
 •Mealy machines give you outputs instantly, that is immediately
upon receiving input, but the output is not held after that clock
cycle.

4. Question 4. Difference Between One Hot And Binary

Encoding?
Answer :
One hot encoding is encoding of a finite state machine where each state will take a
separate flip flop. If u hav 8 states in Finite state machine then encoder requires 8 flip
flops. Same state machine requires only three ff'f in Gray and Binary encoding. One hot
encoding will increase the speed but area utilisation will be more.

Binary encoding is a binary count of the state machine number in sequence

and implement very less logic.
Binary encoding is the simplest state machine encoding and all possible states are
defined and there is no possibility of a hang state. Power Electronics Tutorial
5. Question 5. How To Achieve 180 Degree Exact Phase
Shift?
Answer :
Never tell using inverter
a) DCM an inbuilt resource in most of FPGA can be configured to
get 180 degree phase shift.
b) BUFGDS that is differential signaling buffers which are also
inbuilt resource of most of FPGA can be used.
Electrical and Electronics Engineering Interview Questions
6. Question 6. What Is Significance Of Ras And Cas In Sdram?
Answer :
SDRAM receives its address command in two address words. It
uses a multiplex scheme to save input pins. The first address
word is latched into the DRAM chip with the row address strobe
(RAS).

Following the RAS command is the column address strobe (CAS)

for latching the second address word. Shortly after the RAS and
CAS strobes, the stored data is valid for reading.

7. Question 7. Tell Some Of Applications Of Buffer?

Answer :
 a) They are used to introduce small delays.
b) They are used to eliminate cross talk caused due to inter
electrode capacitance due to close routing.
c) They are used to support high fan-out, e.g.: bufg
Analog Communication Tutorial Power Electronics Interview
Questions
8. Question 8. Give Two Ways Of Converting A Two Input
Nand Gate To An Inverter?
Answer :
a) Short the 2 inputs of the nand gate and apply the single input
to it.
b) Connect the output to one of the input and the other to the
input signal.
9. Question 9. Why Is Most Interrupts Active Low?
Answer :
This answers why most signals are active low if you consider the
transistor level of a module, active low means the capacitor in the
output terminal gets charged or discharged based on low to high
and high to low transition respectively. When it goes from high to
low it depends on the pull down resistor that pulls it down and it
is relatively easy for the output capacitance to discharge rather
than charging. Hence people prefer using active low signals.
Electronics Interview Questions
10. Question 10. Design A Four-input Nand Gate Using
Only Two-input Nand Gates.
Answer :
Basically, you can tie the inputs of a NAND gate together to get
an inverter.
VLSI Design Tutorial
11. Question 11. What Will Happen If Contents Of Register
Are Shifter Left, Right?
Answer :
 It is well known that in left shift all bits will be shifted left and LSB
will be appended with 0 and in right shift all bits will be shifted
right and MSB will be appended with 0 this is a straightforward
answer What is expected is in a left shift value gets Multiplied by
2
e.g.: consider 0000_1110=14 a left shift will make it
0001_110=28, it the same fashion right shift will Divide the value
by 2.
Verilog Interview Questions
12. Question 12. Given The Following Fifo And Rules, How
Deep Does The Fifo Need To Be To Prevent Underflow Or
Overflow?
Answer :
RULES:

1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty cycle(en_B) = 25%
Assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 400 = 4000ns, but we only
output for 1000ns,due to (3), so 3000ns of the enable we are
doing no output work. Therefore, FIFO size = 3000ns/40ns = 75
entries
Electronics and Communications Engineering Interview Questions
13. Question 13. Differences Between D-latch And D Flip-
flop?
Answer :
D-latch is level sensitive where as flip-flop is edge sensitive. Flip-
flops are made up of latches.

14. Question 14. What Is A Multiplexer?

Answer :
Is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line.
 (2n =>n). Where n is selection line.

15. Question 15. What Are Set Up Time & Hold Time
Constraints? What Do They Signify? Which One Is Critical
For Estimating Maximum Clock Frequency Of A Circuit?
Answer :
Set up time is the amount of time the data should be stable
before the application of the clock signal, where as the hold time
is the amount of time the data should be stable after the
application of the clock. Setup time signifies maximum delay
constraints; hold time is for minimum delay constraints. Setup
time is critical for establishing the maximum clock frequency.
ELECTRONICS & INSTRUMENTATION Engineering Interview
Questions
16. Question 16. How Can You Convert An Sr Flip-flop To A
Jk Flip-flop?
Answer :
By giving the feedback we can convert, i.e. !Q=>S and
Q=>[Link] the S and R inputs will act as J and K respectively.

17. Question 17. How Can You Convert The Jk Flip-flop To

A D Flip-flop?
Answer :
By connecting the J input to the K through the inverter.
VHDL Interview Questions
18. Question 18. How Do You Detect If Two 8-bit Signals
Are Same?
Answer :
XOR each bits of A with B (for e.g. A [0] xor B [0]) and so on. The
o/p of 8 xor gates is then given as i/p to an 8-i/p nor gate.

if o/p is 1 then A=B.

Electrical and Electronics Engineering Interview Questions
19. Question 19. Convert D-ff Into Divide By 2. (not Latch)
What Is The Max Clock Frequency The Circuit Can Handle,
Given The Following Information?
 Answer :
T_setup= 6nsT_hold = 2nS T_propagation = 10nS

Circuit: Connect Qbar to D and apply the clk at clk of DFF and
take the O/P at Q. It gives freq/2. Max. Freq of operation: 1/
(propagation delay+setup time) = 1/16ns = 62.5 MHz

20. Question 20. 7 Bit Ring Counter's Initial State Is

0100010. After How Many Clock Cycles Will It Return To
The Initial State?
Answer :
6 cycles
VLSI Interview Questions
21. Question 21. Design All The Gates (not, And, Or, Nand,
Nor, Xor, Xnor) Using 2:1 Multiplexer?
Answer :
Using 2:1 Mux, (2 inputs, 1 output and a select line)
a) NOT :Give the input at the select line and connect I0 to 1 & I1
to 0. So if A is 1, we will get I1 that is 0 at the O/P.
b) AND: Give input A at the select line and 0 to I0 and B to I1. O/p
is A & B
c) OR: Give input A at the select line and 1 to I1 and B to I0. O/p
will be A | B
d) NAND: AND + NOT implementations together
e) NOR: OR + NOT implementations together
f) XOR: A at the select line B at I0 and ~B at I1. ~B can be
obtained from (a)
g) XNOR: A at the select line B at I1 and ~B at I0
22. Question 22. Design A Circuit That Calculates The
Square Of A Number?
Answer :
It should not use any multiplier circuits. It should use Multiplexers
and other logic?
 1^2=0+1=1
2^2=1+3=4
3^2=4+5=9
4^2=9+7=16
5^2=16+9=25
See a pattern yet? To get the next square, all you have to do is
add the next odd number to the previous square that you found.
See how 1,3,5,7 and finally 9 are added. Wouldn’t this be a
possible solution to your question since it only will use a counter,
multiplexer and a couple of adders? It seems it would take n clock
cycles to calculate square of n.

23. Question 23. N Number Of Xnor Gates Is Connected In

Series Such That The N Inputs (a0, A1, A2......) Are Given
In The Following Way: A0 & A1 To First Xnor Gate And A2
& O/p Of First Xnor To Second Xnor Gate And So On.....
Nth Xnor Gates Output Is Final Output. How Does This
Circuit Work? Explain In Detail?
Answer :
If N=Odd, the circuit acts as even parity detector, i.e. the output
will 1 if there are even number of 1's in the N input...This could
also be called as odd parity generator since with this additional 1
as output the total number of 1's will be ODD. If N=Even, just the
opposite, it will be Odd parity detector or Even Parity Generator.
Analogue electronics Interview Questions
24. Question 24. What Is Race-around Problem? How Can
You Rectify It?
Answer :
The clock pulse that remains in the 1 state while both J and K are
equal to 1 will cause the output to complement again and repeat
complementing until the pulse goes back to 0, this is called the
race around problem. To avoid this undesirable operation, the
clock pulse must have a time duration that is shorter than the
 propagation delay time of the F-F, this is restrictive so the
alternative is master-slave or edge-triggered construction.
Power Electronics Interview Questions
25. Question 25. An Assembly Line Has 3 Fail Safe
Sensors And One Emergency Shutdown Switch. The Line
Should Keep Moving Unless Any Of The Following
Conditions Arise:
Answer :
(i) If the emergency switch is pressed
(ii) If the senor1 and sensor2 are activated at the same time.
(iii) If sensor 2 and sensor3 are activated at the same time.
(iv) If all the sensors are activated at the same time
suppose a combinational circuit for above case is to be
implemented only with NAND Gates. How many minimum number
of 2 input NAND gates are required?

No of 2-input NAND Gates required = 6 you can try the whole

implementation.

26. Question 26. How Will You Implement A Full

Subtractor From A Full Adder?
Answer :
All the bits of subtrahend should be connected to the xor gate.
Other input to the xor being one. The input carry bit to the full
adder should be made 1. Then the full adder works like a full
subtract.
Analog Communication Interview Questions
27. Question 27. What Is Difference Between Setup And
Hold Time. The Interviewer Was Looking For One Specific
Reason, And Its Really A Good Answer Too..the Hint Is
Hold Time Doesn't Depend On Clock, Why Is It So...?
Answer :
Setup violations are related to two edges of clock, i mean you can
vary the clock frequency to correct setup violation. But for hold
 time, you are only concerned with one edge and do not basically
depend on clock frequency.
Electronics Interview Questions
28. Question 28. In A 3-bit Johnson's Counter What Are
The Unused States?
Answer :
2(power n)-2n is the one used to find the unused states in
Johnson counter.

So for a 3-bit counter it is 8-6=[Link] states=2. the two

unused states are 010 and 101.

29. Question 29. What Is Difference Between Ram And

Fifo?
Answer :
FIFO does not have address lines

Ram is used for storage purpose where as FIFO is used for

synchronization purpose i.e. when two peripherals are working in
different clock domains then we will go for FIFO.
VLSI Design Interview Questions
30. Question 30. Consider Two Similar Processors, One
With A Clock Skew Of 100ps And Other With A Clock Skew
Of 50ps. Which One Is Likely To Have More Power? Why?
Answer :
Clock skew of 50ps is more likely to have clock power. This is
because it is likely that low-skew processor has better designed
clock tree with more powerful and number of buffers and
overheads to make skew better.

31. Question 31. Is It Possible To Reduce Clock Skew To

Zero? Explain Your Answer?
Answer :
Even though there are clock layout strategies (H-tree) that can in
theory reduce clock skew to zero by having the same path length
from each flip-flop from the pll, process variations in R and C
 across the chip will cause clock skew as well as a pure H-Tree
scheme is not practical (consumes too much area).

32. Question 32. The Circle Can Rotate Clockwise And

Back. Use Minimum Hardware To Build A Circuit To
Indicate The Direction Of Rotating?
Answer :
2 sensors are required to find out the direction of rotating. They
are placed like at the drawing. One of the m is connected to the
data input of D flip-flop, and a second one - to the clock input. If
the circle rotates the way clock sensor sees the light first while D
input (second sensor) is zero - the output of the flip-flop equals
zero, and if D input sensor "fires" first - the output of the flip-flop
becomes high.

33. Question 33. You Have Two Counters Counting Upto

16, Built From Negedge Dff , First Circuit Is Synchronous
And Second Is "ripple" (cascading), Which Circuit Has A
Less Propagation Delay? Why?
Answer :
The synchronous counter will have lesser delay as the input to
each flop is readily available before the clock edge. Whereas the
cascade counter will take long time as the output of one flop is
used as clock to the other. So the delay will be propagating. For
E.g.: 16 state counter = 4 bit counter = 4 Flip flops Let 10ns be
the delay of each flop The worst case delay of ripple counter = 10
* 4 = 40ns The delay of synchronous counter = 10ns only.(Delay
of 1 flop)
Verilog Interview Questions
34. Question 34. Difference Between Synchronous And
Asynchronous Reset?
Answer :
Synchronous reset logic will synthesize to smaller flip-flops,
particularly if the reset is gated with the logic generating the
 dinput. But in such a case, the combinational logic gate count
grows, so the overall gate count savings may not be that
significant. The clock works as a filter for small reset glitches;
however, if these glitches occur near the active clock edge, the
Flip-flop could go metastable. In some designs, the reset must be
generated by a set of internal conditions. A synchronous reset is
recommended for these types of designs because it will filter the
logic equation glitches between clocks.

Disadvantages of synchronous reset:

Problem with synchronous resets is that the synthesis tool cannot
easily distinguish the reset signal from any other data signal.
Synchronous resets may need a pulse stretcher to guarantee a
reset pulse width wide enough to ensure reset is present during
an active edge of the clock. if you have a gated clock to save
power, the clock may be disabled coincident with the assertion of
reset. Only an asynchronous reset will work in this situation, as
the reset might be removed prior to the resumption of the clock.
Designs that are pushing the limit for data path timing, cannot
afford to have added gates and additional net delays in the data
path due to logic inserted to handle synchronous resets.

Asynchronous reset:
The biggest problem with asynchronous resets is the reset
release, also called reset removal. Using an asynchronous reset,
the designer is guaranteed not to have the reset added to the
data path. Another advantage favoring asynchronous resets is
that the circuit can be reset with or without a clock present.

Disadvantages of asynchronous reset: ensure that the release of

the reset can occur within one clock period. if the release of the
reset occurred on or near a clock edge such that the flip-flops
went metastable.

35. Question 35. Implement The Following Circuits:

Answer :
 (a) 3 input NAND gate using min no of 2 input NAND Gates
(b) 3 input NOR gate using min no of 2 input NOR Gates
(c) 3 input XNOR gate using min no of 2 input XNOR Gates
Assuming 3 inputs A,B,C?
3 input NAND Connect:
a) A and B to the first NAND gate
b) Output of first Nand gate is given to the two inputs of the
second NAND gate (this basically realizes the inverter
functionality)4
c) Output of second NAND gate is given to the input of the third
NAND gate, whose other input is C ((A NAND B) NAND (A NAND
B)) NAND C Thus, can be implemented using '3' 2-input NAND
gates. I guess this is the minimum number of gates that need to
be used.
[Link] Counter Asynchronous Counter

1. In synchronous counter, all In asynchronous counter,

flip flops are triggered with different flip flops are
same clock simultaneously. triggered with different
clock, not
simultaneously.

2. Synchronous Counter is Asynchronous Counter is

faster than asynchronous slower than synchronous
counter in operation. counter in operation.

3. Synchronous Counter does Asynchronous Counter

not produce any decoding produces decoding error.
errors.

4. Synchronous Counter is Asynchronous Counter is

also called Parallel Counter. also called Serial
Counter.

5. Synchronous Counter Asynchronous Counter

designing as well designing as well as
implementation are implementation is very
complex due to increasing easy.
the number of states.
6. Synchronous Counter will Asynchronous Counter
operate in any desired will operate only in fixed
count sequence. count sequence
(UP/DOWN).

7. Synchronous Counter Asynchronous Counter

examples are: Ring examples are: Ripple UP
counter, Johnson counter. counter, Ripple DOWN
counter.

8. In synchronous counter, In asynchronous counter,

propagation delay is less. there is high propagation
delay.
 VERILOG

1. What is the difference between blocking and non-blocking?

Example: "Verilog has two types of procedural assignment statements, blocking

and non-blocking. The two are identified using assignment operators represented by
the symbols = and <=. The blocking assignment statement behaves in a way similar
to older programming languages. The entire statement is completed at once before
control moves on to the following statement. However, the non-blocking operator
evaluates all the right-hand sides for the current time unit and designates the left-
hand sides later at the conclusion of the time unit."

2. Explain Verilog full case and parallel case.

Example: "Full case statements are statements in which every potential case-
expressions' binary patterns are capable of matching to either a case item or default.
If the case statement you are considering does not involve a case default and if you
are likely to discover a binary case expression that does not match any of the
defined case items, the case statement would not be considered full.
A parallel case statement is a statement where it is only possible to match a case
expression, just one case item. If you can find a case expression that would fit more
than one case item, the matching case items are called 'overlapping case items' and
the case statement would be not parallel."

3. What is the difference between a task and a function?

Example: "A function cannot enable a task but functions are capable of enabling
other functions, within functions, no events, timing control statements or delays are
allowed and in every function, there should always be a minimum of one argument.
Also, functions can only yield one value and cannot use input or output statements.
Alternatively, tasks can enable a function and enable additional versions of a certain
task. Tasks are capable of containing any statements and are permitted to use zero
or more arguments, including output, input or input."

4. What is PLI?

Example: "Programming Language Interface, or PLI, is a mechanism that allows

interfacing between Verilog programs and programs written in C language. It also
provides a mechanism to access the internal databases of the simulator within the C
program. Users utilize PLI to implement system calls which is difficult and
sometimes impossible using Verilog syntax. Using PLI lets you take advantage of
both the parallel and hardware related features of Verilog and the sequential
progress of a C program."
5. What is the difference between == and ===?

Example: "The output of == can be either 1, 0 or X. However, the output of === can
only be 0 or 1. If you are comparing two nos using == and if one or both the figures
have one or more bits as X, then the output would be X. But, if you used ===, the
output would be 0 or 1. == can only be used for comparison of 1s and 0s, since It
can not compare Xs. To compare Xs, you would have to incorporate ===."

6. What are $monitor, $display and $strobe?

Example: "They are all commands that have similar syntax and that show text on
the screen while running a simulation. They are typically less convenient to use than
waveform tools, such as cwaves. $display and $strobe appear once each time you
execute them, but $monitor displays each time you change one of the parameters."
The key distinction between $display and $strobe is that $strobe displays the
parameters at the conclusion of the current simulation time unit instead of at the
moment when you execute it. The format sequence is similar to C/C++, and
sometimes contains format characters. Commonly-used format characters include
"%d" for decimal, "%h" for hexadecimal, "%b" for binary, "%c" for character, "%s" for
string, "%t" for time and "%m" for hierarchy level.

7. How would you execute blocking and non-blocking statements?

Example: "To execute blocking assignments, you generally must carry out a simple
process that consists of evaluating the right-hand side equation and updating the
left-hand side expression without interference from another Verilog statement. A
blocking assignment's function is to block trailing assignments until after the
completion of the current assignment. Conversely, the process of executing non-
blocking assignments involves two steps: evaluate the right-hand side of all non-
blocking statements at the start of the time step and update the left-hand side of all
non-blocking statements at the conclusion of the time step."

8. Explain transport delay and inertial delay.

Example: "Transport delay is the delay that is caused by the wires that connect the
gates. Wires delay the signal they carry due to the wire's resistance, inductance and
Capitan. Transport delay is basically propagation delay on a wire. In Verilog,
transport delay is modeled like this: a <= #10 b. Inertial delay is the time that it takes
for a gate to change its output. In Verilog, inertial delay is modeled like so: assign
#10 a = b;."

9. What are the key differences between Verilog and VDHL?

Example: "Verilog is syntactically similar to a C type programming language while

VHDL is more similar to the ADA language. Verilog is easy to learn and simple to
write, but VHDL takes a longer time to learn and requires more complex written
code. Verilog also supports lower-level logic representation, whereas VHDL does
not."
10. What do the terms wire and reg refer to?

Example: "Wire is the physical connection between structural elements that are
necessary for Verilog to function. Its value is designated by a continuous assignment
or a gate output. The register type, also called reg, integer, time, real and real-time,
represents the abstract data storage element. It is assigned values only within an
always statement or an initial statement.
The primary distinction between wire and reg is that wire cannot store value when
there no connection between a and b. Without a connection like a->b, the wire loses
value. However, reg can hold value even if there is not a physical connection. The
default values of wire and reg are Z and X, respectively."

1) What is Verilog?

Verilog is a Hardware Description Language (HDL) used for describing a digital

system such as a network switch, a microprocessor, a memory, or a flip-flop. Verilog
is mainly used to verify analog circuits, mixed-signal circuits, and the design of
genetic circuits. It is also used in the design and verification of digital circuits at the
register-transfer level of abstraction.

Verilog supports a design mainly at the following three levels of abstraction:

o Behavioral level
o Register-transfer level
o Gate level

2) Who is the founder of the Verilog programming language?

Verilog was introduced by Prabhu Goel, Phil Moorby, Chi-Lai Huang, and Douglas
Warmke between late 1983 and early 1984.

28.6M
657
Features of Java - Javatpoint

3) What is VHDL? / What is the full form of VHDL in VLSI?

VHDL is an acronym that stands for Very high-speed integrated circuit Hardware
Description Language. It is a programming language used to describe circuits in
digital systems and model the digital system by using dataflow, behavioral and
structural style of modeling.
4) What are the different variants of the VHDL?

VHDL is defined by IEEE standards and has mainly two common variants:

o VHDL-1987
o VHDL-1993

5) What are the main usages of VHDL?

Following are the main usages of VHDL:

o VHDL is hardware describing language used to describe the behavior of

electronic circuits, most commonly digital circuits.
o It is mainly used to design hardware and create test entities to verify the
behavior of that hardware.
o It is used as a design entry format by various EDA tools, such as synthesis
tools, simulation tools, and formal verification tools.

6) Are Verilog and VHDL the same?

Verilog and VHDL are not identical. They are different, and the main difference
between Verilog and VHDL is that Verilog is based on C language while VHDL is
based on Ada and Pascal languages.

7) What is the difference between Verilog and VHDL?

Difference between Verilog and VHDL:

Although both Verilog and VHDL are Hardware Description Languages (HDL) used
to describe digital system hardware such as microprocessors and flip-flops. These
languages are different from common programming languages. Let's compare them
to see the main differences between them:

Verilog VHDL

Verilog is a kind of Hardware Description VHDL is a kind of Hardware Description Langu

Languages (HDL) that is used to model electronic design automation to describe digita
electronic systems. systems such as field-programmable gate arr
circuits.
 Verilog is a newer language than VHDL, as it VHDL is an older Hardware Description Langua
was introduced in 1984. Verilog as it was introduced in 1980.

Verilog is based on the C language. VHDL is based on Ada and Pascal languages.

Verilog is a case-sensitive language. VHDL is not a case-sensitive language.

Verilog is a simple and easy-to-learn language. VHDL is complex in comparison to the Verilog la

Verilog mainly focuses on hardware modeling VHDL is a rich and strongly typed language. It
but has a lower level of programming more verbose than Verilog.
constructs. So, it is not as verbose as VHDL.

Verilog is more compact than VHDL. In VHDL, you have to write more lines of code.

Verilog is weakly typed and deterministic. All VHDL is self-documenting and often catches
data types are predefined in Verilog, and each Verilog. It focuses on unambiguous semantic
has a bit-level representation. portability between tools.

8) What are HDL simulators?

HDL simulators are software packages that are used to simulate expressions written
in one of the Hardware Description Languages, such as Verilog, VHDL,
SystemVerilog.

9) What is the difference between blocking and non-blocking in Verilog?

There are two types of procedural assignment statements in Verilog known as

blocking and non-blocking. You can identify them as they use different assignment
operators represented by the symbols = and <=.

o Blocking: The blocking assignment statement is very much similar to older

programming languages. As the name suggests, it blocks the current process
until it complete. It completes the entire statement at once before control
moves on to the following statement.
o Non-blocking: The non-blocking assignment statement or operator assesses
all the right-hand sides for the current time unit and chooses the left-hand
sides later after the time unit.

10) What do you understand by Verilog full case statements and Verilog parallel
case statements?
There are two types of case statements in Verilog.

o Verilog full case statements

o Verilog parallel case statements

Verilog full case statements

The Verilog full case statements are statements in which binary patterns of every
potential case expression can match either a case item or default. If your considered
case statement does not involve a case default and is likely to discover a binary case
expression that does not match any of the defined case items, the case statement
would not be considered full.

Verilog parallel case statements

A parallel case statement is a statement where it matches a case expression, just

one case item. If you can find a case expression that would fit more than one case
item, the matching case items are called 'overlapping case items,' and the case
statement would be not parallel."

11) What are the main differences between Task and Function in Verilog?

Following is a list of main differences between a Task and a Function in Verilog:

Functions Tasks

In Verilog, a function cannot enable a task; however, a In Verilog, tasks can enable a f
function can enable other functions. enable other versions of tasks.

A function cannot contain any event, delay, or timing control A task can contain any event, dela
statements because they are not permitted. statements because it is allowed
these statements.

A function can carry out its required duty in zero simulation Tasks also run with a zero simula
time because the program time is not incremented during they can also be executed in a
the function routine. time.

At the time of the invocation of a function, it must pass at A task is allowed to use zero or
least one argument. type output or input.

Functions only return a single value and cannot use either A task cannot return a value but
output or input statements. values via the output and input stat

12) What is the full form of PLI? Why is it used?

PLI is an acronym that stands for Programming Language Interface. It is a
mechanism that facilitates interfacing between Verilog programs and programs
written in C language. It also provides a mechanism used to access the internal
databases of the simulator within the C program. Using Verilog syntax, the users can
utilize PLI to implement difficult system calls. It also provides the advantage of both
the parallel and hardware-related features of Verilog and the sequential progress of
a C program.

13) What do you understand by Sensitivity list?

The sensitivity list is used to specify that when you make changes in any one of the
elements in the list change, begin end statement inside that always will get executed.

14) What is the difference between == and === in Verilog?

Following is a list of main differences between == and === in Verilog:

== ===

In Verilog, the main difference between == and === is that the output On the other hand, the
of == can be either 1, 0 or X. only be 0 or 1.

If you compare two numbers using == and if one or both the figures If you are comparing t
have one or more bits as X, then the output would be X. ===, the output would be

== can only be used to compare 1s and 0s since it cannot compare Xs. === can also be used to

15) What do you understand by $monitor, $display, and $strobe?

The $monitor, $display, and $strobe are commands with similar syntax and show
text on the screen while running a simulation. These commands are typically less
convenient to use than waveform tools, such as cwaves.
The $display and $strobe command appear once each time you execute them, but
the $monitor command is used to display each time you change one of the
parameters.

The main difference between the $display and the $strobe command is that the
$strobe command is used to display the parameters after the current simulation time
unit. On the other hand, the $display command displays the parameters when you
execute it. In these commands, the format sequence is similar to C/C++ and
sometimes contains format characters. The most commonly-used format characters
are "%d" for decimal, "%h" for hexadecimal, "%b" for binary, "%c" for character, "%s"
for string, "%t" for time, and "%m" for hierarchy level.
16) What is the difference between $monitor and $display?

The $monitor and $display are system functions or command and are used to see
the test bench results. Following is a list of some key differences between $monitor
and $display.

$monitor $display

The monitor is used to make changes in the value of the signal. A It is used to display the valu
signal can be variable, string, or expression. signal.

The monitor command can be invoked only once. The display command ca
invoked more than once.

17) What are the main differences between Wire and Reg?

Key differences between Wire and Reg

Wire Reg

The wire is used to assume value. Reg is used to hold value.

Wire requires drivers to get output values. Reg does not need a driver to get output.

The wire elements can only be used to model The reg elements can also be used for co
combinational logic. as sequential logic.

We can use wire at the left-hand side of an We cannot use reg on the left-hand si
assigned statement. statement.

18) What is the process to execute blocking and non-blocking assignments?

There is a simple process to execute blocking and non-blocking assignments. To

execute blocking assignments, we have to use a simple process of evaluating the
right-hand side equation and updating the left-hand side expression without
interference from another Verilog statement. A function of a blocking assignment is
to block trailing assignments until after the completion of the current assignment. On
the other hand, the process of executing non-blocking assignments needs two steps:

o Evaluate the right-hand side of all non-blocking statements at the start of the
time step.
o Update the left-hand side of all non-blocking statements after the time step.
19) What do you understand by continuous assignment?

In Verilog, the continuous assignment statements are used to model combinational

logic. By combinational logic, we mean the digital logic implemented by Boolean
circuits. In combinational logic, the output is a pure function only of present inputs.
The combinational logic is completely different from sequential logic, where the
present input depends on the present input and the past inputs. The continuous
assignment statements are implemented with an assigned statement or with a wire
declaration.

A continuous assignment is used to drive values to the net. The left-hand side can
be scalar, vector net, or concatenation of both, while the right-hand side can be
scalar or vector net or register or concatenation of both.

20) What are the full case and parallel case statements?

Full case statement: The full case is a case statement in which all possible case
expressions can be matched with case items or case default.

Parallel case statement: A parallel case statement is a case statement in which it is

possible to match a case expression with one and only one case item. If you find a
case expression that would match more than one case item, the matching case is
called an overlapping or non-parallel statement.

21) What do you understand by transport delay and inertial delay?

Transport delay: Transport delay is a type of delay caused by the wires that
connect to the gates. Due to the wire's resistance and inductance, it delays the
signal.

Inertial delay: The inertial delay is the time it takes for a gate to change its output.

22) How can you write an FSM code in Verilog?

There are mainly four ways to write FSM code in Verilog:

o Using the first method where all input decoders, present state, and output
decoder are combined in one process.
o Using the second method where all combinational circuits and sequential
circuits are separated in a different process.
 o Using the third method, where input decoder and present state are combined,
and output decoder are separated in other processes.
o Using the fourth method, all three input decoders, present state, and output
decoder are separated into three processes.

23) In a pure combinational circuit, is it necessary to mention all the inputs in the
sensitivity disk? If yes, then why?

Yes. In a pure combinational circuit, it is necessary to mention all the inputs in the
sensitivity disk; otherwise, you will get a pre and post-synthesis mismatch in the
result.

24) Which will be updated first between variable and signal?

Signals are updated first between variable and signal.

25) What do you understand by the freeze, deposit, drive, and force command in
Verilog?

The freeze, deposit, drive, and force are commands used in Verilog that can be
defined in the following way:

o Freeze: The freeze command is used to put a value on the signal. This value
remains the same throughout the simulation and cannot be overwritten by
simulation.
o Deposit: The deposit command is also used to value the signal, but it will
hold until it is overwritten. For example, if you deposit 0 to a flip flop, it will
remain a '0' until the simulation updates it to a new value. It is like giving an
initial value to a signal.
o Drive: The drive command is used to put a value to a signal, and if it is
updated by simulation, it will then 'resolve' to a new value. For example, if you
drive a signal to '1', and the simulation value is '0', the signal will go 'X.'
o Force: The force is a powerful Verilog command which you can use to drive
signals at any timestamp of your simulation.
26) Write a Verilog code to swap contents of two registers with and without a
temporary register?

A Verilog code to swap contents of two registers with a temporary register:

1. always @ (posedge clock)

2. begin
3. temp=b;
4. b=a;
5. a=temp;
6. end

A Verilog code to swap contents of two registers without a temporary register:

1. always @ (posedge clock)

2. begin
3. a <= b;
4. b <= a;
5. end

27) What does the timescale 1 Ns/ 1 Ps signify in a Verilog code?

The timescale directive is a compiler directive used to measure simulation time or

delay time. The timescale / reference_time_unit specifies the unit of measurement
for times and delays. The time_precision specifies the precision to which the delays
are rounded off.

28) What is the difference between $setup and $hold?

In Verilog, the $setup and $hold are used to monitor the setup and hold time
constraints for sequential logic. The setup time is the minimum time in which the data
must arrive before the active edge of a clock signal. The hold time is the minimum
time in which the data cannot change after the active edge of a clock signal.

These two constraints are defined in the following image:

29) How can you generate a sine wave using the Verilog coding style?

In Verilog, the easiest and efficient way to generate sine waves is using CORDIC
Algorithm.

30) What do you understand by casex and casez statements in Verilog?

The casex and casez are the types of case statements in Verilog. Here, casez treats
all z values in the case alternatives or the case expression as don't cares. All bit
positions with z can also be represented by ? in that position. casex treats all x and z
values in the case item or the case expression as don't cares. Don't cares are not
allowed in the case statement so, we have to use casex and casez.

31) What is a repeat loop in Verilog?

The repeat loop is used to execute loop fixed for several times. It is not used to loop
expression such as we see in the while loop statement. It contains constant,
variable, or signal. For example, repeat(5).

[Link] 1. Write A Verilog Code To Swap Contents Of Two Registers

With And Without A Temporary Register?
Answer :
With temp reg ;
always @ (posedge clock)
begin
 temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin
a <= b;
b <= a;
end
[Link] 2. Difference Between Task And Function?
Answer :
Function:
o A function is unable to enable a task however functions can
enable other functions.
o A function will carry out its required duty in zero simulation
time. ( The program time will not be incremented during the
function routine)
o Within a function, no event, delay or timing control statements
are permitted
o In the invocation of a function their must be at least one
argument to be passed.
o Functions will only return a single value and can not use either
output or inout statements.
Tasks:
o Tasks are capable of enabling a function as well as enabling
other versions of a Task
o Tasks also run with a zero simulation however they can if
required be executed in a non zero simulation time.
o Tasks are allowed to contain any of these statements.
o A task is allowed to use zero or more arguments which are of
type output, input or inout.
 o A Task is unable to return a value but has the facility to pass
multiple values via the output and inout statements .
Perl Scripting Interview Questions
[Link] 3. Difference Between Inter Statement And Intra Statement
Delay?
Answer :
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
[Link] 4. Difference Between $monitor,$display & $strobe?
Answer :
These commands have the same syntax, and display text on the screen
during simulation. They are much less convenient than waveform display
tools like cwaves?. $display and $strobe display once every time they are
executed, whereas $monitor displays every time one of its parameters
changes.
 The difference between $display and $strobe is that $strobe displays the
parameters at the very end of the current simulation time unit rather than
exactly where it is executed. The format string is like that in C/C++, and
may contain format characters. Format characters include %d (decimal),
%h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time),
%m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the
number instead of the space needed. Append b, h, o to the task name to
change default format to binary, octal or hexadecimal.

Syntax:
$display (“format_string”, par_1, par_2, ... );
$strobe (“format_string”, par_1, par_2, ... );
$monitor (“format_string”, par_1, par_2, ... );
Perl Scripting Tutorial
[Link] 5. What Is Difference Between Verilog Full Case And Parallel
Case?
Answer :
A "full" case statement is a case statement in which all possible case-
expression binary patterns can be matched to a case item or to a case
default. If a case statement does not include a case default and if it is
possible to find a binary case expression that does not match any of the
defined case items, the case statement is not "full."

A "parallel" case statement is a case statement in which it is only possible

to match a case expression to one and only one case item. If it is possible
to find a case expression that would match more than one case item, the
matching case items are called "overlapping" case items and the case
statement is not "parallel."
Shell Scripting Interview Questions
[Link] 6. What Is Meant By Inferring Latches,how To Avoid It?
Answer :
Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0})
2'd0 : out = i0;
 2'd1 : out = i1;
2'd2 : out = i2;
endcase
in a case statement if all the possible combinations are not compared and
default is also not specified like in example above a latch will be inferred ,a
latch is inferred because to reproduce the previous value when unknown
branch is specified.

For example in above case if {s1,s0}=3 , the previous stored value is

reproduced for this storing a latch is inferred.

The same may be observed in IF statement in case an ELSE IF is not

specified.

To avoid inferring latches make sure that all the cases are mentioned if not
default condition is provided.

[Link] 7. Tell Me How Blocking And Non Blocking Statements Get

Executed?
Answer :
Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-
hand side expression) of the blocking assignment without interruption from
any other Verilog statement. A blocking assignment "blocks" trailing
assignments in the same always block from occurring until after the current
assignment has been completed

Execution of nonblocking assignments can be viewed as a two-step

process:

o Evaluate the RHS of nonblocking statements at the beginning

of the time step.
o Update the LHS of nonblocking statements at the end of the
time step.
Shell Scripting Tutorial System Administration Interview Questions
[Link] 8. Variable And Signal Which Will Be Updated First?
Answer :
Signals
[Link] 9. What Is Sensitivity List?
Answer :
The sensitivity list indicates that when a change occurs to any one of
elements in the list change, begin…end statement inside that always block
will get executed.
System Verilog Interview Questions
10. Question 10. In A Pure Combinational Circuit Is It Necessary To
Mention All The Inputs In Sensitivity Disk? If Yes, Why?
Answer :
Yes in a pure combinational circuit is it necessary to mention all the inputs
in sensitivity disk other wise it will result in pre and post synthesis
mismatch.
VLSI Design Tutorial
11. Question 11. Tell Me Structure Of Verilog Code You Follow?
Answer :
A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the
simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration - register types (only assigned
within always statements). reg register
variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration - (only assigned outside always
statements) wire net variable 1;
// hierarchy - instantiating another module
 reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule
VHDL Interview Questions
12. Question 12. Difference Between Verilog And Vhdl?
Answer :
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the
same system file, may be separately compiled if so desired. However, it is
good design practice to keep each design unit in it's own system file in
which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative

mode. Compilation is a means of speeding up simulation, but has not
changed the original nature of the language. As a result care must be
taken with both the compilation order of code written in a single file and the
compilation order of multiple files. Simulation results can change by simply
changing the order of compilation.

Data types
 VHDL. A multitude of language or user defined data types can be used.
This may mean dedicated conversion functions are needed to convert
objects from one type to another. The choice of which data types to use
should be considered wisely, especially enumerated (abstract) data types.
This will make models easier to write, clearer to read and avoid
unnecessary conversion functions that can clutter the code. VHDL may be
preferred because it allows a multitude of language or user defined data
types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to

use and very much geared towards modeling hardware structure as
opposed to abstract hardware modeling. Unlike VHDL, all data types used
in a Verilog model are defined by the Verilog language and not by the user.
There are net data types, for example wire, and a register data type called
reg. A model with a signal whose type is one of the net data types has a
corresponding electrical wire in the implied modeled circuit. Objects, that is
signals, of type reg hold their value over simulation delta cycles and should
not be confused with the modeling of a hardware register. Verilog may be
preferred because of it's simplicity.

Design reusability
VHDL. Procedures and functions may be placed in a package so that they
are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and

procedures used within a model must be defined in the module. To make
functions and procedures generally accessible from different module
statements the functions and procedures must be placed in a separate
system file and included using the `include compiler directive.
Perl Scripting Interview Questions
13. Question 13. Can You Tell Me Some Of System Tasks And Their
Purpose?
Answer :
$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.
 The most useful of these is $[Link] can be used for displaying
strings, expression or values of variables.

Here are some examples of usage.

$display("Hello oni");
--- output: Hello oni
$display($time) // current simulation time.
--- output: 460
counter = 4'b10;
$display(" The count is %b", counter);
--- output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and
puts it in interactive mode where the user can enter commands; $finish
exits the simulator back to the operating system
14. Question 14. Can You List Out Some Of Enhancements In Verilog
2001?
Answer :
In earlier version of Verilog ,we use 'or' to specify more than one element in
sensitivity list . In Verilog 2001, we can use comma as shown in the
example below.

// Verilog 2k example for usage of comma

always @ (i1,i2,i3,i4)
Verilog 2001 allows us to use star in sensitive list instead of listing all the
variables in RHS of combo logics . This removes typo mistakes and thus
avoids simulation and synthesis mismatches, Verilog 2001 allows port
direction and data type in the port list of modules as shown in the example
below

module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
 output [7:0] data_out
);
15. Question 15. Write A Verilog Code For Synchronous And
Asynchronous Reset?
Answer :
Synchronous reset, synchronous means clock dependent so reset must not
be present in sensitivity disk

eg: always @ (posedge clk )

begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in
sensitivity list.

Eg: Always @(posedge clock or posedge reset)

begin
if (reset)
. . . end
VLSI Interview Questions
16. Question 16. What Is Pli?why Is It Used?
Answer :
Programming Language Interface (PLI) of Verilog HDL is a mechanism to
interface Verilog programs with programs written in C language. It also
provides mechanism to access internal databases of the simulator from the
C program.

PLI is used for implementing system calls which would have been hard to
do otherwise (or impossible) using Verilog syntax. Or, in other words, you
can take advantage of both the paradigms - parallel and hardware related
features of Verilog and sequential flow of C - using PLI.

17. Question 17. There Is A Triangle And On It There Are 3 Ants One On
Each Corner And Are Free To Move Along Sides Of Triangle What Is
Probability That They Will Collide?
Answer :
 Ants can move only along edges of triangle in either of direction, let’s say
one is represented by 1 and another by 0, since there are 3 sides eight
combinations are possible, when all ants are going in same direction they
won’t collide that is 111 or 000 so probability of not collision is 2/8=1/4 or
collision probability is 6/8=3/4
Ethernet Interview Questions
18. Question 18. How To Write Fsm Is Verilog?
Answer :
there r mainly 4 ways 2 write fsm code

o using 1 process where all input decoder, present state, and

output decoder r combine in one process.
o using 2 process where all comb ckt and sequential ckt
separated in different process
o using 2 process where input decoder and persent state r
combine and output decoder seperated in other process
o using 3 process where all three, input decoder, present state
and output decoder r separated in 3 process.
Shell Scripting Interview Questions
19. Question 19. What Is Difference Between Freeze Deposit And Force?
Answer :
$deposit(variable, value);

This system task sets a Verilog register or net to the specified value.
variable is the register or net to be changed; value is the new value for the
register or net. The value remains until there is a subsequent driver
transaction or another $deposit task for the same register or net. This
system task operates identically to the ModelSim force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none
of these is specified, then -freeze is assumed for unresolved signals and -
drive is assumed for resolved signals. This is designed to provide
compatibility with force files. But if you prefer -freeze as the default for both
resolved and unresolved signals.
20. Question 20. Will Case Infer Priority Register If Yes How Give An
Example?
Answer :
yes case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
end
Advanced C++ Interview Questions
21. Question 21. Given The Following Verilog Code, What Value Of "a" Is
Displayed?
Answer :
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
This is a tricky one! Verilog scheduling semantics basically imply a four-
level deep queue for the current simulation time:

o Active Events (blocking statements)

o Inactive Events (#0 delays, etc)
o Non-Blocking Assign Updates (non-blocking statements)
o Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".

The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
 Finally, the display statement is placed into the 4th queue. Only events in
the active queue are completed this sim cycle, so the "a = 0" happens, and
then the display shows a = 0. If we were to look at the value of a in the next
sim cycle, it would show 1.

22. Question 22. What Is The Difference Between The Following Two
Lines Of Verilog Code?
Answer :
#5 a = b;
a = #5 b;
#5 a = b;
Wait five time units before doing the action for "a = b;".

a = #5 b; The value of b is calculated and stored in an internal temp

register,After five time units, assign this stored value to a.

23. Question 23. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog

Code?
Answer :
'timescale directive is a compiler [Link] is used to measure simulation
time or delay time. Usage :`timescale / reference_time_unit : Specifies the
unit of measurement for times and delays. time_precision: specifies the
precision to which the delays are rounded off.
Basic C Interview Questions
24. Question 24. What Is The Difference Between === And == ?
Answer :
output of "==" can be 1, 0 or X.
output of "===" can only be 0 or 1.
When you are comparing 2 nos using "==" and if one/both the numbers
have one or more bits as "x" then the output would be "X" . But if use "==="
outpout would be 0 or 1.

e.g A = 3'b1x0
B = 3'b10x
A == B will give X as output.
A === B will give 0 as output.
 "==" is used for comparison of only 1's and 0's .It can't compare Xs. If any
bit of the input is X output will be X

"===" is used for comparison of X also.

System Administration Interview Questions
25. Question 25. How To Generate Sine Wav Using Verilog Coding Style?
Answer :
The easiest and efficient way to generate sine wave is using CORDIC
Algorithm.

26. Question 26. What Is The Difference Between Wire And Reg?
Answer :
(wire,tri)Physical connection between structural elements. Value assigned
by a continuous assignment or a gate output. Register type: (reg, integer,
time, real, real time) represents abstract data storage element. Assigned
values only within an always statement or an initial statement. The main
difference between wire and reg is wire cannot hold (store) the value when
there no connection between a and b like a->b, if there is no connection in
a and b, wire loose value. But reg can hold the value even if there in no
connection. Default values:wire is Z,reg is x.
ASIC Interview Questions
27. Question 27. How Do You Implement The Bi-directional Ports In
Verilog Hdl?
Answer :
module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
 assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct

always @ (posedge clk)

begin
b <= bidir;
a <= inp;
end
endmodule
System Verilog Interview Questions
28. Question 28. What Is Verilog Case (1) ?
Answer :
wire [3:0] x;
always @(...) begin
case (1'b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end
The case statement walks down the list of cases and executes the first one
that matches. So here, if the lowest 1-bit of x is bit 2, then something3 is
the statement that will get executed (or selected by the logic).

29. Question 29. Why Is It That "if (2'b01 & 2'b10)..." Doesn't Run The True
Case?
Answer :
This is a popular coding error. You used the bit wise AND operator (&)
where you meant to use the logical AND operator (&&).
Universal Verification Methodology (UVM) Interview Questions
30. Question 30. What Are Different Types Of Verilog Simulators ?
Answer :
There are mainly two types of simulators available.
 o Event Driven
o Cycle Based
Event-based Simulator:
This Digital Logic Simulation method sacrifices performance for rich
functionality: every active signal is calculated for every device it propagates
through during a clock cycle. Full Event-based simulators support 4-28
states; simulation of Behavioral HDL, RTL HDL, gate, and transistor
representations; full timing calculations for all devices; and the full HDL
standard. Event-based simulators are like a Swiss Army knife with many
different features but none are particularly fast.

Cycle Based Simulator:

This is a Digital Logic Simulation method that eliminates unnecessary
calculations to achieve huge performance gains in verifying Boolean logic:

o Results are only examined at the end of every clock cycle; and
o The digital logic is the only part of the design simulated (no
timing calculations). By limiting the calculations, Cycle based
Simulators can provide huge increases in performance over
conventional Event-based simulators.
Cycle based simulators are more like a high speed electric carving knife in
comparison because they focus on a subset of the biggest problem: logic
verification.

Cycle based simulators are almost invariably used along with Static Timing
verifier to compensate for the lost timing information coverage.