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Assignment Array

The document outlines various assignments related to memory declaration and manipulation in Verilog, including initializing arrays, printing values, and generating random numbers. It also discusses a half adder implementation and the representation of a specific value in different radix formats. Additionally, it covers the use of seeds in random number generation and the handling of strings in Verilog as reg vectors.

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11 views5 pages

Assignment Array

The document outlines various assignments related to memory declaration and manipulation in Verilog, including initializing arrays, printing values, and generating random numbers. It also discusses a half adder implementation and the representation of a specific value in different radix formats. Additionally, it covers the use of seeds in random number generation and the handling of strings in Verilog as reg vectors.

Uploaded by

coreexcellence.admn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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16-07-2025

Assignment

1) Declare Memory size 1KB depth 128

Answer:reg[63:0]mem[127:0];

2) Memory size 2Kb, Width 16

Answer: reg[15:0]mem[63:0];

3) Write a code to print all array values

Answer : integer index =10;

Initial begin

for(index =0;index<=7;index=index+1)

data_out[index]<=1;

end

4) Write a code to initialize all values to zero and print all those values after
initialization

Answer: reg[123:0] parity=0;

5) Assign all array elements with random values between 50-59

intA[i] = $urandom_range(50-59);

Task to complete
6) Declare another integer array copy the first array element to another and then
compare the both the elements
7) In the above code insert a task called print array () to print the array elements
8) Assign array elements with a random values b/w 1.5-2.5
9) Declare an array with random values assigned without repetition of values
10) Assign a random values b/w 30 to 60 without using $urandom_range.

Discussion questions

1. reg [3:0] a,c, d;


reg [4:0] b, e f;
{a,b,c,d,e,f} = {10’h123, 20’h4569A};
values of a to f?
2. write a half adder code in verilog
3. represent wdata(size is 10 bits) with value 578 using 10bit size in all
radix format?

1. reg [3:0] a,c, d;


reg [4:0] b, e f;
{a,b,c,d,e,f} = {10’h123, 20’h4569A};
values of a to f?
Answer
2. write a half adder code in Verilog
module Half_adder(
input a,b,
output sum,carry);

xor(sum,a,b); //structural module

and(carry,a,b);

endmodule

module half_adder(input a,b, output reg sum, carry);

always @(*)

begin

sum=a^b; //behavioral level

carry=a&b;

end

endmodule

module halfadder( input a,b, output s,c);


assign s=a^b;

assign c=a&b;

endmodule

4. represent wdata(size is 10 bits) with value 578 using 10bit size in all
radix format?
Answer:
(578)10=¿
( 578 )10 =( 1001000010 ) 2
( 578 )10 =(1102)8
16-07-2025

Theory Section

Agenda:

 Seed in $random
 String
 Hierarchal modelling

Seed in $random

To start from a particular point, we are using “seed”

Without using seed same some set of random values will show the output
how many times you run the code, by using seed it will generate the different
random values.

Ex: module tb();

Integer a;

integer seed;

initial begin

$value$plusargs(“seed=%d”,seed);

Repeat(10) begin

a=$random(seed);

$display(“a=%d”,a);

end

end

endmodule
String

Verilog does not have string keyword

Strings are stored using ASIC format as a reg vectors

String has to hold the value unless no change in data

Ex: reg[8*13-1:0] string_val;

string_val = “hello verilog”;

Verilog is static on nature, size once declared can’t be changed during the
execution. Essentially string in Verilog is reg vector which is compulsory
multiple of 8.

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