SCSB1301 - COMPUTER ARCHITECTURE AND ORGANIZATION

UNIT I – GENERAL REGISTERS

Introduction – General Register Organization – Stack Organization – Basic Computer
Organization – Instruction codes – Computer Registers – Computer Instructions – Instruction
Cycle

Introduction
In the study of computer architecture, one of the fundamental components to understand is the
concept of general registers within the CPU. The CPU, or Central Processing Unit, serves as
the brain of the computer, executing instructions from programs through a cycle of fetching,
decoding, executing, and storing. Within the CPU, registers play a critical role by providing
small, fast storage locations that hold data temporarily during instruction execution. Registers
can be categorized into general-purpose registers (GPRs) and special-purpose registers. GPRs
are versatile and used for a wide range of functions including arithmetic operations, temporary
data storage, intermediate results, data transfer, and addressing.

Components of CPU

• Control Unit (CU)

• ALU (Arithmetic Logic Unit)
• Memory or Storage Unit
• Registers
Control Unit

As its name implies, a control unit acts as the "brain" of the CPU. A major role of a control
unit is to manage and execute instructions to perform the tasks specified by a computer
program. v. A CPU executes instructions by fetching them from memory, decodes them, and
then executes them. So, it plays a vital role in fetch-decode-execute instructions.

Functions of Control Unit

• Instruction Fetch − A CU fetches instructions from RAM (Random Access Memory).
• Instruction Decoding − It decodes the fetched instructions to operate.
• Instruction Execution − A CU sends control signals to perform operations like ALU
for arithmetic and logical operations.
• Control Flow Management − It controls flow by updating the programme counter.
• Exception Handling − A control unit effectively manages exceptions and interruptions
like hardware failures, system calls, and external events, by appropriately diverting the
control flow of the CPU to the planned procedure for managing such exceptions.
• Synchronization − A CU plays a crucial role in facilitating the coordination of
instruction execution across several cores.
Arithmetic Logic Unit (ALU)

The Arithmetic Logic Unit (ALU) is a component that has been extensively optimised and
engineered to do multiple tasks concurrently. It is commonly built to execute operations
speedily. It works in conjunction with other CPU components, such as registers, memory, and
control units, to execute complex instructions.

Functions of an ALU
• Arithmetic Operations − The ALU can perform basic arithmetic operations.
• Logic Operations − The ALU can also perform logical operations like AND, OR,
NOT, XOR, and bit-shifting operations.
Memory Unit

A memory is a hardware component which is used to store and access the data whenever
required. Majorly; computer memory is categorised into two parts Primary Memory (RAM)
and Secondary Memory (Hard Disk). RAM is used for short-term, fast data access and is
essential for active program execution. On the other hand, storage or secondary memory
provides permanent data storage. Hence, memory and storage units both are critical
components of a computer system.

Functions of memory

Primary Memory

• RAM is also known as primary or temporary memory; it is a type of volatile memory

used for temporarily storing data.
• The contents inside the RAM are erased when the computer’s power gets off or
restarted.
• RAM is actively used for program or instruction execution.
• Once we start the computer; system necessary files, programs and operating system
files are loaded into the RAM for the smooth running of the computer.
• The more RAM a computer has, the better it can handle multitasking and the faster it
can run applications since data can be accessed more quickly.

Functions of the CPU

The key functions of a CPU are as follows −

• The CPU performs arithmetic and logic operations.

• It directs the operation of the processor.
• It directs Input and output units that how to respond to the instructions that have been
communicated to the processor.
• A CPU contains registers which are considered small storage locations within the CPU
to hold data temporarily during execution of a program.
• A CPU executes instructions by fetching them from memory, decodes them, and then
executes them.

General Register Organization

A set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU.
They include combinational circuits that implement data processing. The information is always
defined in a register before processing. The registers speed up the implementation of programs.

Registers implement two important functions in the CPU operation are as follows −
 • It can support a temporary storage location for data. This supports the directly
implementing programs to have fast access to the data if required.
• It can save the status of the CPU and data about the directly implementing program.

Example − Address of the next program instruction, signals get from the external devices and
error messages, and including different data is saved in the registers.

If a CPU includes some registers, therefore a common bus can link these registers. A general
organization of seven CPU registers is displayed in the figure.

The CPU bus system is managed by the control unit. The control unit explicit the data flow
through the ALU by choosing the function of the ALU and components of the system.

Consider R1 ← R2 + R3, the following are the functions implemented within the CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.

ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).

Decoder Destination Selector (SELD) − It can transfers the result into R1.

The multiplexers of 3-state gates are performed with the buses. The state of 14 binary selection
inputs determines the control word. The 14-bit control word defines a micro-operation.

For example:

MULT R1, R2, R3

This is an instruction of an arithmetic multiplication written in assembly language. It uses three

address fields R1, R2, and R3. The meaning of this instruction is:

R1 <-- R2 * R3

This instruction also can be written using only two address fields as:

MULT R1, R2

In this instruction, the destination register is the same as one of the source registers. This means
the operation

R1 <-- R1 * R2

The use of a large number of registers results in a short program with limited instructions.

The encoding of register selection fields is specified in the table.

Encoding of Register Selection Field

Binary Code SELA SELB SELD

000 Input Input None

001 R1 R1 R1
 Binary Code SELA SELB SELD

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7

There are several micro-operations are implemented by the ALU. Few of the operations
implemented by the ALU are displayed in the table.

Encoding of ALU Operations

OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 ADD A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

 OPR Select Operation Symbol

10000 Shift right A SHRA

11000 Shift left A SHLA

There are some ALU micro-operations are shown in the table.

ALU Micro-Operations

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

Stack Organization
Stack is also known as the Last In First Out (LIFO) list. It is the most important feature in the CPU.
It saves data such that the element stored last is retrieved first. A stack is a memory unit with an
address register. This register influence the address for the stack, which is known as Stack Pointer
(SP). The stack pointer continually influences the address of the element that is located at the top
of the stack.
It can insert an element into or delete an element from the stack. The insertion operation is known
as push operation and the deletion operation is known as pop operation. In a computer stack, these
operations are simulated by incrementing or decrementing the SP register.

Register Stack

The stack can be arranged as a set of memory words or registers. Consider a 64-word register stack
arranged as displayed in the figure. The stack pointer register includes a binary number, which is
the address of the element present at the top of the stack. The three-element A, B, and C are located
in the stack.

The element C is at the top of the stack and the stack pointer holds the address of C that is 3. The
top element is popped from the stack through reading memory word at address 3 and decrementing
the stack pointer by 1. Then, B is at the top of the stack and the SP holds the address of B that is 2.
It can insert a new word, the stack is pushed by incrementing the stack pointer by 1 and inserting a
word in that incremented location.

The stack pointer includes 6 bits, because 26 = 64, and the SP cannot exceed 63 (111111 in binary).
After all, if 63 is incremented by 1, therefore the result is 0(111111 + 1 = 1000000). SP holds only
the six least significant bits. If 000000 is decremented by 1 thus the result is 111111.
Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is null, then
the one-bit register ‘EMTY’ is set to 1. The data register DR holds the binary information which is
composed into or readout of the stack.

First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is not full (FULL
= 0), a new element is inserted using the push operation.

The push operation is executed as follows −

SP←SP + 1 It can increment stack pointer

K[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is saved in the SP.
The word from DR is inserted into the stack using the memory write operation. The first element
is saved at address 1 and the final element is saved at address 0. If the stack pointer is at 0, then the
stack is full and ‘FULL’ is set to 1. This is the condition when the SP was in location 63 and after
incrementing SP, the final element is saved at address 0. During an element is saved at address 0,
there are no more empty registers in the stack. The stack is full and the ‘EMTY’ is set to 0.

A new element is deleted from the stack if the stack is not empty (if EMTY = 0). The pop operation
includes the following sequence of micro-operations −

DR←K[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMTY ← 1) Check if stack is empty

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the stack pointer is decremented.
If the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set to 1. This is the condition
when the element in location 1 is read out and the SP is decremented by 1.
Memory Stack
A portion of memory is assigned to a stack operation to implement the stack in the CPU. Here
the processor register is used as a Stack Pointer (SP). The above figure shows the portion of
computer memory divided into three segments: Program Instructions, Data, and Stack.
• Program Counter (PC): It is a register that points to the address of the next
instruction that is going to be executed in the program.
• Address Register (AR): This register points at the collection of data and is used
during the execute phase to read an operand.
• Stack Pointer (SP): It points at the top of the stack and is used to push or pop the
data items in or from the stack.
As we can see in the figure, these three registers are connected to a common address bus and
either one of them can provide an address for memory.

Stack Pointer is first going to point at the address 3001, and then the stack will grow with
the decreasing addresses. It means that the first item is going to be stored at address 3001, the
second item at address 3000, and the items can keep getting stored in the stack until it reaches
the last address 2000 where the last item will be held.Here the data which is getting inserted
into the Stack is obtained from the Data Register and the data retrieved from the Stack is also
read by the Data Register. This operation is used to insert a new data item into the top of the
Stack. The new item can be inserted as follows:-
PUSH
SP ←SP-1
M[SP]← DR
In the first step, the Stack Pointer is decremented to point at the address where the data item
will be stored. Then, by using the memory write operation, the data item from Data Register
gets inserted into the top of the stack ( at the address where the Stack Pointer is pointing).
POP
This operation is used to delete a data item from the top of the Stack. Data item can be deleted
as follows:-
DR←M[SP]
SP←SP+1
In the first step, the top data item is read from the Stack into the Data Register. The Stack
Pointer is then incremented to point at the next data item in the stack. Push or Pop operations
can be performed with the help of the following microoperations:
• Access to memory with the help of Stack Pointer (SP), and
• Updating the stack.
It totally depends upon the organization of the stack whether the Stack Pointer (SP) is updated
by incrementing or decrementing the address values. In this case, the Stack Pointer grows by
decreasing the memory address. The Stack may be made in a way that the Stack Pointer grows
by increasing the memory also. Since the address is always available and automatically updated
in the Stack Pointer, the CPU can refer to the Memory Stack without having to specify an
address.

Basic Computer Organization

Computer organization refers to the operational units and their interconnections that realize the
architectural specifications of a computer. It focuses on the hardware aspects of a computer
system.

1. Components of a Computer System:

• Central Processing Unit (CPU): The CPU is the core component that performs
computations and executes instructions. It includes:
o Arithmetic Logic Unit (ALU): Executes arithmetic and logical operations.
 o Control Unit (CU): Directs the operation of the processor by interpreting and
executing instructions.
o Registers: Small, fast storage locations for temporary data and instructions.
• Memory Unit: Stores data and instructions needed for processing.
o Primary Memory: Includes RAM (volatile memory) and ROM (non-volatile
memory).
o Secondary Memory: Includes hard drives, SSDs, and other storage devices for
long-term data storage.

2. Bus Architecture:

• Definition: A bus is a communication pathway connecting two or more components of

a computer. It is essential for data transfer within the computer system.
• Types of Buses:
o Data Bus: Transfers actual data between components.
o Address Bus: Carries the address of the data (but not the data itself) between
the CPU and memory.
o Control Bus: Carries control signals and coordinates the activities of all
components.

3. Input/Output (I/O) System:

• Function: Manages data exchange between the external environment and the
computer.
• Components: Includes input devices (keyboard, mouse), output devices (monitor,
printer), and I/O interfaces.

4. Memory Hierarchy:

• Organizes memory in a way that balances speed and cost efficiency.

• Levels:
o Registers: Fastest, smallest, and most expensive type of memory, located
within the CPU.
o Cache Memory: Small, fast memory that holds frequently accessed data and
instructions to speed up processing.
 o Main Memory (RAM): Larger, slower than cache, used for temporary data
storage during program execution.
o Secondary Storage: Large, persistent storage used for storing data and
programs long-term (e.g., hard drives, SSDs).

5. Instruction Cycle:

• The process by which the CPU executes an instruction, typically involving:

o Fetch: Retrieving an instruction from memory.
o Decode: Interpreting the instruction.
o Execute: Performing the operation specified by the instruction.
o Store: Writing the result back to memory or a register.

6. Basic Input/Output System (BIOS):

• Function: Initializes and tests hardware components during the booting process and
provides runtime services for operating systems and programs.
• Components: Includes firmware that is stored in ROM and executed when the
computer is powered on.

7. Motherboard:

The main circuit board that houses the CPU, memory, and other essential components. Provides
the necessary circuitry for communication between all hardware components of the computer.

8. Performance Considerations:

• Clock Speed: The speed at which a CPU executes instructions, measured in GHz.
• Cores and Threads: Multi-core processors can execute multiple instructions
simultaneously, increasing performance.
• Cache Size: Larger caches can store more data closer to the CPU, reducing access time
and improving performance.
Instruction Codes

Computer instructions are a set of machine language instructions that a particular processor
understands and executes. A computer performs tasks on the basis of the instruction provided.

An instruction comprises of groups called fields. These fields include:

o The Operation code (Opcode) field which specifies the operation to be performed.
o The Address field which contains the location of the operand, i.e., register or memory
location.
o The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction

2. Register - reference instruction
3. Input-Output instruction

Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit
to specify the addressing mode 'I'.
Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost
bit (bit 15) of the instruction.

A Register-reference instruction specifies an operation on or a test of the AC (Accumulator)

register.

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need a
reference to memory and is recognized by the operation code 111 with a 1 in the leftmost bit
of the instruction. The remaining 12 bits are used to specify the type of the input-output
operation or test performed.

o The three operation code bits in positions 12 through 14 should be equal to 111.
Otherwise, the instruction is a memory-reference type, and the bit in position 15 is taken
as the addressing mode I.
o When the three operation code bits are equal to 111, control unit inspects the bit in
position 15. If the bit is 0, the instruction is a register-reference type. Otherwise, the
instruction is an input-output type having bit 1 at position 15.

Instruction Set Completeness

A set of instructions is said to be complete if the computer includes a sufficient number of
instructions in each of the following categories:

o Arithmetic, logical and shift instructions

o A set of instructions for moving information to and from memory and processor
registers.
o Instructions which controls the program together with instructions that check status
conditions.
o Input and Output instructions

Arithmetic, logic and shift instructions provide computational capabilities for processing the
type of data the user may wish to employ. A huge amount of binary information is stored in
the memory unit, but all computations are done in processor registers. Therefore, one must
possess the capability of moving information between these two units. Program control
instructions such as branch instructions are used change the sequence in which the program is
executed. Input and Output instructions act as an interface between the computer and the user.
Programs and data must be transferred into memory, and the results of computations must be
transferred back to the user.

Instruction Formats:

A computer performs a task based on the instructions provided. Instructions in computers are
comprised of groups called fields. These fields contain different information for computers
which are all written in 0s and 1s. Each field has a different significance or meaning, based
on which a CPU decides what to perform. The most common fields are:

• The operation field specifies the operation to be performed, like addition.

• Address field which contains the location of the operand, i.e., register or
memory location.
• Mode field which specifies how operand is to be founded.
An instruction is of variable length depending upon the number of addresses it contains.
Generally, CPU organization is of three types based on the number of address fields:
• Single Accumulator organization
• General register organization
• Stack organization
In the first organization, the operation is performed using a special register called the
accumulator. In the second, multiple registers are used for the computation purpose. In the
third organization, the work on stack basis operation due to which it does not contain any
address field. We generally see a blend of various organizations applied
Types of Instructions
Based on the number of addresses, instructions are classified as:
Zero Address Instructions
These instructions do not specify any operands or addresses. Instead, they operate on data
stored in registers or memory locations implicitly defined by the instruction. For example, a
zero-address instruction might simply add the contents of two registers together without
specifying the register names.

Zero Address Instruction

A stack-based computer does not use the address field in the instruction. To evaluate an
expression, it is first converted to reverse Polish Notation i.e. Postfix Notation.

Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B
 PUSH A TOP = A

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

One Address Instructions

These instructions specify one operand or address, which typically refers to a memory
location or register. The instruction operates on the contents of that operand, and the result
may be stored in the same or a different location. For example, a one-address instruction
might load the contents of a memory location into a register. This uses an implied
ACCUMULATOR register for data manipulation. One operand is in the accumulator and the
other is in the register or memory location. Implied means that the CPU already knows that
one operand is in the accumulator so there is no need to specify it.

One Address Instruction

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]
 LOAD A AC = M[A]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

Two Address Instructions

These instructions specify two operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of both operands, and the result may be
stored in the same or a different location. For example, a two-address instruction might add
the contents of two registers together and store the result in one of the registers.
This is common in commercial computers. Here two addresses can be specified in the
instruction. Unlike earlier in one address instruction, the result was stored in the accumulator,
here the result can be stored at different locations rather than just accumulators, but require
more number of bit to represent the address.

Two Address Instruction

Here destination address can also contain an operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

 MOV R1, A R1 = M[A]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

Three Address Instructions

These instructions specify three operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of all three operands, and the result may
be stored in the same or a different location. For example, a three-address instruction might
multiply the contents of two registers together and add the contents of a third register, storing
the result in a fourth register. This has three address fields to specify a register or a memory
location. Programs created are much short in size but number of bits per instruction increases.
These instructions make the creation of the program much easier but it does not mean that
program will run much faster because now instructions only contain more information but
each micro-operation (changing the content of the register, loading address in the address bus
etc.) will be performed in one cycle only.

Three Address Instruction

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

Computer Registers

Registers are a type of computer memory used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU. The registers used by the CPU are
often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data (such as bit
sequence or individual characters).

The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address of
the next instruction after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer:

Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.
o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the memory
location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the
memory location.
o The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the
processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input data.
Instruction Cycle
Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-
operations. In the above examples, there is one sequence each for the Fetch, Indirect,
Execute and Interrupt Cycles.

The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always
followed by the Fetch Cycle. For both fetch and execute cycles, the next cycle depends on
the state of the system.
We assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC designates
the state of processor in terms of which portion of the cycle it is in:-
00 : Fetch Cycle
01 : Indirect Cycle
10 : Execute Cycle
11 : Interrupt Cycle

At the end of the each cycles, the ICC is set appropriately. The above flowchart of Instruction
Cycle describes the complete sequence of micro-operations, depending only on the
instruction sequence and the interrupt pattern(this is a simplified example). The operation of
the processor is described as the performance of a sequence of micro-operation.
Different Instruction Cycles:

• The Fetch Cycle –

At the beginning of the fetch cycle, the address of the next instruction to be
executed is in the Program Counter(PC).
• Step 1: The address in the program counter is moved to the memory address
register(MAR), as this is the only register which is connected to address lines of
the system bus.

• Step 2: The address in MAR is placed on the address bus, now the control unit
issues a READ command on the control bus, and the result appears on the data
bus and is then copied into the memory buffer register(MBR). Program counter is
incremented by one, to get ready for the next instruction. (These two action can
be performed simultaneously to save time)
• Step 3: The content of the MBR is moved to the instruction register(IR).

• Thus, a simple Fetch Cycle consist of three steps and four micro-operation.
Symbolically, we can write these sequence of events as follows:-
• Here ‘I’ is the instruction length. The notations (t1, t2, t3) represents successive
time units. We assume that a clock is available for timing purposes and it emits
regularly spaced clock pulses. Each clock pulse defines a time unit. Thus, all time
units are of equal duration. Each micro-operation can be performed within the
time of a single time unit.
First time unit: Move the contents of the PC to MAR.
Second time unit: Move contents of memory location specified by MAR to MBR.
Increment content of PC by I.
Third time unit: Move contents of MBR to IR.
Note: Second and third micro-operations both take place during the second time
unit.
• The Indirect Cycles –
Once an instruction is fetched, the next step is to fetch source operands. Source
Operand is being fetched by indirect addressing( it can be fetched by
any addressing mode, here its done by indirect addressing). Register-based
operands need not be fetched. Once the opcode is executed, a similar process may
be needed to store the result in main memory. Following micro-operations takes
place:-

• Step 1: The address field of the instruction is transferred to the MAR. This is used
to fetch the address of the operand.
Step 2: The address field of the IR is updated from the MBR.(So that it now
contains a direct addressing rather than indirect addressing)
Step 3: The IR is now in the state, as if indirect addressing has not been occurred.
Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment
to consider the Interrupt Cycle .
• The Execute Cycle
The other three cycles(Fetch, Indirect and Interrupt) are simple and predictable.
Each of them requires simple, small and fixed sequence of micro-operation. In
each case same micro-operation are repeated each time around.
Execute Cycle is different from them. Like, for a machine with N different
opcodes there are N different sequence of micro-operations that can occur.
Lets consider an add instruction:

• Here, this instruction adds the content of location X to register R. Corresponding

micro-operation will be:-

• We begin with the IR containing the ADD instruction.

Step 1: The address portion of IR is loaded into the MAR.
Step 2: The address field of the IR is updated from the MBR, so the reference
memory location is read.
Step 3: Now, the contents of R and MBR are added by the ALU.
Lets take a complex example :-
• Here, the content of location X is incremented by 1. If the result is 0, the next
instruction will be skipped. Corresponding sequence of micro-operation will be
:-

• Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not)
and action (PC is incremented by 1) can be implemented as one micro-operation.
Note : This test and action micro-operation can be performed during the same
time unit during which the updated value MBR is stored back to memory.

• The Interrupt Cycle:

At the completion of the Execute Cycle, a test is made to determine whether any
enabled interrupt has occurred or not. If an enabled interrupt has occurred then
Interrupt Cycle occurs. The nature of this cycle varies greatly from one machine
to another.
Lets take a sequence of micro-operation:-
 • Step 1: Contents of the PC is transferred to the MBR, so that they can be saved
for return.
Step 2: MAR is loaded with the address at which the contents of the PC are to be
saved.
PC is loaded with the address of the start of the interrupt-processing routine.
Step 3: MBR, containing the old value of PC, is stored in memory.
Note: In step 2, two actions are implemented as one micro-operation. However,
most processor provide multiple types of interrupts, it may take one or more
micro-operation to obtain the save_address and the routine_address before they
are transferred to the MAR and PC respectively.
Uses of Different Instruction Cycles :
Here are some uses of different instruction cycles:

1. Fetch cycle: This cycle retrieves the instruction from memory and loads it into
the processor’s instruction register. The fetch cycle is essential for the processor
to know what instruction it needs to execute.
2. Decode cycle: This cycle decodes the instruction to determine what operation it
represents and what operands it requires. The decode cycle is important for the
processor to understand what it needs to do with the instruction and what data it
needs to retrieve or manipulate.
3. Execute cycle: This cycle performs the actual operation specified by the
instruction, using the operands specified in the instruction or in other registers.
The execute cycle is where the processor performs the actual computation or
manipulation of data.
4. Store cycle: This cycle stores the result of the operation in memory or in a
register. The store cycle is essential for the processor to save the result of the
computation or manipulation for future use.