Microprocessors and

Microcontrollers
Module III – Part I
 Interrupt Structure of 8085
• Interrupt is a signal sent by an external device to the processor,
to request the it to perform a particular task or work.
• The processor will check for interrupts at the last machine cycle of
each instruction.
• If there is any interrupt, it accepts the interrupt and sends the INTA
signal to the peripheral.
• The current value of program counter will be saved to stack and
starting address (vector address) of interrupt service routine (ISR)
will be copied to program counter.
• The processor executes the interrupt service routine (ISR).
• It returns to main program after executing the ISR.
 Types of Interrupts
– Software
• The software interrupts are program instructions.
• The 8085 has eight software interrupts from RST 0 to RST 7
• The vector address for these interrupts can be calculated as
Interrupt number * 8
– Hardware
• An external device initiates the hardware interrupts by applying
an appropriate signal at the interrupt pin of the processor.
• The 8085 has five hardware interrupts
– (1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
 Hardware Interrupts
– TRAP:
• This interrupt is a non‐maskable interrupt. It is unaffected by any mask or
interrupt enable.
• TRAP is a vectored interrupt.
• TRAP has the highest priority.
• TRAP interrupt is both edge and level triggered.
– RST 7.5:
• The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• It is edge sensitive.
• It is a maskable interrupt. It can be disabled by DI instruction.
• Enabled by EI instruction.
 Hardware Interrupts
•RST 6.5 and 5.5:
– The RST 6.5 and RST 5.5 both are level triggered.
– RST 6.5 and RST 5.5 are maskable interrupts. These can be disabled by DI
instruction.
– The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
• INTR:
– INTR is a maskable interrupt. It can be enabled and disabled .
– Non‐ vectored interrupt. After receiving INTA signal, it has to supply the
address of ISR.
– It has lowest priority.
– It is a level sensitive interrupt.
– The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each
instruction.
2. If INTR signal is high, then 8085 completes its current instruction and sends
an interrupt acknowledge signal INTA to the device that interrupted.
3. In response to the acknowledge signal, interrupted device places an RST
instruction on the data bus.
4. On receiving the instruction, the 8085 saves the address of next instruction
on stack and executes received instruction.
5. Then the microprocessor executes the interrupt service routine.
 Priority of Interrupts
TRAP ‐1
RST 7.5 ‐ 2
RST 6.5 ‐ 3
RST 5.5 ‐ 4
INTR ‐5
 Maskable and Non‐Maskable Interrupts
– Maskable Interrupt:
• An Interrupt that can be disabled or ignored by the instructions of CPU is
called as Maskable Interrupt.
• Eg: RST 7.5, RST 6.5, RST 5.5 and INTR are maskable Interrupts.
– Non‐Maskable Interrupt:
• An interrupt that cannot be disabled or ignored by the instructions of
CPU is called as Non‐Maskable Interrupt.
• Eg: TRAP interrupt of 8085
 Vectored and Non‐Vectored Interrupts
– Vectored interrupt
• In vectored interrupts, the processor automatically branches to the
specific address in response to an interrupt.
• Eg: TRAP – 0024H
RST 7.5 - 003CH
RST 6.5 - 0034H
RST 5.5 – 002CH
– Non‐vectored interrupt
• But in non ‐vectored interrupts the interrupted device should give the
address of the interrupt service routine (ISR).
• Eg: INTR
Interrupt control circuit
 Enabling/disabling interrupts
– EI instruction
• Used for setting the Interrupt Enable flip flop.
• System reset or an interrupt disables the interrupt process
– DI instruction
• Used for resetting the Interrupt Enable flip flop.
• To be included in program segments where an inteerupt from outside
cannot be tolerated.
 SIM instruction
– The 8085 provides masking facility for RST 7.5, RST 6.5 and RST 5.5
– The masking or unmasking is done by moving an 8‐bit data to
accumulator and then executing SIM instruction.
 RIM instruction
– The status of pending interrupts can be read using RIM instruction.
– When RIM instruction is executed an 8‐bit data is loaded in
accumulator, which can be interpreted as shown
 I/O interfacing
• Interfacing is the process of connecting devices together such
that they can exchange information.
– Memory mapped I/O
– I/O mapped I/O
 Memory mapped I/O
– With memory mapped I/O there is a single address space for
memory and I/O devices.
– The processor treats the I/O devices just like memory
locations and uses same instructions to access both memory
and I/O devices.
– Single read line and single write line are required on the bus
to access both memory and I/O devices.
Memory mapped I/O
 I/O mapped I/O
– The memory and I/O devices are addressed separately.
– Processor uses different instructions for memory and I/O
devices. (ie, MOV for memory and IN,OUT for I/O)
– Different read and write control signals are used for memory
and I/O devices.
I/O mapped I/O
 I/O mapping
Memory mapped I/O I/O mapped I/O
Large Number of instructions like MOV A, M, MOV M, Only two instructions IN Port, OUT Port
A, LDA, STA etc are used for the data transfer. are used for the data transfer
Data transfer is possible between any register of CPU Data transfer is possible only between
and I/O devices. Accumulator and I/O devices.
Arithmetic and logic operations can be performed with Arithmetic and logic operations cannot
the data of I/O ports using with the instructions like be performed in this scheme.
ORA M, XRA M, ANA M, ADD M, SUB M etc.
Memory mapping of 64 Kbyte is shared between 256 (FF H) I/O devices may be
system memory and I/O ports. interfaced
16-bit address lines are needed. 8-bit address lines are needed.
It takes different T-states depending on the instructions. It takes 10 T-states for its execution
 Address Decoding:
– Address decoding is the way by which microprocessor
decodes an address to select a memory location among the
total available memory locations.
– Two types of address decoding techniques are there.
• Absolute Decoding or Full Decoding
• Partial Decoding or Linear Decoding
 Absolute Decoding or Full Decoding

• The decoding in which all available address lines are used for
decoding to select a location.
• This decoding technique is normally used in large memory
systems.
Absolute Decoding or Full Decoding
 Partial Decoding or Linear Decoding
• The decoding in which all available address lines are not
used for decoding to select a location is called partial
decoding technique.
• In small systems, the hardware for decoding circuit can be
eliminated by using individual high order address lines to
select memory chips. This is the partial decoding technique.
• The cost of the decoding circuit can be reduced with this
technique.
Partial Decoding or Linear Decoding
Programmable Peripheral Interface (PPI) 8255A
– The input/output devices are generally interfaced to the
microprocessor through the input/output port.
– The input/output port is either nonprogrammable or programmable.
– A non-programmable port can either be connected in input mode or
output mode
– INTEL 8212 is an 8-bit non-programmable I/O port.
– A programmable I/O port can be programmed to act either as an input
port or an output port.
– The INTEL 8255A is a programmable port device.
Intel 8212
 Intel 8255A
– The IC 8255 A has three 8-bit ports:
• Port-A
• Port-B
• Port-C
 8255
– The port-C can be used as two
4-bit ports represented as Port
CUpper and Port CLower.
– Port-A (PA7-PA0) and
Port-CUpper (PC7-PC4) together
form Group A.
– Port-B (PB7-PB0) and
Port-CLower (PC3-PC0) form
Group B.
8255
 8255
– After deciding the configuration of 3 ports a control word of the
command has to be given to the 8255.
– An 8-bit control word is formed for this purpose.
– The control register has 6 control lines RD, WR , RESET, A1, A0 and CS
 8255
– The 6 bits AD2-AD7 of 8085 are decoded to provide CS ; the remaining
two bits AD0-AD1 may be used for the selection of control register or
any of the three ports.
– Since the six bits of are decoded for CS , as many as 26 (= 64) PPI (8255)
can be connected to any system.
– For the selection of any port of 8255 AD1 and AD0 bits of the address
data bus are connected to A1 and A0 terminals of 8255.
8255
Operating modes of 8255
 Operating modes of 8255
– MODE 0(Simple input / Output):
• Two 8 bit ports(port A and port B) and two 4 bit ports(port Cupper and port
Clower) are available for I/O operations.
• Any port can be used as an input or output port.
– MODE 1 :(Strobed I/O mode)
• Two groups ‐ group A and group B are available for strobed data transfer.
• Each group contains one 8‐bit data I/O port and one 4 bit control port.
• The 8 bit data port can be either used as input or output port.
• Out of 8 bit port C,PC3‐PC5 are used to generate control signals for port A
and PC0‐PC2 are used to generate control signals for port B. The lines PC6
and PC7 may be used as independent I/O lines.
 Operating modes of 8255
– MODE 2: Strobed bi‐directional I/O mode:
• This mode allows bidirectional data transfer over a single 8‐bit data bus (port
A) using handshake signals.
• 5 bit control port PC3‐PC7 is used for generating/accepting handshaking
signals of port A.
• port B and three lines of port C (PC2‐PC0) may be used in either simple I/O
mode or strobed mode.
Operating modes of 8255

– BIT SET/RESET MODE:

• Any one of the 8‐bits of PORT
C can be Set or Reset
depending upon the select bits
on control word register
 Problem
– Obtain the control word when the ports of 8255A are to be used in
mode 0 with port-A as output port and port B as input port and port C
as output port.
 Program
MVI A, 80 H
– Write an assembly OUT 03 H
language program to LOOP: MVI A, 00 H
generate a square ware OUT 00 H
CALL DELAY
of 1 KHz frequency MVI A, 01 H
using 8255A. The wave OUT 00 H
should be available at CALL DELAY
JMP LOOP
PA0 terminal of Port-A.
DELAY: LXI D, 003FH
LOOP1: DCX D
MOV A, E
ORA D
JNZ LOOP1
RET
 Handshaking signals
– These are dedicated signals to coordinate data transfer between two devices with
different speed. The following are the commonly used handshaking signals:
• STB (Strobe Input) :
• This signal is generated by a peripheral device that it has transmitted a byte of data.
• IBF (Input buffer full) :
• This signal is an acknowledgement by the 8255 to indicate that the input latch has received
the data byte.
• OBF(Output Buffer Full) :
• This is an output signal that goes low when the microprocessor writes data into the output
latch of the 8255.
• ACK (Acknowledge) :
• This is an input signal from a peripheral that must output a low when the peripheral
receives the data from the 8255 ports.
 Interfacing LED with 8085
– LEDs are interfaced with 8085 using 8255 PPI.
– address lines, data lines and control lines RD and WR are used for interfacing.
– LEDs are connected to any one of the port by configuring the port in simple
I/O mode.
– LEDs are connected to the ground through current limiting resistors.
– When logic 1 is sent to any pin of Port A, the LED will conduct the current and
it will glow.
– When logic 0 is sent to any pin of Port A, then the LEDs will be off.
Interfacing LED with 8085
 Program to blink LEDs continuously
– In order to configure the 8255 with Port A as output port, the control word to be
written in Control Word Register should be 80H.

MVI A, 80H DELAY: MVI C, FFH

OUT 03H REP: DCR C
BACK: MVI A, FF JNZ REP
OUT 00H RET
CALL DELAY
MVI A, 00H
OUT 00H
CALL DELAY
JMP BACK
 Introduction to Embedded Systems
– An embedded system is an electronic system, which includes a single
microcomputer (Microcontroller) like the 8051 or ARM.
– It is configured to perform a specific dedicated application.
– Software is programmed into the on-chip ROM of the single chip computer.
This software is not accessible to the user and software solves only a limited
range of problems.
– Here the microcomputer is embedded or hidden inside the system.
– Every embedded microcomputer system accepts inputs, performs
computations, generates outputs and runs in real time.
 Features of an Embedded System
– Dedicated to specific tasks.
– Supported by a wide array of processors and processor architectures
– Have real‐time constraints.
– Usually a real‐time operating system (RTOS) is used.
– Have severe power constraints.
– Must be able to operate under extreme environmental conditions.
– Utilizes fewer system resources than desktop systems.
– All the object code is usually stored in ROM.
– Have dedicated debugging circuitry.
– Have software upgradation capability.
 Characteristics of an Embedded System
– The important characteristics of an embedded system are
– Speed (bytes/sec) : Should be high
– Power (watts) : Low power dissipation
– Size and weight : As far as possible small size and low weight
– Accuracy (% error) : Must be very accurate
– Adaptability : High adaptability and accessibility.
– Reliability : Must be reliable over a long period of time.
 Recent trends in Embedded systems
– Processor speed and Power
– The embedded systems are nowadays designed with 16, 32 bit processors
which can work in real time environment.
– These processors are able to perform high speed signal processing activities
which resulted in the development of high definition communication
devices like 4G, 5G mobiles.
– The recent developments in VLSI technology has paved the way for low
power battery operated devices which are very handy and have high
longevity.
– Also , the present day embedded systems are provided with higher memory
capabilities, so that most of them are based on tiny operating systems like
android.
 Recent trends in Embedded systems
– Communication interfaces
– Most of the present day embedded systems are aimed at internet
based applications.
– The communication interfaces like Ethernet, USB, wireless LAN
etc. have become very common resources in almost all the
embedded systems.
– The developments in memory technologies also helped in porting
the TCP/IP protocol stack and the HTTP server software on to the
embedded systems. Such embedded systems can provide a link
between any two devices anywhere in the globe
 Recent trends in Embedded systems
– Operating systems :
– With recent software developments ,there is a considerable growth
in the availability of operating systems for embedded systems.
– Many new operating systems are developed which can be used in
real time applications.
– There are both commercial RTOSes like Vx Works , QNX,WIN‐CE
and open source RTOSes like RTLINUX etc.
– The Android OS in mobiles has revolutionized the embedded
industry
 Recent trends in Embedded systems
– Programming Languages :
– Languages like C++, Java etc. are now widely used in embedded
application programming. For example by having the Java virtual
machine in a mobile phone, one can download Java applets from a
server which can be executed on your mobile.
– Nowadays we also find devices like ASICs and FPGAs in the
embedded system market. These hardware devices are popular as
programmable devices and reconfigurable devices.
 Challenges in Embedded Systems
– Amount and type of hardware needed.
– Optimizing various hardware elements for a particular design.
– Taking into account the design metrics
– Design metrics examples – power dissipation, physical size, number of
gates, prototype development and manufacturing costs.
– Optimizing the Power Dissipation.
– Clock Rate Reduction and Operating Voltage Reduction
– Disable use of certain structural units of the processor to reduce power
dissipation the processor to reduce power dissipation.
– Control of power requirement, for example, by screen auto‐brightness
control.
 Challenges in Embedded Systems
– Process Deadlines
– Meeting the deadline of all processes in the system while keeping the memory, power
dissipation, processor clock rate and cost at minimum is a challenge.
– Flexibility and Upgradeability
– Ability to offer the different versions of a product for marketing and offering the
product in advanced versions later on.
– Reliability
– Designing reliable product by appropriate design and thorough testing, verification and
validation is a challenge.
– Testing, Verification and Validation
– Testing – to find errors and to validate that the implemented software is as per the
specifications and requirements to get reliable product.
 Real‐time embedded systems
– An embedded system which gives the required output in a specified
time or which strictly follows the time dead lines for completion of a
task is known as a real time system. i.e a Real Time system , in addition
to functional correctness, also satisfies the time constraints .
– There are two types of Real time systems.(i) Soft real time system and
(ii) Hard real time system.
 Soft Real‐Time system
– A real time system in which the violation of time constraints will cause
only degraded quality, but the system can continue to operate is known
as a soft real time system.
– In soft real‐time systems, the design focus is to offer a guaranteed
bandwidth to each real‐time task and to distribute the resources to the
tasks.
– Eg: microwave oven , washing machine ,TV remote etc.
 Hard Real‐Time system
– A real time system in which ,the violation of time constraints will cause
critical failure and loss of life or property damage or catastrophe is
known as a hard real time system.
– These systems usually interact directly with physical hardware instead
of through a human being.
– Eg: deadline in a missile control embedded system, delayed alarm during a
gas leakage , car airbag control system, delayed response in pacemakers,
failure in RADAR functioning etc.
Application Areas of Embedded Systems
Application Areas of Embedded Systems