NAND Flash Media Management
Algorithms
Erich F. Haratsch
Seagate
Flash Memory Summit 2017
Santa Clara, CA 1
Outline
§ NAND Flash Scaling Trends
§ ECC
§ Hard and Soft Decision Decoding
§ Read Voltage Calibration
§ Redundant Silicon Elements
§ Summary
Flash Memory Summit 2017
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NAND Scaling Trends
512Gb
NAND Die Capacity
512Gb 80b/1KB
ECC for SSD Endurance
64-layer TLC
256Gb 256Gb
48-layer TLC
60b/1KB
128Gb 128Gb
16nm MLC
64Gb 40b/1KB
64Gb
24nm MLC
2011 2014 2016 2017 Year 2D MLC 2D TLC 3D TLC Technology
§ 3D NAND may extend beyond 100 § Required ECC for SSD-grade endurance
layers exceeds 60b/1KB for 2D TLC
§ 3D NAND extends scaling towards 1Tb
die capacity § 3D NAND relies on strong ECC to make
TLC mainstream for SSDs
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NAND Impairments
Impairment Effect Mitigation
Program/Erase Cycling Voltage shift/widening ECC
Read Voltage Calibration
Retention Voltage shift/widening ECC
Read Voltage Calibration
Media Defects Page, block, plane, die Redundant Silicon
failure Elements
§ Presented Flash media management algorithms
can help to mitigate Read Disturb and Intercell
Interference as well
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ECC: BCH Codes
§ Conventional SSD Controllers use BCH Codes
§ BCH codes are algebraic codes, defined by:
• Code word length
• Error correction capability per code word
• For example: 40 bit error correction over 1 KB code
words
§ Many SSD controllers implement BCH codes
with 1 KB code words
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ECC: BCH Codes
§ BCH codes typically support hard-decision
decoding only
§ Error recovery by read retry
§ Individual hard decision decoding attempts
for different read voltages
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Reading from Flash: Hard Decision
Decoding
11 01 00 10
Read reference Read reference Read reference
voltage MSB voltage LSB voltage MSB
§ NAND Flash Memory compares read voltage with read reference voltage to generate
hard decision
§ One reference voltage for LSB page, 2 reference voltages for MSB page
§ Hard decision is used for decoding
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Voltage Distribution Shift and
Widening
§ P/E cycling
increases right tails
of distributions
§ Retention increases
left tails of
distributions
§ Default read
reference voltages
are misplaced as a
result
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Read Retry Algorithm
Read Page
from Flash § Default read reference
voltage optimized for typical
Change read
condition
Decode
Data
reference § Read retry algorithm cycles
voltage
through several individual
read decoding steps
no
Success? § Retry steps use read
reference voltages
yes optimized for program/erase
Pass Data
cycling, retention, read
to Host disturb, etc.
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Low-Density Parity Check (LDPC)
Codes
b1 b2 b3 b4 b5 b6
§ Defined by a sparse (low c1
density) parity check c2
c3
matrix H
§ Are represented with a Bi-Partite Graph:
b1 b2 b3 b4 b5 b6
bi-partite graph bit nodes
§ Support hard and soft
check nodes
decision decoding c1 c2 c3
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Soft Decision Decoding
11 01 00 10
Read reference Read reference Read reference
voltage MSB voltage LSB voltage MSB
§ Multiple read operations with different reference voltages
to generate soft decision
§ LDPC decoder uses soft decision during error recovery
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Hard/Soft LDPC vs. BCH
Hard/soft gain
§ Soft-decision LDPC decoding has significantly
better error correction than BCH decoding
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Soft LDPC Levels
Read voltage placements
for soft LDPC:
Soft LDPC
read voltages
Default read
voltage
§ Sequence of retries with
varying read voltage
settings
§ Computation of soft
information (LLRs) based
on multiple read decisions
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Optimizing LDPC Error Correction
LDPC Matrix and Codec Optimization
Non-optimized LDPC
Partially-optimized LDPC
Fully Optimized LDPC
Optimized LDPC
UBER
-10
uBER
10
-3
10
rBER
RBER
§ LDPC code parameters and decoding algorithm need to
be optimized for good performance at low error rates
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Adaptive Code Rates
§ Beginning of Life: use less ECC to increase overprovisioning
§ End of life: increase ECC to maintain reliability
NAND Page Spare
Conventional Error Correction: ECC
User Data and OP Space
Stores fixed ECC in spare field
NAND Page Spare Adaptive ECC allows
Adaptive ECC (BOL): for more free space
Stores ECC in a portion of User Data and OP Space ECC @ BOL = More OP
spare field and increase OP
and less write
NAND Page Spare amplification
Adaptive ECC (EOL):
Stores ECC in spare field and User Data and OP Space ECC
uses some of the NAND page
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Switching Code Rates
§ Multiple LDPC codes
cover wide RBER range
§ As NAND flash ages,
controller switches to
the next stronger code
Stronger Codes § Read performance
improves, since
stronger LDPC codes
decode data faster
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Read Voltage Calibration
Voltage distributions
before/after cycling:
Default read Optimized
voltage read voltage
§ Optimized read voltages
reduce retry rate and extend
endurance
§ Optimum read voltages shift
as a function of endurance,
retention and read disturb
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Media Failures
Die § Pages, blocks,
planes or the whole
Plane 0 Plane 1 die can fail
Block X Block Y § ECC cannot
Page m Page n
recover data from
such catastrophic
failures
§ Need RAID-like
protection inside
SSD
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RAISETM: Redundant Array of
Independent Silicon Elements
Drive
Die 1 Die 2 Die n
§ RAID-like data protection within the drive
§ Write data across multiple dies with additional
protection
§ Corrects full page, block or die failures when all soft
LDPC steps fail
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SSD Controller: Block Diagram
Data Management ECC Read/Write
LDPC Write path
Encoder NAND
Flash
Flash
Interface
Host LLR devices
Host FTL Generation Read path
Interface
LDPC Decoder
Firmware: Data and Media Management
Controller
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Multi-Level Error Correction
§ Hard-decision LDPC decoding is
RAISE™
on-the-fly error correction method
§ Progressively apply stronger
decoding methods such as soft-
decision LDPC decoding and
signal processing
§ Specialized noise handling
techniques for P/E cycling,
retention, read disturb, etc.
§ Optimize time-to-data
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Conclusion
§ Latest memory geometries demand intelligent
NAND management features
§ 3D NAND will still rely on strong ECC and
advanced NAND management features to
make TLC mainstream for SSD applications
Flash Memory Summit 2017
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Thank You! Questions?
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Flash Memory Summit 2017
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