🎯 1.
Design Specification
✅ Purpose
Define what the system must do.
✅ Key Content
Functional requirements (e.g., “32-bit ALU supporting add, subtract, multiply,
divide”)
Performance goals (e.g., clock frequency, latency, throughput)
Power consumption constraints
Area budget (chip size)
Technology constraints (process node, supply voltages)
Interface standards (AXI, PCIe, etc.)
✅ Deliverable
A requirements document or specification.
🎯 2. Behavioral Description
✅ Purpose
Describe how the system behaves at a high level, without hardware detail.
✅ Activities
Write algorithmic models in C, SystemC, MATLAB, or pseudocode.
Validate functionality through simulation.
Explore architectures (e.g., pipeline depth, parallel units).
✅ Deliverable
A high-level model that demonstrates the behavior meets the spec.
🎯 3. RTL Description (HDL)
✅ Purpose
Create a detailed Register Transfer Level model, describing:
Registers and their updates on clock edges
Combinational logic in-between
✅ Languages
Verilog
VHDL
✅ Key Points
Timing is described cycle by cycle.
Synthesisable (i.e., can be mapped to gates).
✅ Example
verilog
Copy
Edit
always @(posedge clk) begin
if (reset)
q <= 0;
else
q <= d;
end
This models a D flip-flop.
✅ Deliverable
Synthesizable RTL code
Testbenches for simulation
🎯 4. Functional Verification and Testing
✅ Purpose
Verify the RTL behaves correctly before synthesizing it.
✅ Methods
Simulation with testbenches applying inputs and checking outputs
Code coverage analysis
Formal verification (property checking)
✅ Tools
Synopsys VCS
Cadence Incisive
Mentor ModelSim
✅ Iteration
If bugs are found, return to RTL Description and fix them.
🎯 5. Logic Synthesis / Timing Verification
✅ Purpose
Transform RTL into a gate-level netlist using standard cell libraries.
✅ Activities
Mapping flip-flops, gates, and multiplexers to library cells.
Optimize for area, power, timing.
Generate constraints (e.g., clock definitions, false paths).
Perform Static Timing Analysis (STA).
✅ Deliverable
Gate-Level Netlist (.v or .edf)
Reports on area, power, timing
✅ Iteration
If timing constraints aren’t met, adjust RTL or constraints.
🎯 6. Gate-Level Netlist
✅ Purpose
A complete, fully resolved connectivity representation of gates and flip-flops.
✅ Properties
Equivalent to RTL in functionality
Realistic timing delays estimated
Ready for physical implementation
✅ Use
Input to the Place and Route step.
🎯 7. Logical Verification and Testing
✅ Purpose
Confirm the gate-level netlist matches RTL behavior.
✅ Methods
Equivalence checking (formal comparison of RTL and netlist)
Gate-level simulation (often with delays back-annotated)
Regression testing with known vectors
✅ Outcome
Functional correctness and timing validation.
🎯 8. Floor Planning / Automatic Place and Route
✅ Purpose
Physically arrange standard cells and connect them.
✅ Sub-steps
Floor Planning
Allocate area to large blocks (memories, macros).
Define power and clock regions.
Placement
Position all standard cells in the core area.
Clock Tree Synthesis
Create balanced clock distribution to all flip-flops.
Routing
Connect cells with metal layers.
Timing Closure
Re-analyze timing with accurate parasitics and iterate until constraints are met.
✅ Tools
Cadence Innovus
Synopsys IC Compiler
✅ Iteration
If timing fails, may return to logic synthesis or adjust placement.
🎯 9. Physical Layout
✅ Purpose
Generate the final geometry for manufacturing.
✅ Deliverable
GDSII file (graphic database system)
Contains all polygons for masks
✅ Use
Sent to the foundry for mask fabrication.
🎯 10. Layout Verification
✅ Purpose
Verify that the layout is correct and manufacturable.
✅ Checks
DRC (Design Rule Check):
Ensure all foundry spacing/width constraints are met.
LVS (Layout vs. Schematic):
Ensure layout connectivity matches netlist.
Parasitic Extraction:
Compute resistances/capacitances to validate timing.
✅ Iteration
Errors require fixes and re-verification.
🎯 11. Implementation
✅ Purpose
Finalize the design for production.
✅ Activities
Tape-out of the GDSII to the fab.
Mask generation and wafer processing.
✅ Outcome
Chips manufactured, tested, and packaged.
🔁 Feedback Loops
Note the arrows pointing back in the diagram—this is crucial:
Functional Verification failure: back to RTL.
Synthesis timing failure: back to RTL or constraints.
Layout timing failure: back to synthesis or floor planning.
DRC/LVS failure: back to floor planning/physical layout.
Iterative refinement ensures:
✅ Correctness
✅ Timing met
✅ Manufacturability
✨ Summary Table
Step Purpose
Design Specification Define goals and constraints
Behavioral Description Model functionality
RTL Description Hardware description
Functional Verification Confirm RTL correctness
Logic Synthesis RTL to gates
Gate-Level Netlist Standard cell representation
Logical Verification Validate equivalence
Floor Planning & P&R Physical design
Physical Layout GDSII creation
Layout Verification DRC/LVS checks
Implementation Send to fab
