Experiment 1: Write VHDL code for realize all logic gates.

a) AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs
are logic ‘1’.
Truth table Logic diagram
Inputs Output
A B Y A
Y
0 0 0 B
0 1 0
1 0 0 AND2
1 1 1
Y = A AND B
= A.B

VHDL Code for AND Gate:

-- File : [Link]
-- Entity : andgate

-- Description : VHDL code to realize AND gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity andgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end andgate;

architecture Behavioral of andgate is

begin
Y<= A and B ;
end Behavioral;

y
b) OR Gate: A logic gate whose output is logic ‘0’ if and only if all of its inputs are
logic ‘0’.
Truth table Logic diagram
Inputs Output
A 2
A B Y 1 Y
0 0 0 B 3
0 1 1
1 0 1 OR2
1 1 1
Y = A OR B
=A+B
VHDL Code for OR Gate:

-- File : [Link]
-- Entity : orgate

-- University : Vishweswaraia Technological University

Belgaum,Karnataka
-- Simulators : Mentor Graphics Modelsim OR Active HDL
-- Synthesizers : Xilinx ISE
-- Target Device : XC4000 Series

-- Description : VHDL code to realize OR gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity orgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end orgate;

architecture Behavioral of orgate is

begin
Y<= A or B ;
end Behavioral;
500 1000 1500 2000 2500 3000 3500 4000 4500

y
 c) NOT Gate: A logic gate whose input is complement of its input.

Truth table Logic diagram

Input Output
A Y
0 1
1 0 INV

Y = NOT A

VHDL Code for NOT Gate:

-- File : [Link]
-- Entity : notgate

-- Description : VHDL code to realize NOT gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity notgate is
Port( A : in std_logic;
Y : out std_logic
);
end notgate;

architecture Behavioral of notgate is

begin
Y<= not A ;
end Behavioral;
500 1000 1500 2000 2500 3000 3500 4000 4500 ns

y
 d) NAND Gate: A logic gate which gives logic ‘0’ output if and only if all of its
inputs are logic ‘1’
Truth table Logic diagram
Inputs Output
A B Y 2
1
0 0 0 3
0 1 1
1 0 1 NAND2
1 1 1

Y= A NAND B
=(A. B)\

VHDL Code for NAND Gate:

-- File : [Link]
-- Entity : nandgate

-- Description : VHDL code to realize NAND gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity nandgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end nandgate;
architecture Behavioral of nandgate is
begin
Y<= A nand B ;
end Behavioral;
500 1000 1500 2000 2500 3000 3500 4000 4500 ns

y
 e) NOR Gate: A logic gate whose output logic ‘1’ if and only if all of its inputs are
logic ‘0’
Truth table Logic diagram
Inputs Output
A B Y 2
0 0 0 1
0 1 1 3
1 0 1
NOR2
1 1 1

Y= A NOR B
=(A+ B)\

VHDL Code for NOR Gate:

-- File : [Link]
-- Entity : norgate

-- Description : VHDL code to realize NOR gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity norgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end norgate;

architecture Behavioral of norgate is

begin
Y<= A nor B ;
end Behavioral;

y
 f) EX-OR (Exclusive OR): A logic gate whose output is logic ‘0’ when all the inputs
are equal and logic ‘1’ when they are un equal.
Truth table Logic diagram
Inputs Output
A B Y 2
0 0 0 1
0 1 1 3
1 0 1
XOR2
1 1 0
Y= A EX-OR B
= A (+)B
= A.B\ + A\.B

VHDL Code for EX-OR Gate:

-- File : [Link]
-- Entity : xorgate

-- Description : VHDL code to realize EX-OR gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Entity Declarations
entity xorgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end xorgate;

architecture Behavioral of xorgate is

begin
= A xor B ;
end Behavior

200 400 600 800 1000 1200 1400 1600 1800 2000 2200 ns

y
 g) EX-NOR (Exclusive -NOR) gate: A logic gate that prodices a logic ‘1’ only when
the two inputs are equal
Truth table Logic diagram
Inputs Output
A B Y 2
0 0 0 1
0 1 1 3
1 0 1
1 1 0 XNOR2

Y= A XNOR B
= (A (+)B)\
= (A.B)\ + A.B

VHDL Code for EX-NOR Gate:

-- File : [Link]
-- Entity : xnorgate

-- Description : VHDL code to realize EX-NOR gate functionality

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity xnorgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end xnorgate;
architecture Behavioral of xnorgate is
begin
Y<= A xnor B ;
end Behavioral; ns
200 400 600 800 1000 1200 1400 1600 1800 2000 2200

a
b

y
Experiment 2: Write a VHDL program for the following combinational designs.

a) 2 to 4 decoder: A decoder is a digital logic circuit that converts n-bits binary input
code in to M output lines. OR It is a logic circuit that decodes from binary to octal,
decimal, Hexa-decimal or any other code such as 7-segment etc.

EN SEL(1) SEL(0)

INST1 INST2
INV INV

U5
2
3
4
1 D0
NAND3

U6
2
3
4
1 D1
NAND3

Block Diagram of Decoder U7

2
3
4
1 D2
NAND3

U8
2
3
4
1 D3
NAND3

Logic Diagram of 2:4 Decoder

EN Inputs Output
Sel(1) Sel(0) D
1 X X 0
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
Truth table
-- File : [Link]
-- Entity : decoder24

-- Description : 2 to 4 DECODER

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity decoder24 is
generic(
N: INTEGER :=2;
M: INTEGER :=4 );
port (
EN : in STD_LOGIC;
SEL: in STD_LOGIC_VECTOR (N-1 downto 0);
D: out STD_LOGIC_VECTOR (M-1 downto 0) );
end decoder24;
architecture decoder24_arch of decoder24 is
signal aux: INTEGER;
begin
aux<=conv_integer(SEL);
process(EN,aux)
begin
if (EN='1') then
for i in 0 to M-1 loop
if aux=i then
D(i)<='1' ;
else
D(i)<='0' ;
end if;
end loop;
else
for i in 0 to M-1 loop
D(i)<='0' ;
end loop;
end if;

end process;
end decoder24_arch;
 Simulator Waveforms for 2:4 Decoder:
500 10 0 0 15 0 0 2000 2500 ns

EN
SEL 0 1 2 3 0 1 2 3 0 1 2

D 0000 0 0 10 0 10 0 10 0 0 0001 0 0 10 0 10 0 10 0 0 0001 0 0 10 0 10 0

D (3 )

D (2 )

D (1 )

D (0 )
b) 8 to 3 (Encoder without & with priority)

Encoder: A logic circuit that produces coded binary outputs from uncoded inputs.

Priority encoder: Whenever two or more inputs are applied at a time, internal
hardware will check this condition and if the priority is set such that higher numbered
input should be taken into account and remaining are considered as don’t care then
output code will be appear will be “higher numbered input”.

Truth table for 8-input priority encoder

EN DIN (7:0) EOUT

0 XXXXXXXX 0
1 XXXXXXX0 0
1 XXXXXX 01 1
1 XXXXX 011 2
1 XXXX 0 111 3
1 XXX 0 1 111 4
1 XX 0 1 1 111 5
1 X0 1 1 1 111 6
1 0 1 1 1 1 111 7
1 1 1 1 1 1 111 0

Block Diagram of priority encoder

-- File : [Link]
-- Entity : pencoder

-- Description : 8-input priority encoder

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity pencoder is
port (
X: in STD_LOGIC_VECTOR (7 downto 0);
E: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR (2 downto 0);
A: out STD_LOGIC
);
end pencoder;

architecture pencoder_arch of pencoder is

begin
pe: process(x,E)
variable k: integer;
begin
y <= "000";
A <= '0';
if E = '1' then
for j in 0 to 7 loop
if x(j) = '1' then
y <= conv_std_logic_vector(j,3);
A <= '1';
end if;
end loop;
end if;
end process pe;
end pencoder_arch;
Simulator Waveforms for 8-input priority encoder:
300 400 500 600 700 800 900 1000 1100 ns

E
x 05 0A 0F 14 19 1E 23 28 2D 32

x(7)

x(6)

x(5)
x(4)

x(3)

x(2)

x(1)

x(0)
y 2 3 4 5

y(2)
y(1)

y(0)

A
 c) 8 :1 Multiplexer: The multiplexer is a combinational circuit which accepts several data
inputs and allows only one of them AT A TIME to get through to the output.
EN SEL(2) SEL(1) SEL(0)

ENABLE INV1
INV3 INV2

2 U1
3
4 1
5

D0 D0 6
AND5

2 U2

D1 0 EN 3
4 1
5
1 D1 6

D2
AND5
2 U3
2 3

D3 3
4
D2 5
6
4 1

Data D4 O/PData Output 2

3
AND5
U4
2 U9

Inputs 5 Y
8:1
4 1 3

D5 67
D3
5
6
AND5
4
5

6
1 Y
D6 4

2 U5
1 9

D4 3

D7 5 7
6
AND5 8
OR8
2 U6
3
54 1
D5 6
AND5
2 U7
3

SEL0 D6
4
5
6
AND5
1

SEL1 5
2 U8
3
4 1

D7
SEL2 6
AND5

Control Inputs
Block Diagram of 8:1 Mux Logic Diagram

EN CONTROL INPUTS OUTPUT(Y)

SEL(3) SEL(3) SEL(3) (Selected
Inputs)
0 0 0 0 D0
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7
-- File : mux8_1.vhd
-- Entity : mux8_1

-- Description : 8 TO 1 MULTIPLEXOR

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity mux8_1 is
port (
D: in STD_LOGIC_VECTOR (7 downto 0);
EN: in STD_LOGIC;
SEL: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC );
end mux8_1;
architecture mux8_1_arch of mux8_1 is
begin
process(EN,SEL,D)
begin
if(EN='1')then
y<='0';
else
case SEL is
when "000" => y <= D(0);
when "001" => y <= D(1);
when "010" => y <= D(2);
when "011" => y <= D(3);
when "100" => y <= D(4);
when "101" => y <= D(5);
when "110" => y <= D(6);
when others=> y <= D(7);
end case;
end if;
end process;

end mux8_1_arch;
 Simulator Waveforms for 8:1 Multiplexer:

1000 2000 3000 4000 5000 6000 7000 8000 9000 ns

D(7)

D(6)

D(5)

D(4)

D(3)

D(2)

D(1)

D(0)

EN

SEL 0 1 2 3 4 5 6 7

Y
 d) Multiplexer, Demultiplexer, comparator.

Multiplexer: Ref Exp 2(b)

Demultiplexer: Demultiplexer is a combinational circuit that accepts single input and
distributes it several outputs (Selectively distributes it to 1 of N output channels) &
Exhastly reverse of the multiplexer.
EN SEL(2) SEL(1) SEL(0)

ENABLE

0 D0 D0
EN 1 D1 Y

2 D2 D1
3 D3
Data Input O/P 1:8
D2
Demux 4 D4
Y
5 D5 D3
6 D6
7 D7 D4

D5
Data Outputs
SEL0
D6
SEL1
SEL2 D7
Control Input
Block Diagram of 1:8 Demux Logic Diagram

Truth Table
EN CONTROL INPUTS OUTPUTS
SEL(3) SEL(3) SEL(3)
0 X X X 0
1 0 0 0 D0=Y
1 0 0 1 D1=Y
1 0 1 0 D2=Y
1 0 1 1 D3=Y
1 1 0 0 D4=Y
1 1 0 1 D5=Y
1 1 1 0 D6=Y
1 1 1 1 D7=Y
-- File : [Link]
-- Entity : demux

-- Description : 1:8 DEMULTIPLEXER

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity demux8_1 is
port ( Y : in STD_LOGIC;
EN : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR (2 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0) );
end demux8_1;

architecture demux8_1_arch of demux8_1 is

begin
process(EN,SEL,Y)
begin
if(EN='1')then
D<=(others=>'0');
else
case SEL is
when "000" => D(0)<=Y;
when "001" => D(1)<=Y;
when "010" => D(2)<=Y;
when "011" => D(3)<=Y;
when "100" => D(4)<=Y;
when "101" => D(5)<=Y;
when "110" => D(6)<=Y;
when others=> D(7)<=Y;
end case;
end if;
end process;

end demux8_1_arch;
 Simulator Waveforms for 1: Demultiplexer:

500 1000 1500 2000 2500 3000 3500 ns

EN
SEL 0 1 2 3 4 5 6 7

D 00 02 0A 2A A

D(7)
D(6)
D(5)

D(4)

D(3)

D(2)
D(1)
D(0)
Comparator: A circuit that compares two numbers and produces an output
indicating whether they are equal. It may also indicate which number is greater if they
are unequal. Ex: ‘1’ bit comparator

Truth table:
Comparing Outputs
inputs
A B Y=(A>B) Y=(A<B) Y=(A=B)
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

A 2
U1
AB\
3
1 Y(A<B)
INV1
AND2
U3
2

3
1 Y(A=B)
NOR2

U2
2

B 3
1 Y(A>B)
AND2 A\B
INV2
-- File : [Link]
-- Entity : bitcomp

-- Description : SINGLE BIT MAGNITUDE COMPARATOR.

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity bitcomp is
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR(1 DOWNTO 0);
Y: out BOOLEAN
);
end bitcomp;

architecture bitcomp_arch of bitcomp is

begin
process(A,B,sel)
begin
case sel is
when "00" => y <= A=B;
when "01" => y <= A>B;
when "10" => y <= A<B;
when others => y <= FALSE ;
end case;
end process;

end bitcomp_arch;
Simulator Waveforms for SINGLE BIT MAGNITUDE
COMPARATOR:
500 1000 1500 2000 2500 3000 3500 ns

sel 0 1 2 3 0

Y true false true false true false true false tr

 Experiment 3: Write a VHDL code to describe the functions of full adder using
different modeling styles.
A logic circuit for the addition of two one bit numbers is called half adder (sum
and carry are output) and a logic circuit that accepts two one-bit signal and
Carry-in as inputs and produces their sum and carry as outputs is called full adder.

Truth table for Full adder Truth table for Half adder

INPUTS OUTPUTS INPUTS OUTPUTS

A B Cin SUM CARRY
0 0 0 0 0 A B SUM CARRY
0 0 1 1 0 0 0 0 0
0 1 0 1 0 0 1 1 0
0 1 1 0 1
1 0 0 1 0 1 0 1 0
1 0 1 0 1 1 1 0 1
1 1 0 0 1
1 1 1 1 1
U1 U10
A 2
A(+)B(+)C SUM A 2
B 3 1 1 SUM
Cin 4 B 3
A(+)B
XOR3 XOR2
U2
2 U11
1 2
3 1 CARRY
3
AND2
U3 U5 AND2 A.B
2 2
1 3 1 CARRY
3 4

AND2 OR3
U4
2
1 A.B + [Link] + [Link]
3

AND2

Full adder using 2-Half adder

VHDL Code for HALF ADDER

-- File : [Link]
-- Entity : HA
-- Architecture : HA_arch

-- Description : HALF ADDER.

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations

entity HA is
port(
A,B : in STD_LOGIC;
S,CY : out STD_LOGIC
);
end HA;

architecture HA_arch of HA is
begin
S<= A XOR B;
CY<= A AND B;

end HA_arch;
VHDL Code for FULL ADDER

-- STRUCTURAL MODELING-A set of interconnect with different COMPONENT

-- File : [Link]
-- Entity : FA
-- Architecture : FA_arch

-- Description : FULL ADDER.

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Declarations
entity FA is
port(
A,B,Cin : in STD_LOGIC;
SUM,CARRY : out STD_LOGIC
);
end FA;

architecture STRUCTURAL of FA is

signal sum1,cy1,cy2:std_logic;
component HA
port(
A,B : in STD_LOGIC;
S,CY : out STD_LOGIC
);
end component ;
begin
u1: HA port map(A=>A, B=>B, S=>SUM1, CY=>CY1);
u2: HA port map(A=>SUM1, B=>Cin, S=>SUM, CY=>CY2);

CARRY<= cy1 OR cy2;

end STRUCTURAL;
-- DATAFLOW MODELING-A set of concurrent assignment statements.

architecture DATAFLOW of FA is

begin
SUM<= A XOR B XOR Cin;
CARRY<= (A AND B) OR (Cin AND A)OR (Cin AND B);

end DATAFLOW;

-- BEHAVIORAL MODELING-A set of sequential assignment statements according to

-- the behavior of the design. (Process is single concurrent statement, which has
sequential statements.)

architecture BEHAVIOR of FA is

begin
process(A,B,Cin)
begin
SUM<= A XOR B XOR Cin;
CARRY<= (A AND B) OR (Cin AND A)OR (Cin AND B);
end process;

end BEHAVIOR;
 Simulator waveforms of HALF ADDER
1 2 3 4 5 6 7 8 9 us

SUM

CARRY

Simulator waveforms of FULL ADDER

100 200 300 400 500 600 700 800 900 ns

Cin

SUM

CARRY
Experiment 4: Write a model for 32 bit ALU using the schematic diagram
Shown below example

➢ ALU should use the combinational logic to calculate an output based on the four
bit Opcode input.
➢ ALU should pass the result to the out bit when enable line is high and tri-state
when low enable.
➢ ALU should decode the 4-bit op-code according to the given in example below
Opcode ALU operation
1 A+B
2 A–B
3 A Complement
4 A*B
5 A AND B
6 A OR B
7 A NAND B
8 A XOR B

Function table for ALU

Enable Mode Opcode Functional description
0 X XXXX Y<=”Z” (Tri-stated)
1 0 0001 Y<= A + B ;
1 0 0010 Y<= A – B;
1 0 0011 Y <= A(15:0)* B(15:0)* ;
1 1 0100 Y <= NOT A (Complement)
1 1 0101 Y <= A AND B (AND Operation)
1 1 0110 Y <= A OR B (OR Operation)
1 1 0111 Y <= A NAND B (NAND Operation)
1 1 1000 Y <= A XOR B (XOR Operation)
1 X 1001 Y <= Y (ALU is ideal or previous data is
latched for all other higher opcodes.
1 X 1010 “ “
1 X 1011 “ “
1 X 1100 “ “
1 X 1101 “ “
1 X 1110 “ “
1 X 1111 “ “
 ARTHAMETIC LOGIC UNIT (ALU)

ALU is logic circuit which is able to perform different arithmetic and logical
function basically ALU is the heart of central processing unit (CPU).

Cin Cin + 1 (CY)

Data One stage of
i/p 32 Arithmetic
A 32 circuit
B
4 0 32
Opcode [3 :0]
0
2:1
Enabl 32 Mux
32 Y
Conetrol 1
Signals 1 (Data o/p)
One stage of
Logic circuit

Mode

Mode : ‘0’ Arthmatic operation

‘1’ Logic operation

Enable ‘0’ Y <= “ Z “

‘1’ Out put performed

Note: For A*B, A&B lower 16 bit [15:0] can be taken in to consideration.
VHDL Code for 8_bit ALU:
-- File : [Link]
-- Entity : alu

-- Description : 8-bit ALU.

--The IEEE standard 1164 package, declares std_logic, etc.

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.NUMERIC_STD.all;
Entity Declarations
-- NOTE : JUST BY CHANGING THE WIDTH OF INPUT AND OUTPUT
OF (31 DOWNTO O)
-- WILL BECOME 32-BIT ALU

entity Alu is
port( Clk : in Std_Logic;
MODE,EN: in Std_Logic;
A,B : in Std_Logic_Vector(7 downto 0);
OPCODE : in Std_Logic_Vector(3 downto 0);
Y : out Std_Logic_Vector(7 downto 0));
end Alu;

architecture Alu_a of Alu is

signal C_s : Unsigned(7 downto 0);
begin

process (A, B,OPCODE,mode)

variable A_v : Unsigned(7 downto 0);
variable B_v : Unsigned(7 downto 0);
begin
A_v := Unsigned(A);
B_v := Unsigned(B);
if(EN='0')then
C_s<=(others=>'Z');
if(mode='0')then
case OPCODE is
when "0000" => C_s <= A_v + B_v;
when "0001" => C_s <= A_v - B_v;
when "0010" => C_s <= A_v(3 downto 0) * B_v(3 downto 0);
when others => C_s <= (others => '0');
end case;
else
case opcode is
when "0011" => C_s <= not A_v;
 when "0100" => C_s <= not B_v;
when "0101" => C_s <= A_v and B_v;
when "0110" => C_s <= A_v nand B_v;
when "0111" => C_s <= A_v or B_v;
when "1000" => C_s <= A_v nor B_v;
when "1001" => C_s <= A_v xor B_v;
when "1010" => C_s <= A_v xnor B_v;
when others => C_s <= (others => '0');
end case;
end if;
end if;
end process;

process
begin
wait until Clk'event and Clk = '1';
y <= Std_Logic_Vector(C_s);
end process ;
end Alu_a;

Simulator waveforms for 8_bit ALU:

50 100 150 200 250 300 350 ns

Clk

MODE

EN

A 08

B 04

OPCODE 0 1 2 3 4 3 6 A D
4 5 7 8 9 B C

Y UU 04 2 00 F7 FB 00 F 0C F3 0C F3 00
0 F