United International University

Dept. of Computer Science & Engineering (CSE)

CSE1326: Digital Logic Design Laboratory

Name: Avijit Biswas

Section:​ ​ ​ D

Group No:​ ​ ​ 3

Experiment No:​ 7

Experiment Name:

Logic diagram of 4-bit downward counter

Date of Performance: 2 5 0 5 2 0 2 5

Date of Submission: 0 1 0 6 2 0 2 5

​
I thereby certify that this lab report is prepared by me only. I did not copy any part of this from
anybody, and did not let other copy any part of my report.

Avijit
Signature of the Teaching Assistant Signature of the Student
Objective:

●​ To gain a clear understanding of the design principles and operation of ripple counters.​

●​ To implement and examine four distinct types of digital counters.​

●​ To observe the timing characteristics and performance of edge-triggered flip-flops in

●​ To distinguish between up counters and down counters in asynchronous counter

Introduction:

Ripple counters are a type of asynchronous sequential circuit used to count clock pulses. They are
constructed using flip-flops, where each flip-flop’s output serves as the clock input for the next
stage in the sequence. The name "ripple" reflects the way the state changes propagate through the
flip-flops one after another, introducing a slight delay at each stage. Unlike synchronous counters,
which use a common clock signal for all flip-flops, ripple counters experience cumulative
propagation delays, making them less suitable for high-speed applications. Despite this limitation,
their simple design, low cost, and ease of implementation make ripple counters ideal for basic
counting functions such as digital clocks, frequency division, and timer circuits.

Apparatus:

Name Specifications Quantity

IC D Flip-Flop IC(7474 IC) 1

IC JK Flip-Flop IC (7476 IC) 1

Trainer board - 1

Wire 5v -

Logisim Win 2.7.1 -

Table 01: Apparatus table

Experiment Details:

For the upward D flip-flop counter each D flip-flop is configured so that it toggles based on the state
of the previous flip-flop’s output. The implemented ripple counter should follow the function table
shown below-

Clock pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1
2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0

Table 02 : Function table for D Flip-Flop upward counter

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Fig 01: D Flip-Flop positive edge upward counter

Similar to D Flip-flop, the falling edge downward counter should follow the function table
03,Instead of taking Q as the clock pulse for the next flip flop, we are taking its complement Q’
Fig 02: J-k Flip-flop negative edge downward counter.

Discussion:

Gaining hands-on experience with ripple counters is fundamental to understanding sequential logic
design. These counters serve as the basis for numerous digital applications, such as timers,
frequency dividers, and memory address generators. Exploring various flip-flop types, including D
and JK, along with different triggering methods (positive and negative edge), illustrates the
flexibility and timing challenges encountered in digital circuits.

JK flip-flops are especially advantageous for counters due to their toggling ability, while D
flip-flops offer more straightforward state control. However, the ripple effect inherent in
asynchronous counters introduces cumulative delays, which can impact accuracy in time-sensitive
systems. This experiment underscores the balance between circuit simplicity and operational
efficiency, emphasizing the importance of selecting the appropriate counter architecture based on
application requirements.

Conclusion:

In this laboratory exercise, we successfully designed and evaluated four different 3-bit ripple
counters utilizing various flip-flop configurations and edge-triggering schemes. The experiment
deepened our understanding of asynchronous counter operation, timing delays, and the role of
edge-triggered flip-flops. Mastering these core concepts is essential for progressing to more
complex sequential digital system design.