Register

Serial-in Serial-out (SISO) Shift Register

This type of shift register accepts data serially, i.e. one bit at a time, and also output data serially. Data
may be shifted left using shift-left register or shifted right using shift-right register.
Shift-left register - A shift-left register can be built using J-K flip-flops or S-R flip-flops or D flip-flops.
In J-K flip-flop, to input data 1, J=1 and K=0; to input data 0, J=0 and K=1, should be applied. When the
clock pulse is applied, the data will be shifted bit by bit to the left.
In the shift register using D flip-flop, to input data 1, D=1 and to input data 0, D=0 should be applied.
In four bit register, the register can store up to four bits of data. The Q output of the first flip-flop (FF) is
connected to the D input of the second FF, The Q output of the second FF is connected to the D input of
the third FF and so on. The data is outputted from the Q terminal of the last FF.
When serial data is transferred into a register, each new bit is clocked into the first FF at the positive
going edge of each clock pulse. The bit was previously stored by the first FF is transferred to the left
second FF. The bit was stored by the second FF is transferred to the left third FF and so on. The bit was
stored by the last FF is shifted out.
For example, consider that all stages are reset (0) and a steady logical-1 is applied at the serial input line
connected to FF0. The data in each stage after each of the four shift puls es is shown in following table.
The logical-1 input enters into FF0 and then shifts left to FF3 after four shift pulses.

Shift Pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 1 1
4 1 1 1 1

Shift-right register
A shift-right register can be built using J-K flip-flops or S-R flip-flops or D flip-flops. In J-K flip-flop, to
input data 1, J=1 and K=0; to input a 0, J=0 and K=1, should be applied. When the clock pulse is applied,
the data will be shifted bit by bit to the right.
In the shift register using D flip-flop, to input data 1, D=1 and to input data 0, D=1 should be applied.
In four bit register, the register can store up to four bits of data. The Q output of the first flip -flop (FF) is
connected to the D input of the second FF, The Q out put of the second FF is connected to the D input of
the third FF and so on. The data is outputted from the Q terminal of the last FF.
When serial data is transferred into a register, each new bit is clocked into the first FF at the positive
going edge of each clock pulse. The bit was previously stored by the first FF is transferred to the right
second FF. The bit was stored by the second FF is transferred to the right third FF and so on. The bit was
stored by the last FF is shifted out.
For example, consider that all stages are reset (0) and a steady logical-1 is applied at the serial input line
connected to FF0. The data in each stage after each of the four shift pulses is shown in following table.
The logical-1 input enters into FF0 and then shifts right t o FF3 after four shift pulses.

Shift Pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1

Serial-in Parallel-out (SIPO) Shift Register

It consists of one serial input, and outputs are taken from all the flip-flops parallel. In this register, data is
shifted serially but shifted out in parallel. In order to shift the data out in parallel, it is necessary to have
all the data available at the output at the same time. Once the data is stored, each bit appears on its
respective output line and all the bits are available simultaneously, rather than on a bit by bit basis as
with the serial output.

Parallel-in Serial-out (PISO) Shift Register

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and AND & OR
gates for entering data (i.e. writing) to the register. The Shift/Load’ allows the data to be entered in
parallel form into the register and the data to be shifted out serially from terminal Q 4 .
When Shift/Load’ line is HIGH, gates I, 2 and 3 are disabled, but gates 4, 5 and 6 are enabled allowing the
data bits to shift-right from one stage to the next. When Shift/Load’ line is LOW, gates 4, 5 and 6 are
disabled, but gates 1, 2 and 3 are enabled allowing the data input to appear at the D input s of the
respective flip-flops. When a clock pulse is applied, these data bits are shifted to the output Q terminals of
the flip-flops.
Parallel-in Parallel out (PIPO) Shift Register
For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately
following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in - parallel out
shift register constructed by D flip-flops.
The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the
data at the D inputs appear at the corresponding Q outputs simultaneously.
 COUNTER

A counter is a sequential circuit consisting a set of flip-flops connected in a suitable manner to count the
sequence of the input pulses presented to it in digital form. Counters can be broadly classified under 3 -
heads as follows :
 Asynchronous and Synchronous Counters
 Single and Multimode Counter
 Modulus Counter
Asynchronous Counters or Ripple Counter or Serial Counter – In an asynchronous counter, each
flip-flop is triggered by the output from the previous flip-flop which limits its speed of operation. The
settling time in asynchronous counters, is the cumulative sum of the individual settling times of flip -flops.
Synchronous Counters or Parallel Counter – In synchronous counters, the clock pulses is applying
simultaneously to all the flip-flops which leads to the settling time of the counter being equal to the
propagation delay of a single flip-flop.
Single Mode Counters - Single Mode Counters operate in a single mode, i.e. it counts either in the UP
mode or in the DOWN mode.
Multimode Counters - Multimode Counters operate in multiple mode i.e. it counts both in UP and DOWN
mode.
Modulus Counters - Modulus Counters are defined based on the number of states they are capable of
counting. For example, a MOD-10 counter has 10 state.

Q. Difference between Synchronous Counters and Asynchronous Counters.

Asynchronous Counters Synchronous Counters

1. In this type of c ounter FFs are 1. In this type of counter there is no
connected in such a way that the output connection between the output of first FF
of first FF drives the clock for the second and clock input of next FF and so on.
FF, the output of the second the clock of
the third and so on.
2. All the FFs are not clocked 2. All the FFs are clocked simultaneously.
simultaneously.
3. Design and implementation is very 3. Design and implementation becomes
simple even for more number of states. tedious and complex as the number of
states increases.
4. Main drawback of these counters is 4. Since clock is applied to all the FFs
their low speed as the clock is propagated simultaneously the total propagation
through a number of FFs before it reaches delay is equal to the propagation delay of
the last FF. only one FF. Hence they are faster.
Q. What are the uses or applications of counters?
The most typical uses of counters are
1. To count the number of times that a certain event takes place; the occurrence of event to be counted
is represented by the input signal to the counter.
2. To control a fixed sequence of actions in a digital system.
3. To generate timing signals.
4. To generate clocks of different frequencies.

Asynchronous Counters or Ripple Counter

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.
All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are
also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
The MOD of the ripple counter or asynchronous counter is 2 n if n flip-flops are used. For a 4-bit counter,
the range of the count is 0000 to 1111 (2 4 -1). A counter may count up or count down or count up and
down depending on the input control. The count sequence usually repeats itself. When counting up, the
count sequence goes from 0000, 0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc. When counting down
the count sequence goes in the opposite manner: 1111, 1110, ... 0010, 0001, 0000, 1111, 1110, ... etc.
The complement of the count sequence counts in reverse direction. If the uncomplemented output counts
up, the complemented output counts down. If the uncomplemented output counts down, the
complemented output counts up.
There are many ways to implement the ripple counter depending on the characteristics of the flip flops
used and the requirements of the count sequence.
 Clock Trigger: Positive edged or Negative edged
 JK or D flip-flops
 Count Direction: Up, Down, or Up/Down
Asynchronous counters are slower than synchronous counters because of the delay in the transmission of
the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the count change
synchronously with the assertion of the clock. Examples of synchronous counters are the Ring and
Johnson counter.
4-bit Ripple Up-counter using Negative Edge triggered Flip flops

The 4-bit up-counter counts in the order 0,1,2,3,…..15 i.e. 0000,0001,0010…….. ..11111.

Condition Operation

Initially let both the FFs be Q3 Q2 Q1 = 000................initially

in the reset state
 As soon as the first negative clock edge is applied, FF1 will
toggle and Q1 will be equal to 1.
 Q1 is connected to clock input of FF2. Since Q 1 has changed
After 1st negative clock from 0 to 1, it is treated as the positive clock edge by FF2.
edge There is no change in Q2 and Q3 because all FFs are a
negative edge triggered FF.
Q3 Q2 Q1 = 001................After the first clock pulse
 On the arrival of second negative clock edge, FF1 toggles
again and Q1 = 0.
 The change in Q1 acts as a negative clock edge for FF2. So it
After 2nd negative clock will also toggle, and Q2 will be 1. Since Q2 has changed from
edge 0 to 1, it is treated as the positive clock edge by FF3. There is
no change in Q3 because this FF is a negative edge triggered
FF.
Q3 Q2 Q1 = 010.............After the second clock pulse
 On the arrival of 3rd negative clock edge, FF1 toggles again
and Q1 become 1 from 0.
After 3rd negative clock
 Since this is a positive going change, FF2 does not respond to
edge
it and remains inactive. So Q2 does not change and continues
to be equal to 1.
  Since Q2 =1, it is treated as the positive clock edge by FF3.
There is no change in Q3 because this FF is a negative edge
triggered FF.
Q3 Q2 Q1 = 011................After the third clock pulse
 On the arrival of 4th negative clock edge, FF1 toggles again
and Q1 become 0 from 1.
 This negative change in Q1 acts as clock pulse for FF2. Hence
After 4th negative clock it toggles to change Q2 from 1 to 0.
edge  Again this negative change in Q2 acts as clock pulse for FF3.
Hence it toggles to change Q3 from 0 to 1.
Q3 Q2 Q1 = 100..............After the fourth clock pulse
 On the arrival of 5th negative clock edge, FF1 toggles again
and Q1 become 1 from 0.
After 5th negative clock  Q1 is connected to clock input of FF2. Since Q 1 has changed
edge from 0 to 1, it is treated as the positive clock edge by FF2.
There is no change in Q2 and also Q3 .
Q3 Q2 Q1 = 101..............After the fifth clock pulse
 On the arrival of 6th negative clock edge, FF1 toggles again
and Q1 become 0 from 1.
 Q1 is connected to clock input of FF2. Since Q 1 has changed
After 6th negative clock from 1 to 0, it is treated as the negative clock edge by FF2.
edge Hence it toggles to change Q2 from 0 to 1.
 Since Q2 has changed from 0 to 1, it is treated as the positive
clock edge by FF3. There is no change in Q3 .
Q3 Q2 Q1 = 110..............After the sixth clock pulse
 On the arrival of 7th negative clock edge, FF1 toggles again
and Q1 become 1 from 0.
After 7th negative clock  Since Q1 has changed from 0 to 1, it is treated as the positive
edge clock edge by FF2. There is no change in Q2 And also Q3 .
Q3 Q2 Q1 = 111..............After the seventh clock pulse
 On the arrival of 8th negative clock edge, FF1 toggles again
and Q1 become 0 from 1.
 This negative change in Q1 acts as clock pulse for FF2. Hence
After 8th negative clock it toggles to change Q2 from 1 to 0.
edge  Again this negative change in Q2 acts as clock pulse for FF3.
Hence it toggles to change Q3 from 1 to 0.
Q3 Q2 Q1 = 000..............After the eighth clock pulse

Counter Output Decimal

Clock Counter
Q3 Q2 Q1 Output
Initially 0 0 0 0
1s t 0 0 1 1
2nd 0 1 0 2
3rd 0 1 1 3
4th 1 0 0 4
5th 1 0 1 5
6th 1 1 0 6
7th 1 1 1 7
8th 0 0 0 0
3-bit Ripple Down-counter using Negative Edge triggered Flip flops

The 3-bit down-counter counts in the order 0,1,2,3,…..7 i.e. 000,001,010…….. ..111.
For down counting, (Q1 )’ of FF1 is connected to the clock of FF2.

Condition Operation

Initially let both the FFs be Q3 Q2 Q1 = 000................initially

in the reset state
 As soon as the first negative clock edge is applied, FF1 will toggle
and Q1 goes from 0 to 1 and (Q1 )’ goes from 1 to 0.
 This negative going signal at (Q1 )’ is connected to clock input of
FF2, toggles FF2 and therefore, Q2 goes from 0 to 1 and again
After 1st negative clock (Q2 )’ goes from 1 to 0.
edge  This negative going signal at (Q2 )’ is connected to clock input of
FF3, toggles FF3 and therefore, Q3 goes from 0 to 1.

Q3 Q2 Q1 = 111................After the first clock pulse

 On the arrival of second negative clock edge, FF1 toggles again
and Q1 changes from 1 to 0 and (Q1 )’ goes from 0 to 1.
After 2nd negative clock  This positive going signal at (Q1 )’ does not affect FF2 and
edge therefore Q2 remains at 1 and also Q3 =1.
Q3 Q2 Q1 = 110.............After the second clock pulse
 On the arrival of 3rd negative clock edge, FF1 toggles again and
Q1 become 0 from 1 and (Q1 )’ goes from 1 to 0.
 This negative going signal at (Q1 )’ is connected to clock input of
After 3rd negative clock FF2, toggles FF2 and therefore, Q2 goes from 1 to 0 and again
edge (Q2 )’ goes from 0 to 1.
 This positive going signal at (Q2 )’ does not affect FF3 and
therefore Q3 remains at 1.
Q3 Q2 Q1 = 101................After the third clock pulse
 On the arrival of 4th negative clock edge, FF1 toggles again and
Q1 become 0 from 1
After 4th negative clock  This positive going signal at (Q1 )’ does not affect FF2 and
edge therefore Q2 remains at 0 and also Q3 =1.
Q3 Q2 Q1 = 100..............After the fourth clock pulse
 On the arrival of 5th negative clock edge, FF1 toggles again and
Q1 become 1 from 0 and (Q1 )’ goes from 1 to 0.
 This negative going signal at (Q1 )’ is connected to clock input of
After 5th negative clock
FF2, toggles FF2 and therefore, Q2 goes from 0 to 1 and again
edge
(Q2 )’ goes from 1 to 0.
 Again this negative going signal at (Q2 )’ is connected to clock
input of FF3, toggles FF3 and therefore, Q3 goes from 1 to 0.
 Q3 Q2 Q1 = 011..............After the fifth clock pulse
 On the arrival of 6th negative clock edge, FF1 toggles again and
Q1 become 0 from 1.
After 6th negative clock  This positive going signal at (Q1 )’ does not affect FF2 and
edge therefore Q2 remains at 1 and also Q3 =0.
Q3 Q2 Q1 = 010..............After the sixth clock pulse
 On the arrival of 7th negative clock edge, FF1 toggles again and
Q1 become 1 from 0 and (Q1 )’ goes from 1 to 0.
 This negative going signal at (Q1 )’ is connected to clock input of
After 7th negative clock FF2, toggles FF2 and therefore, Q2 goes from 1 to 0 and (Q2 )’ goes
edge from 0 to 1.
 This positive going signal at (Q2 )’ does not affect FF3 and
therefore Q3 remains at 0.
Q3 Q2 Q1 = 001..............After the seventh clock pulse
 On the arrival of 8th negative clock edge, FF1 toggles again and
Q1 become 0 from 1 and (Q1 )’ goes from 0 to 1.
After 8th negative clock  This positive going signal at (Q1 )’ does not affect FF2 and
edge therefore Q2 remains at 0 and also Q3 =0.
Q3 Q2 Q1 = 000..............After the eighth clock pulse

Counter Output Decimal

Clock Counter
Q3 Q2 Q1 Output
Initially 0 0 0 0
1s t 1 1 1 7
2nd 1 1 0 6
3rd 1 0 1 5
4th 1 0 0 4
5th 0 1 1 3
6th 0 1 0 2
7th 0 0 1 1
8th 0 0 0 0

3-bit Ripple (Asynchronous) up/down counter

A 3-bit Asynchronous up/down counter can be obtained by combining the up-counting and down-counting
operations in a single counter using control or mode signal. When mode signal M=1 then counter count up
when mode signal M=0 then counter count down. Now we can obtain the expressions for an up/down
counter by combining the up and down counters using the mode signal. Therefore the design equations for
an up/down counter are :
 J1 = K1 = 1
J2 = K2= (QA .Up) + ((QA )’.Down) = QA M + (QA )’M’
J3 = K3= (QA .QB .Up) + ((QA )’.(QB )’.Down) = QA QB M + (QA )’(QB )’M’

The circuit above is of a simple 4-bit Up/Down Asynchronous counter using JK flip-flops configured to
operate as toggle or T -type flip-flops giving a maximum count of zero (000) to fifteen (111) and back to
zero again. Then the 3-Bit counter advanc es upward in sequence (0,1,2,3,…..7) or downwards in reverse
sequence (7,6,5……1,0).

Binary 4-bit Synchronous Up Counter

In a synchronous counter, the clock signal is applied to all the Flip Flops simultaneously. The 4 bit up -
counter counts in the order 0000, 0001, 0010,….1111, 0000, 00001….
Observing the up-counting sequence, QA changes state for every clock pulse. So, FFA has to be in toggle
mod. Therefore, J=K=1 of FFA. QB changes state whenever QA is 1, i.e. FFB toggles whenever QA is 1. So,
connect QA to J and K of FFB. QC changes state whenever QB =1 and QA =1; that means, FFC toggles
whenever QA QB =1. So, QA QB is connected to J and K of FFC. QD changes state whenever QA =1 and QB =1
and QC =1, i.e. FFD toggles whenever QA QB QC =1. So QA QB QC is connected to J and K of FFD.

After
State of Counter
clock pulse
QA QB QC QD
0 0 0 0 0
1 1 1 1 1
2 1 1 1 0
3 1 1 0 1
4 1 1 0 0
5 1 0 1 1
6 1 0 1 0
7 1 0 0 1
8 1 0 0 0
9 0 1 1 1
10 0 1 1 0
11 0 1 0 1
12 0 1 0 0
13 0 0 1 1
14 0 0 1 0
15 0 0 0 1
16 0 0 0 0
Binary 4-bit Synchronous Down Counter

In a synchronous counter, the clock signal is applied to all the Flip Flops simultaneously. The 4 bit down-
counter counts in the order 0000, 1111, 1110,….0000, 1111….
Observing the down-counting sequence, QA changes state for every clock pulse. So, FFA has to be in
toggle mod. Therefore, J=K=1 of FFA. Q B changes state whenever QA is 0, i.e. (QA )’=1 i.e. FFB toggles
whenever (QA )’=1. So, connect (QA )’ to J and K of FFB.
QC changes state whenever QB =0 and QA =0; i.e. (QA )’=1 and (QB )’=1 that means, FFC toggles whenever
(QA )’(QB )’=1. So, (QA )’(QB )’ is connected to J and K of FFC.
QD changes state whenever QA =0 and QB =0 and QC =0, i.e. (QA )’=1 and (QB )’=1 and (QC )’=1 i.e. FFD
toggles whenever (QA )’(QB )’ (QC )’=1. So (QA )’(QB )’(QC )’ is connected to J and K of FFD.
After clock pulse State of Counter
QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

Binary 4-bit Synchronous Up/Down (Bidirectional) Counter

A 4-bit synchronous up/down counter can be obtained by combining the up-counting and down-counting
operations in a single counter using control or mode signal. When mode signal M=1 then counter count up
when mode signal M=0 then counter count down. Now we can obtain the expressions for an up/down
counter by combining the up and down counters using the mode signal. Therefore the design equations for
an up/down counter are :
J1 = K1 = 1
J2 = K2= (QA .Up) + ((QA )’.Down) = QA M + (QA )’M’
J3 = K3= (QA .QB .Up) + ((QA )’.(QB )’.Down) = QA QB M + (QA )’(QB )’M’
J4 = K4= (QA .QB .QC .Up) + ((QA )’.(QB )’.(QC )’.Down) = QA QB QC M + (QA )’(QB )’(QC )’M’
This 4-bit up/down counter is also called Bidirectional counters because this type of counter can count
in both directions either Up or Down depending on the state of their input control pin.
The circuit above is of a simple 4-bit Up/Down synchronous counter using JK flip-flops configured to
operate as toggle or T -type flip-flops giving a maximum count of zero (0000) to fifteen (1111) and back to
zero again. Then the 4-Bit counter advances upward in sequence (0,1,2,3,4…..15) or downwards in
reverse sequence (15,14,13,12……1,0).