Module 1

1. Draw and explain the functional block diagram of 8051

 8051 is an 8 bit microcontroller

 The architectural features of 8051 are as follows:
o Eight bit CPU with registers A and B
 Has an 8 bit ALU(arithmetic and logical unit) capable of
processing 8 bit of data. It has two math operation registers A and
B
o Sixteen bit program counter (PC)
 Holds the address of the next instruction to be executed.
o Sixteen bit Data pointer (DPTR)

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  Hold the 16bit address of the data, particularly when the data is in
external memory. It consists of 2 eight-bit registers – DPH (data
pointer higher byte) and DPL (data pointer higher byte)
o Eight bit program status word (PSW)
 Also called the flag register. Consist of 5 flags- carry, auxillary
carry, two bits to select the register bank (RS1 and RS0), overflow
and the parity bit
o Eight bit stack pointer (SP)
 Keeps track of the stack memory. It holds the address of the top of
the stack.
o 4KB of internal ROM
 Used to hold the program code. Address starts from 0000H to
0FFFH
o 128 bytes of internal RAM
 Used to temporarily hold data
 RAM consist of 4 identical register banks, 16 bytes of bit
addressable memory and 80 bytes of general scratch pad area
o Ports
 Has 4 ports – Port 0, Port 1, Port 2, and Port 3. Each port is eight
bit wide. Port 0 works as the AD bus during external memory
interfacing. Port 2 is used to send the higher byte of the address
during external memory interfacing. Port3 has multiple functions.
Port1 works as simple I/O port
o Timers
 Has two 16-bit timers – Timer 0 and Timer 1.
 These registers are used for timing and counting function.
o Serial communication
 Has serial data receiver/transmitter.
 The serial communication circuit uses SCON to control data
communication, SBUF to hod the data during serial
communication and PCON registers to control the data rates

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o Interrupts
 Has three internal and 2 external interrupts. Interrupt feature can be
enabled or disabled using interrupt enable (IE). The priority of
interrupts are set using the interrupt priority(IP) register
o Bus control signals
 Used for sending the control signals to peripheral devices
o Oscillator and clock
 The heart of 8051 is the circuitry that generates the clock pulses
by which all internal operations are synchronized . Pins XTAL1
and XTAL2 are provided for connecting a resonant network to
form an oscillator. Clock is generated using a crystal that can
generate oscillation typically in the range of 1MHz to 16MHz

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2. Compare (i) microprocessor and microcontroller (ii) Harvard and Von Neumann architecture
and (iii) RISC and CISC architecture

Sl.
No MICROCONTROLLERS MICROPROCESSORS
.
1 Contains CPU, RAM, ROM, Timer, I/O Ports Only CPU. No RAM, no ROM and no
and other peripherals. I/O Ports.

2 The fixed amount of on-chip ROM, RAM, and Must add RAM, ROM, I/O ports, and
number of I/O ports makes them ideal for many timers externally to make them
applications in which cost and space are critical functional. Makes the system bulkier
and much more expensive
In many applications, the space it takes, the
3 power it consumes, and the price per unit are Have the advantage of versatility on the
much more critical than the computing power amount of RAM, ROM, and I/O ports

Concerned with rapid movement of bits within Concerned with rapid movement of
the chip, few instructions to move data from code and data from external addresses
4 external memory to CPU to the chip, many instructions to move
data from external memory to the CPU

5 Many bit handling instructions Few bit handling instructions

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5
(ii)

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(iii)

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3. List the salient features of 8051

Ø Eight-bit CPU optimized for control applications

Ø Extensive Boolean processing (single-bit logic) capabilities

Ø 64K Program memory address space

Ø 64K Data memory address space

Ø 4K bytes of on chip program memory (ROM)

Ø 128 bytes of on chip data RAM

Ø Thirty two bi-directional and individually addressable I/O lines (P0– P3)

Ø Two sixteen bit Timer/Counters (T0 and T1)

Ø Serial data receiver/transmitter

Ø Two external and three internal interrupt sources

Ø Oscillator and clock circuits

4. Explain the internal RAM organization of 8051 with a neat diagram

8051 has 128bytes of internal which is organized into
 First 32 bytes consists of register banks.
o There are 4 register banks (Bank0, Bank1, Bank2 and Bank 3).
o Each register bank consists of eight registers each.
o The registers are byte addressable.
o The registers can be addressed using the address or register names (R0
through R7).
o Bank0 address starts from 00H(R0 of bank 0) and ends at 07H(R7 of Bank0).
o Bank1 address starts from 08H(R0 of bank 1) and ends at 0FH(R7 of Bank1).
o Bank2 address starts from 10H(R0 of bank 2) and ends at 17H(R7 of Bank2).
o Bank3 address starts from 18H(R0 of bank 3) and ends at 1FH(R7 of Bank3).

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 16 bytes of bit addressable memory
o Address starts from 20H to 2FH
o Each location is bit addressable. Each bit has an address. For example LSB of
memory location 20H is 00H, MSB of memory location is 20H is 07H.
o Thus address LSB of 2FH is 78H and MSB is 7fH
 Remaining 80 bytes – General Scratch pad area
o Address starts from 30H to 7FH. Can be addressed using these addresses
alone.
o Each location is byte addressable.

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5. List and explain the criteria for choosing a microcontroller
 Performance and cost: It must perform the desired functions efficiently at the optimal
cost
 Speed: what is the highest speed that the microcontroller supports?
 Packaging: Does it come with a DIP(dual inline packaging) packaging or QFP(quad flat
packaging). This is important in terms of space, assembling and prototyping of the end
product
 Power consumption: Critical in case of battery operated systems
 Amount of on chip ROM and RAM
 Number of I/O pins and timer on chip
 Easiness of upgrade to higher performance or lower power consumption version
 Cost per unit. This is important in terms of final cost of the product in which a
microcontroller is used.

6. Describe the various pins used in external memory interfacing

32 – 39 & 21 – 28 : 16 Address Lines – for selecting an address in the external memory

32 – 39 : 8 Data Lines – for reading from or writing into the memory

30 : ALE - It is used for demultiplexing data and address lines. Provides the correct timing for a
latch to store the lower address byte.

31: EA - External Access pin (active low).

It is connected to GND if the code stored in an external ROM is to be accessed

It is connected to Vcc if the code stored in the internal ROM is to be accessed.

The external ROM will be accessed whenever the EA pin is grounded or when the PC contains
an address higher than the last address in the internal 4k ROM (0FFFh)

29: PSEN - Program Store Enable pin (active low).

It is the read signal for external ROM. When it is low, it enables the ROM to place a byte of
program code on the data bus.

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16: WR – Write (active low) - used for writing the data into the external RAM

17: RD – Read (active low) - used for reading the data from external RAM

7. Explain the pin configuration of Port 0 with a neat diagram?

Output port

All pins of port 0 will be used as the address/data bus during external memory interfacing. It is
responsible for carrying the lower byte of address and also behaves as the data bus during
external memory interfacing.

By default, all port pins work as output pins. When a data is written to the port register, the data
bit is latched to the D latch in the port circuit. The processor generates ̅̅̅̅̅
𝑊𝑅 signal, when an
instruction moves the data to the port.
̅̅̅̅̅ 𝑠𝑖𝑔𝑛𝑎𝑙 𝑖𝑠 𝑐𝑜𝑛𝑛𝑒𝑐𝑡𝑒𝑑 𝑎𝑠 𝑡ℎ𝑒 𝑎𝑐𝑡𝑖𝑣𝑒 𝑙𝑜𝑤 𝑐𝑙𝑜𝑐𝑘 𝑜𝑓 𝑡ℎ𝑒 𝐷 flip flop, thus enabling the data to
𝑊𝑅

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be latched in the D latch. When the port is working as output , the control signal (CONTROL=0)
i.e the ALE causes the MUX switch connects to 𝑄̅ .

Case 1: If D=0 then Q=0 and 𝑄̅ = 1. When 𝑄̅ = 1 the lower FET(T2) turns on and upper FET
(T1) turns off causing a logic ‘0’ to appear on the port pin.

Case 2: If D=1 then Q=1 and 𝑄̅ = 0. When 𝑄̅ = 0 the lower FET(T2) turns off and since
CONTROL=0, upper FET (T1) turns ON causing a logic ‘1’ to appear on the port pin.

Input Port

TO configure the port as input port first a ‘1’ has to be written to the port latch. This causes D=0,
then Q=0 and 𝑄̅ = 1. This turns off both the FETs causing the pin to float in high impedance
state. The pins are now connected to the input buffer. While reading the ports there are two
possibilities.

1. Reading the input pin

2. Reading the latch

Reading the input pin

When we read the port pins, it activates buffer B2 and brings the data from the pin into the CPU
internal bus.

Reading the latch

When we read the latch, it activates the tristate buffer (B1), bring the data from the Q output of
the latch into the CPU internal bus.

Read modify write

Some of the instructions like INC P2 and DEC P2 will read a latch, modify and rewrite it to the
latch. These instructions read the latch instead of reading the port pin. This happens for those
instructions where the destination operand is a port or a port bit. These instructions are called
read modify write instructions. Read from the latch is used to avoid possible misinterpretation of
the voltage levels at the port pin, when a port bit is driving an external circuit.

Give explanation for Port 1 ,Port 2 and Port 3 using the above reference

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8. Explain the addressing modes of 8051 with example
1) Immediate addressing

In this addressing mode, source operand is a constant. The data is part of the instruction
itself. Data is preceded by # sign

Mnemonic Comment
MOV A, #43H load the immediate data 43H to accumulator
MOV DPTR, #9000H load the immediate data 9000H into DPTR

2) Register Addressing
In this mode the operands are specified using register names. Data can be moved
between accumulator and register (Rn) but movement of data between the registers
(Rn) is not allowed

Mnemonic Comment
MOV A, R0 copy the contents of register R0 to accumulator
MOV R6, A copy the contents of register accumulator to R6

3) Direct addressing

In this mode the operand is specified using the address of the location where the data
resides. This addressing mode can be used to specify both the source and the destination
operand. One of the use of this addressing mode is in instructions associated with
stack operation.

Mnemonic Comment
MOV R0, 40H copy the contents of memory location 40H to register R0
MOV 56H, B copy the contents of memory location 56H to register B
PUSH 0E0H Push the contents of accumulator to stack
POP 00H Pop the contents of stack to memory location 00H

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4) Indirect addressing mode
In this addressing mode a register is used to point to the data. If the data is in the RAM or
SFRs, then R0 and R1 alone can hold the address of the data. The register named is
preceded by @ sign in the instruction. If the data is in 16bit memory location (eg:
external memory) DPTR is used to hold the address

Mnemonic Comment
MOV A, @R0 copy the contents of memory location whose address is in
R0 to accumulator
MOVX @DPTR, A copy the contents of accumulator to the external memory
location whose address is in DPTR

5) Indexed addressing mode

Used to access data elements from a look up table in the program code space of 8051.
Done using indirect addressing and the A register in conjunction with the DPTR or the
PC

Mnemonic Operation Comment

MOVC The number in register A is copy the contents of code memory
A,@A+DPTR added to the DPTR to form location whose address is
the address in ROM where A+DPTR to accumulator
the desired data is found
The data is then fetched
from that address and
placed in the Accumulator

MOVC A,@A+PC The PC is incremented by 1, copy the contents of code memory

before it is added to A to location whose address is A+PC+1
form the final address of the to accumulator
code byte. The data is then
fetched from that address

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 and placed in the
Accumulator

6) Relative Addressing mode

This is a special addressing mode used with certain jump instructions. The relative
address, often referred to as an offset, is an 8-bit signed number, which is automatically
added to the PC to make the address of the next instruction. The 8-bit signed offset value
gives an address range of + 127 to –128 locations.

Mnemonic Comment
JNZ rel Jump on non zero of accumulator to the instruction with
label rel
SJMP rel Short jump to the instruction with label rel

7) Absolute addressing
This addressing mode is used for transfer of control instruction where the next instruction
to be executed is within the 2K memory range. Here the relative address (offset) is 11bit
value

Mnemonic Comment
AJMP addr11 Absolute jump to the memory location whose address is
addr11
ACALL addr11 Absolute call to the subroutine in memory location whose
address is addr11

8) Long addressing
The long addressing mode within the 8051 is used with the instructions LJMP and
LCALL. The address specifies a full 16 bit destination address so that a jump or a call
can be made to a location within a 64KByte code memory space (216 = 64K).

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 Mnemonic Comment
LJMP addr11 Long jump to the memory location whose address is addr16
LCALL addr11 Long call to the subroutine in memory location whose
address is addr16

9) Bit Inherent Addressing

In this addressing mode the operand is inherent part of the opcode. The operand is one bit
and is generally a flag.

Mnemonic Comment
CLR C Clear the contents of the carry flag (CY=0)
SETB TR0 Set the TR0 flag (make TR0=1)

10) Bit direct

In this addressing mode the operand is a bit addressable memory location or flag.

Mnemonic Comment
CLR 87H Clear the contents of the MSB of Port 0 (P0.7=0)
SETB 07H Set the bit addressable memory location 07H

9) Explain the bit configuration of the PSW register

 used to store a number of important bits that are set and cleared by 8051 instructions

 contains the register bank select flags

 P (bit 0) - Parity bit – Set if number of ones in A is even

 - (bit 1) - This bit is intended for the upcoming MCU models

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 OV (bit 2) - Overflow bit. Set if result of arithmetic operation exceeds 255 (decimal) in
case of unsigned operation. In case of signed addition OV is set if there is a carry from bit
6 or from bit 7 but not from both.

 RS1, RS0 (bits 3 and 4) - Register select

RS1 RS0 Register Bank

0 0 Bank 0
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3

11) What is stack? Explain with example PUSH and POP instructions?
Stack is an area of internal RAM used to store and retrieve data quickly. The address of
the top of the stack is stored in an 8 bit register called the Stack Pointer (SP). On power
up SP is loaded with the value 07H. Stack starts from internal RAM location 07H and
grows upward. PUSH and POP instruction deal with stack related operations
PUSH source address
When a PUSH instruction is executed first the stack pointer(SP) is incremented by 1 then
the contents of the source address is copied to stack.

Mnemonic Operation
PUSH 80h SP=SP+1 then the contents of address location 80H is
copied to the address in SP.
For example if SP was 30H before. Then SP will become
31H and the contents of location 80H will be copied to
location 31H

POP dst address

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When a POP is executed first the contents of the last location of the stack (address is
present in SP) will be copied to the destination address and then SP becomes SP-1

Mnemonic Operation
POP 80h Contents of address location in SP is copied to the address
80H and then SP becomes SP-1.
For example if SP was 31H before. Then contents of
location 31H will be copied to location 80H and then SP
will become 30H

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