SECfION 2~7 Memory Unit 63

that the customer fill out the truth table that he or she wishes the ROM to
satisfy. 'T he truth table may be submitted in a special form provided by the
manuJacturer or in a specified forulat on a computer output medium. The
manufacturer makes the corresponding mask for the paths to produce the l's .
•

and 0' s according to the customer's truth table. This procedure is costly because
the vendor charges the customer a special fee for custom masking the particular
ROM. For this reason, mask programming is economical only if a large quantity
of the same ROM configuration is to be ordered.
For small quantities it is more economical to use a second type of ROM
PROM called a ptogrammable read-only memory or PROM. When ordered, PROM units
contain all the fuses intact, giving all l's in the bits of the stored words .. The
fuses in the PROM are blown by application of current pulses through the
output terminals for each address. A blown fuse defines a binary 0 state, and
an intact fuse gives a binary 1 state. This allows users to program PROMs in
their own laboratories to achieve the desired relationship between input ad-
dresses and stored words. Special instruments called P·ROM programmers are
available commercially to facilitate this procedure. In any case, all procedures
for programming ROMs are hardware procedures eVien though the word
flprogramming" is used.
The hardware procedure for programming ROMs or PROMs is irre-
•
versible, and once programmed, the fixed pattern is perIltanent and cannot be
altered . Once a bit pattern has been established, the unit must be discarded
if the bit pattern is to be changed. A third type of ROM available is called erasable
PROM or EPROM. The EPROM can be restructured to the initial value even
though its fuses have been blown previously. When the EPROM is placed
under a special ultraviolet light for a given period of time, the shortwave
radiation discharges the internal gates that serve as fuses. After erasure the 1

EPROM returns to its initial state and can be reprogrammed to a n.e'w set of
words. Certain PROMs can be erased with electrical signals instead of ultravi-
EEPROM olet light. These PROMs are called electrically erasable PROM or EEPROM.

2-1. TI'L 55I come mostly in 14-pin 1e packages. Two pins are reserved for power
supply and the other pins are used for input and output terminals. How
many circuits are included in one such package if it contains the following
type of circuits? (a) Invertersi (b) two-input exclusive-OR gates; (c) three-in-
put OR gates; (d) four-input AND gates; (e) five-input NOR gates; (f) eight-
input NAND' gates; (g) clocked JK flip-flops with asynchronous clear.
2-2. MSI chips perform el'e mentary digital functions such as decoders" multiplex-
ers; registers, and counters. The following are 'fI'L-type integrated circuits
that provide such functions. Find their description in a data book and
compare them with the corresponding component presented in this chapter.
64 CHAPTER TWO Digital Components

a. Ie type 74155 dual 2-to-4-line decode'fs.

b. Ie type 74157 quadruple 2-to-l-line multiplexers.
c. Ie type 74194 4-bit bidirectional shift registe'r with parallel load.
d. Ie type 74163 4-bit binary counter with paraUelload and synchronous
clear.
2-3. Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable
and one 2-to-4-line decoder. Use block diagrams similar to Fig. 2-3.
2..4. Draw the logic diagram of a 2-to-4-line decoder with only NOR gates.
Include an enable input.
2-5,. Modify the decoder of Fig. 2-2 so that the' circuit is enabled when E ::::: 1 and
disabled when E = O. List the modified truth table. •

2-6.. Draw the logic diagram of an eight-input, three-output encoder whose truth
table is given in Table 2-2. What is the output when all the inputs are equal
to O? What is the output when only input Do is equal to O? Establish a
procedure that will distinguish between these two cases.
2-7. Construct a 16-to-l-line multiplexer with two 8-to-l-line multiplexers and
one 2-to-l-line multiplexer. Use block diagrams for the three multiplexers.
2-8. Draw the block diagram of a dual 4-to-l-line multiplexers and explain its
operation by means of a function table.
2-9. Include a two-input AND gate with the register of Fig. 2-6 and connect the
gate output to the clock inputs of all the flip-flops. One input of the AND
gate receives the clock pulses from the clock pulse generator. The other input
of the AND gate provides a parallel load control. Explain the operation of
the modified register.
2-10. What is the purpose of the buffer gate in the clock input of the register of
· 2-7?.
P19.
2-11. Include a synchronous clear capability to the .r egister with parallel load of
Fig. 2-7.
2-12. The content of a 4-bit register is initially 1101. The register is shifted six times
to the right with the serial input being 101101. What is the content of the
register after each shift?
2-13. What is the difference between serial and parallel transfer? Using a shift
register with parallel load, explain how to convert serial input data to parallel
output and parallel input data to serial output.
2..14. A ring counter is a shift register as in Fig. 2-8 with the serial output connected
to the serial input. Starting from an initial state of 1000, list the sequence of
states of the four flip-flops after each shift.
2-15. The 4-bit bidirectional shift register with parallel load shown in Fig. 2-9 is
enclosed within one Ie package.
a. Draw a block diagram of the Ie showing all inputs and outputs. Include
two pins for power supply.
b. Draw a block diagram using two les to produce an 8-bit bidirectional shift
register with parallel load.
2-16. How many flip-flops will be complemented ina lO-bit binary counter to
reach the next count after (a) 1001100111, (b) OD11111111?
 SECTION 2.. 7 M. m ry . ni 65
Show the . O '. C "ans tw · "nfo r ~- ., b~ With paa e load
(. "ga2- 1) oprod eal - · b ry ad seablock
d ' a , for ach 4-bi coute
·...18. hov l OW he 1- '0 ' rwth '1111 adof l g. 2-11 I1b [la ' to
C
op a e a' ivi e~by-N cou . . . t r t at count fro " 000
N-and ba k 00(00). petfi ally I t f r a -VId -by-lOco .r
u mg the cou te 0 Fl - an an ex I A _. ga -
2 19. T e following memory U I · t a ' e pecified b,y ' he umber ,of wo ds' es the
n mberof ' ~ts pe word. How ' yadd ess "e , a d '· nput-ou pu data
lin s are n eded in eac case? (a 2K x 6- (b) 641 x 8; c) 16 x 32'·
(d) 4G x 64.
2=20. Spdfy t: e -U . 'b er of by " tha an be ' tOTed in he ' e ones listed in
rob. 2-19.
Howm ny 28 X 8 de 0 p ovide a memory capacity
of 4096 X 167
2-22. Given a 3 x 8 ROM chi wit an enab e put, show the external conn c-
tion ecessary to construe a 28 x 8 0' w·t f r chips and a deeD e i

2-23. A ., OM chi of4096 x ab" s · a ' two enabl in , u s andop ate from a S-vo t
power upply. How a y pins aT .", 'ded for the integrated c· c ~t pack
age? Draw a bloc dl' a at d label , ' · , ut a out ternlina s in t e
ROM.

1. Hill, F. J.J an G., R. Pete son, Introduction to' Switching Theory and L gical Design, 3rd
ed, New York. John WileYI 981~
2. Mano, M+ M+, Digital Design£ 2nd ed. Englwood Cliffs, i: Prentice Hall., 1991.
3. Rot I C. H., [Link] of LOgIC DesIgn, 3r ed. St. P'a ui, MN· West Publishing,
1985.
4. Sandig I R.~ So, Modern Digital Des£gn . ew Yorik: McGraw-Hill~ 1990.
5. 5hiva, S. G., Introduction to Logic Design. Gle VIew, ll: Scott, Foresman, 1988
6. Wake ly, J~ F., Digltal Design Princlple and Practices. Englewo~d Cliffs, · Prentice
all 990.
I

7 War " 5 A.f an I . H. Hals ~ead, Jr., Computa ion S ructutes Ca b 'dg ,MA: MIT
Pres 1 1990.