0ECEN 106-001 - Microprocessor Application 2023

Team Name:

“Team #0110”
Members:
Ben Olson
Cole Hajek
James Chester
Tran Hai Khanh Le
Derek Schawang

Homework Assignment: #3

Due: 02/20/2023
 Homework and Group Meeting #3

Agenda:
●​ Assignment #3
●​ The problems for chapter 2 were split evenly amongst the group members with
roughly 15 problems a piece. The members were expected to work through their
problems on their own before meeting on Friday the 10th. At the meeting,
students went through the homework together and worked on the problems other
members could not figure out. The problems for chapter 3 were then split up
roughly 7 apiece and the team met on Friday the 17th to finish the homework.

Location:
●​ PKI
○​ 1st floor outside of room 146 at a table for both meetings.

Attendance:
●​ Ben Olson -
○​ 10th - Not present, forgot
○​ 17th - Present
●​ James Chester -
○​ 10th - Present
○​ 17th - Present
●​ Tran Hai Khanh Le
○​ 10th - Present
○​ 10th - Present
●​ Derek Schawang -
○​ 10th - Not present family matters
○​ 17th - Present
●​ Cole Hajek -
○​ 10th - Present
○​ 17th - Not present, was sick and let the group know ahead of time. Got his
share of the work done.

Time logged by group:

●​ Friday 2/10/2023 10 am - 11:30 am

●​ Friday 2/17/2023 10 am - 11:30 am

Team Evaluation 2
●​ Ben Olson - 10
●​ James Chester - 10
●​ Tran Hai Khanh Le - 10
●​ Derek Schawang - 10
●​ Cole Hajek - 10
Chapter 2

1.​ AVR is a(n) 8 bit microcontroller

2.​ GPRs are 8 bits wide

3.​ LDI value is 16 bits

4.​ Largest value a GPR can hold is $FF

5.​ Result in $28 in GPR R20

6.​ A, c, e, and g are invalid

7.​ C is invalid

8.​ You will get an invalid register error from the assembler because you can only add
registers

9.​ You will get an invalid register error from the assembler because you can only add
registers

10.​True

11.​AVR data memory consists of GPRs, I/O Registers and SRAM

12.​True

13.​True

14.​False

15.​False

16.​Data Memory

17.​Data memory size:

a.​ 2144 Bytes
b.​ 1120 Bytes
c.​ 352 Bytes
d.​ 2304 Bytes
18.​EEPROM is slow and will persist, and hold its data values, without power while SRAM is
fast but volatile and will lose any stored data without power.

19.​No I/O memory? NO

20.​No data memory? NO.

21.​ 0x0000-0x3FFF

22.​8704 Bytes

23.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $30​ ​ ; Load $30 into R16

LDI R17, $97​ ​ ; Load $97 into R17
STS $105, R16​ ; Store R16 into 0x105
STS $106, R17​ ; Store R17 into 0x106

24.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $55​ ​ ; Load $55 into R16

STS $300, R16​ ; Store R16 into address 0x300
STS $301, R16​ ; Store R16 into address 0x301
STS $302, R16​ ; Store R16 into address 0x302
STS $303, R16​ ; Store R16 into address 0x303
STS $304, R16​ ; Store R16 into address 0x304

25.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $5F​ ​ ; Load $5F into R16

OUT PORTB, R16​ ; Stores R16 into PORTB

26.​True

27.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $11​ ​ ; Loads $11 into R16

STS $100, R16​ ; Stores R16 into address 0x100
STS $101, R16​ ; Stores R16 into address 0x101
 STS $102, R16​ ; Stores R16 into address 0x102
STS $103, R16​ ; Stores R16 into address 0x103
STS $104, R16​ ; Stores R16 into address 0x104
STS $105, R16​ ; Stores R16 into address 0x105
LDS R20, $100​ ; Loads the value of 0x100 into R20
​ LDS R21, $101​ ; Loads the value of 0x101 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $102​ ; Loads the value of 0x102 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $103​ ; Loads the value of 0x103 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $104​ ; Loads the value of 0x104 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $105​ ; Loads the value of 0x105 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21

28.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $11​ ​ ; Loads $11 into R16

STS $100, R16​ ; Stores R16 into 0x100
STS $101, R16​ ; Stores R16 into 0x101
STS $102, R16​ ; Stores R16 into 0x102
STS $103, R16​ ; Stores R16 into 0x103
STS $104, R16​ ; Stores R16 into 0x104
STS $105, R16​ ; Stores R16 into 0x105
LDS R20, $100​ ; Loads the value of 0x100 into R20
​ LDS R21, $101​ ; Loads the value of 0x101 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $102​ ; Loads the value of 0x102 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $103​ ; Loads the value of 0x103 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $104​ ; Loads the value of 0x104 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ LDS R21, $105​ ; Loads the value of 0x105 into R21
​ ADD R20, R21​ ; Adds the registers R20 and R21
​ STS $105, R20​ ; Stores the value of R20 into 0x105

29.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $15​ ​ ; Loads $16 into R16

 LDI R19, $00​ ​ ; Loads $00 into R19
STS $167, R16​ ; Stores the value of R16 into 0x167
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19

30.​.INCLUDE "m328pdef.inc"
.ORG $00

LDI R16, $15​ ​ ; Loads $16 into R16

LDI R19, $00​ ​ ; Loads $00 into R19
STS $167, R16​ ; Stores the value of R16 into 0x167
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
ADD R19, R16​ ; Add R16 to R19
STS $167, R19​ ; Stores the value of R19 into 0x167

31.​.INCLUDE "m328pdef.inc"
.ORG $00

LDS R16, $168​ ; Loads 4168 into R16

COM R16​ ​ ; 1s complements R16
MOV R27, R16​ ; Copies the value of R16 into R27

32.​.INCLUDE "m328pdef.inc"
.ORG $00

LDS R19, $168 ​ ; Loads $168 into R19

OUT PORTC, R19​ ; Loads the value or R19 into PORTC

33.​ 8 bit

34.​ Zero indexed- bit 0 for Carry and bit 5 for Half Carry

35.​ Zero indexed- bit 3 for Overflow and bit 2 for negative

36.​ In the ADD instruction, when is C raised?

-​ When an overflow out of bit D7.
37.​In the ADD instruction, when is H raised?
-​ When an overflow out of bit D3, carry from lower nibble to higher nibble.

38.​What is the status of the C and Z flags after the following code?
-​ 1111 1111 + 0000 0001 = (1) 0000 0000
-​ C = 1 because there is a carry beyond the D7 bit
-​ Z = 1 because the R20 has the value 0 in it after the addition.

39.​ Find the C flag value:

-​ 0101 0100 + 1100 0100 = (1) 0001 1000 ; C=1
-​ 0000 0000 + 1111 1111 = 1111 1111 ; C=0
-​ 1111 1111 + 0000 0101 = (1) 0000 0100 ; C=1

40.​ Write a simple program in which the value 0x55 is added 5 times.

-​ .INCLUDE "m328pdef.inc"
-​ .ORG $00
-​
-​ LDI R16,0x55 ; Load hexadecimal 55 into R16
-​ MOV R0,R16 ; Move contents of R16 to R0
-​ ADD R16,R0 ; Add 55 with 55
-​ ADD R16,R0 ; Add result to 55
-​ ADD R16,R0 ; Add result to 55
-​ ADD R16,R0 ; Add result to 55
-​ ADD R16,R0 ; Add result to 55

41.​ State the value (in hex) used for each of the following data:
-​ MYDAT_1 = 55 (decimal) = 0x37 (HEX)
-​ MYDAT_2 = 98 (decimal) = 0x62 (HEX)
-​ MYDAT_3 = 'G' (ASCII) = 0x47 (HEX)
-​ MYDAT_4 = 0x50 (it is hex)
-​ MYDAT_5= 200 (decimal) = 0xC8 (HEX)
-​ MYDAT_6 = 'A' (ASCII) = 0x41 (HEX)
-​ MYDAT_7 = 0xAA (it is hex)
-​ MYDAT_8 = 255 (decimal) = 0xFF (HEX)
-​ MYDAT_9 = 0B10010000 (binary) = 0x90 (HEX)
-​ MYDAT_10 = 0B01111110 (binary) = 0x7E (HEX)
-​ MYDAT_11 = 10 (decimal) = 0x0A (HEX)
-​ MYDAT_12 =15 (decimal) = 0x0F (HEX)

42.​ State the value (in hex) for each of the following data:
-​ DAT_1 = 22 (decimal) = 0x16 (HEX)
-​ DAT_2 = $56 (it is hex)
-​ DAT_3 = 0b10011001 (binary) = 0x99 (HEX)
 -​ DAT_4 = 32 (decimal) = 0x20 (HEX)
-​ DAT_5 = 0xF6 (it is hex)
-​ DAT_6 = 0B11111011 = 0xFB (HEX)

43.​Show a simple code to (a) load the value $11 into location $60-$65, and (b) add them
together and place the result in R29 as the values are added. Use .EQU to assign the
names TEMP0-TEMP5 to locations $60-$65.
(a)
INCLUDE "m328pdef.inc"
.ORG $00

LDS R18,$11
MOV R0,R18
LDS R0,$11 ; Store the value $11 in location 0x11 in R0.
STS $60, R0 ; Store the value R0 in the location 0x60.
STS $61, R0 ; Store the value R0 in the location 0x61.
STS $62, R0 ; Store the value R0 in the location 0x62.
STS $63, R0 ; Store the value R0 in the location 0x63.
STS $64, R0 ; Store the value R0 in the location 0x64.
STS $65, R0 ; Store the value R0 in the location 0x65.

(b)
LDI R29, 0 ; Hold the sum of all values.
LDI R16, 6 ; Additional counter
REPEAT:
ADD R29, R0 ; R0 is added to R29 and stored in R29
DEC R16 ; Decrement counter
BRNE REPEAT; Branch if Z = 0.
.EQU TEMP0 = 0x60
.EQU TEMP1 = 0x61
.EQU TEMP2 = 0x62
.EQU TEMP3 = 0x63
.EQU TEMP4 = 0x64
.EQU TEMP5 = 0x65
nop

44.​Assembly language is a ___low___(low, high)-level language while C is a ___high____

(low, high)-level language.

45.​Of C and Assembly language, which is more efficient in terms of code generation(i.e.,
the amount of ROM space it uses)?
-​ Assembly language because it uses less memory space compared to C language.
46.​Which program produces the obj file?
-​ Assembler program

47.​ The source file has the extension “asm”. T

48.​ The source code file can be a non-ASCII file. F

49.​ Every source file must have .ORG and .EQU directives. F

50.​ Do the .ORG and .SET directives produce opcodes? Yes

51.​ They are directions for the assembler rather than instructions for the CPU.

52.​The .ORG directive appears in the “.1st” file. T

53.​ .hex

54.​ .eep, .hex, .obj

55.​0000

56.​The microcontroller looks for the instruction held at address x0000

57.​Find the number of bytes each instruction takes

a.​ 2-byte
b.​ 2-byte
c.​ 2-byte
d.​ 2-byte
e.​ 2-byte
f.​ 2-byte
g.​ 2-byte
h.​ 4-byte
 58.​

59.​ Find the address of the last location

a.​ 03FFF
b.​ 00FFF
c.​ 07FFF
d.​ 1FFF
e.​ 0FFFF
60.​0x0000 low, 0x3FFF high
61.​ 64K
62.​ 2K
63.​ Find the on-chip ROM size in K
a.​ 16K
b.​ 32K
c.​ 64K
d.​ 128K
e.​ 256K
f.​ 1024k
g.​ 8K
 h.​ 1K
64.​ Find the on-chip ROM size in K
a.​ 2k
b.​ 4K
c.​ 1024k
d.​ 2048k
e.​ 4096K
f.​ 8192K
g.​ 24K
h.​ 768K
65.​ 16-bits
66.​ 16-bits

67.​ In the LDI instruction the “K” can only be within the hex range of 00-FF and 255 decimal
is $FF. Since LDI is a 16-bit instruction, only 8 bits are available for storing the max value
of 1111 1111 in binary.
68.​ ADD
69.​ 4 byte (32 bit) There are 16 bits for the opcode and There are 16 bits available for the
locations allowing it to be able to address the entire data memory

70.​ 4 byte (32 bit) There are 16 bits for the opcode and There are 16 bits available for the
locations allowing it to be able to address the entire data memory much like the STS
instruction

71.​Out of the 32 bits required for the instruction, only 10 are used for the operand that
leaves 22 bits for the address giving it the ability to access 4M of memory

72.​RISC - Reduced Instruction Set Computer

​ CISC - Complex Instruction Set Computer

73.​CISC

74.​RISC

75.​RISC

76.​CISC

77.​False
CHAPTER 3

1. 255 iterations

2. The instruction right after the branch instruction.

3. In calculating the target address for a branch, a displacement is added to the contents of the
register PC (program counter).

4. Relative Jump and is a 2-byte instruction.

5. 4-byte

6. RJMP is a smaller instruction and takes less time to execute

7. The target of a BRNE can be anywhere in the 4M word address space F

8. All AVR branch instructions can branch to anywhere in the 4M word address space F

9. 2-byte instruction: BREQ, BRSH, RJMP

10. Dissect the RJMP instruction, indicating how many bits are used for the operand and the
opcode and indicate how far it can branch.
-​ 16 bits used for the operand
-​ 16 bits used for the opcode
-​ RJMP instruction jumps within -2048 to +2047 words of memory relative to the address
of the current PC; the range of 000-$FFF.
-​ PC = PC + operand - 1100 kkkk kkkk kkkk

11. All conditional branches are 2-byte instructions. F

12. Show code for a nested loop to perform an action 1,000 times.
​ ​ LDI R16, 50​ ​ ; R16 = 50
BACK:​ LDI R17, 20​ ​ ; R17 = 20
HERE:​​ DEC R17​ ​ ​ ; R17 = R17 - 1
​ ​ BRNE HERE​​ ​ ; Branch to HERE if R17 is not equal 0
​ ​ DEC R16​ ​ ​ ; R16 = R16 - 1​ ​ ​
​ ​ BRNE BACK​​ ​ ; Branch to BACK if R16 is not equal 0
13. Show code for a nested loop to perform an action 100,000 times.
LDI R16, 1000​ ​ ; R16 = 1000
BACK:​ LDI R17, 100​ ​ ; R17 = 100
HERE:​​ DEC R17​ ​ ​ ; R17 = R17 - 1
​ ​ BRNE HERE​​ ​ ; Branch to HERE if R17 is not equal 0
​ ​ DEC R16​ ​ ​ ; R16 = R16 - 1​ ​ ​
​ ​ BRNE BACK​​ ​ ; Branch to BACK if R16 is not equal 0

14. 20000 times loop is performed

15. The target address of a BRNE is backward if the relative address of the opcode is negative

16. The target address of a BRNE is forward if the relative address of the opcode is positive

17. CALL is a(n) 4-byte instruction.

18. RCALL is a(n) 2-byte instruction.

19. The RCALL target address can be anywhere in the 4M (word) address space. - False

20. The CALL target address can be anywhere in the 4M address space. - True

21. When CALL is executed, how many locations of the stack are used? 2 locations of the
stack are used.

22. When RCALL is executed, how many locations of the stack are used? 2 locations of the
stack are used.

23. Upon reset, the SP points to location- 0x0000

24. Describe the action associated with the RET instruction.- The address below the CALL
instruction gets loaded into the program counter and is executed.

25. Give the size of the stack in AVR. 2K bytes

26. In AVR, which address is pushed into the stack when a call instruction is executed?
-​ The address of current instruction.

27. 800kHz

28. 50 ns

29. 100 ns
30. 62.5 ns

31. False

32. 200*(100*(1+1+2)+1+2)=80600 cycles * 125ns = 10.075ms

33. 200*(100*(1+1+1+2)+1+2)=100600 cycles * 125ns = 12.575ms

34. 200*(100*(1+1+2)+1+2)=200600 cycles * 250ns=50.15ms

35. 200*(1+1+1+100*(1+2)+1+2)=61200 cycles * 100ns=6.12ms