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UNIT-2 - Central Processing Unit - B.C.a Study

The document discusses the organization of general registers within a CPU, detailing how data flows between registers and the ALU using multiplexers. It provides an example of performing an operation using binary selection variables to manipulate the contents of the registers. Additionally, it includes a table of operation selection codes and their corresponding operations.

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61 views2 pages

UNIT-2 - Central Processing Unit - B.C.a Study

The document discusses the organization of general registers within a CPU, detailing how data flows between registers and the ALU using multiplexers. It provides an example of performing an operation using binary selection variables to manipulate the contents of the registers. Additionally, it includes a table of operation selection codes and their corresponding operations.

Uploaded by

ak69403910
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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16/08/2024, 15:57 UNIT-2: Central processing unit – B.C.

A study

B.C.A study

UNIT-2: Central processing unit

General register organisation

Generally CPU has seven general registers. Register organization show how registers are selected and how
data flow between register and ALU. A decoder is used to select a particular register.The output of each
register is connected to two multiplexers to form the two buses A and B. The selection lines in each
multiplexer select the input data for the particular bus. The A and B buses form the two inputs of an ALU.The
operation select lines decide the micro operation to be performed by ALU. The result of the micro operation is
available at the output bus. The output bus connected to the inputs of all registers, thus by selecting a
destination register it is possible to store the result in it.

A bus organization for seven CPU register

EXAMPLE:• To perform the operation R3 = R1+R2 We have to provide following binary selection
variable to the select inputs.
1. SEL A : 001 -To place the contents of R1 into bus A.

2. SEL B : 010 – to place the contents of R2 into bus B 3. SEL OPR : 10010 – to perform the arithmetic
addition A+B 4. SEL REG or SEL D: 011 – to place the result available on output bus in R3.

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16/08/2024, 15:57 UNIT-2: Central processing unit – B.C.A study

Register and multiplexer input selection code

Binary code SELA SELB SELD or SELREG


000 Input Input —
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

Operation with symbol

Operation selection code Operation symbol


0000 Transfer A TSFA
0001 Increment A INC A
0010 A+B ADD
0011 A-B SUB
0100 Decrement A DEC
0101 A AND B AND
0110 A OR B OR
0111 A XOR B XOR
1000 Complement A COMA
1001 Shift right A SHR
1010 Shift left A SHL

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