ASIC Design Flow Tutorial
Lab 2a: Logic Synthesis. Design Compiler
A. Laboratory tasks
Introduction
Using Design Compiler, it is possible to:
• Produce fast, area-efficient ASIC designs by employing user-specified or standard-cell
libraries
• Translate designs from one technology to another
• Explore design tradeoffs involving design constraints such as timing, area, and power under
various loading, temperature, and voltage conditions
• Synthesize and optimize finite state machines
• Integrate netlist inputs and netlist or schematic outputs into third-party environments while
still supporting delay information and place and route constraints
• Create and partition hierarchical schematics automatically.
Basic Synthesis Flow
Develop HDL files
Libraries objects
link_library Specify libraries
target_library
symbol_library
analyze
synthetic_library Read design elaborate
read_file
Design optimization Define design environment Design rule constraints
constraints set_max_transition
create_clock set_max_fanout
set_clock_latency Set design constraints set_max_capacitance
set_propagated_clock
set_clock_uncertaintly
set_clock_transition Optimize the design compile
set_input_delay
set_output_delay check design
set_max_area Analyze and resolve design problems report_area
report_constraint
report_timing
write_file
Save the design database
Fig.1.Basic synthesis flow
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Department of Electronics
Developed by: The-Hung Pham
Design Compiler input and output files
Design Compiler
input and output files
Design Digital Standard Design Reports and Design
source code Cell Libraries constrains logs database
.v (verilog) .rpt(report) Synopsys internal
.db .sdc database format
.vhd(VHDL) .log(log)
Note: source /home/share/Env/synopsys_setup.env to open all tools.
1. Start Design Compiler graphical user interface (GUI) from the
~/TH_TKVM_CLC/Digital_Synopsys/syn directory. To start it use the following command:
% dc_shell
dc_shell> start_gui
This opens the Design Compiler top-level GUI window (Design Vision). (Fig. 1)
Fig.1. Design Compiler Top-level GUI window
Faculty of Electronics and Telecommunications
Department of Electronics
Developed by: The-Hung Pham
2. Put your cursor in the terminal to type commands (Fig. 2).
Fig.2. Application setup window
3. Set up the initial design:
dc_shell> set top_module johnson
dc_shell> set_svf $top_module.svf
dc_shell> define_design_lib work -path ./work
4. Define libraries for the process of synthesis:
dc_shell> lappend search_path ../Lib/db
dc_shell> lappend search_path ../cons
dc_shell> lappend search_path ../RTL
dc_shell> set LIB "saed32rvt_tt1p05v25c.db"
dc_shell> set target_library [list $LIB]
dc_shell> set link_library [list * $LIB]
5. Read and compile the syntax of Verilog files that are from RTL coding:
dc_shell> set file_format verilog
dc_shell> analyze -format $file_format {johnson.v}
dc_shell> elaborate -lib work johnson
dc_shell> current_design $top_module
6. Link Verilog files and Libs for checking pre-synthesis:
dc_shell> link
dc_shell> check_design
Faculty of Electronics and Telecommunications
Department of Electronics
Developed by: The-Hung Pham
Fig.3. Result for linking and checking pre-synthesis.
7. Read Synopsys Design Constraints (.sdc) and set up timing analysis:
dc_shell> group_path -name INREG -from [all_inputs]
dc_shell> group_path -name REGOUT -to [all_outputs]
dc_shell> group_path -name INOUT -from [all_inputs] -to
[all_outputs]
dc_shell> source -echo dc.sdc
8. Start synthesis by using the following commands:
dc_shell> set case_analysis_with_logic_constants true
dc_shell> set_fix_multiple_port_nets -all
dc_shell> compile_ultra -no_autoungroup
dc_shell> set_svf -off
9. Analyze reports about timing, area, and power:
dc_shell> report_area -hierarchy
dc_shell> report_timing -max_paths 100 -delay_type min
Faculty of Electronics and Telecommunications
Department of Electronics
Developed by: The-Hung Pham
dc_shell> report_timing -max_paths 100 -delay_type max
dc_shell> report_qor
Faculty of Electronics and Telecommunications
Department of Electronics
Developed by: The-Hung Pham
9.9 Write important output files for the next steps (.v, .ddc, .sdc, …)
dc_shell> set verilogout_equation false
dc_shell> write_file -format verilog -hierarchy -output
./output/design_mapped.v
dc_shell> write_file -format ddc -hierarchy -output
./output/design_mapped.ddc
dc_shell> write_sdc -nosplit ../cons/icc2.sdc
dc_shell> write_sdf ./output/design_mapped.sdf
10. To exit Design Compiler write exit in the command line.
dc_shell> exit
B. Homework
Synthesize 2 designs in the Lab 1, including the combinational circuit and the 8-bit counter circuit.
Faculty of Electronics and Telecommunications
Department of Electronics
Developed by: The-Hung Pham
