ECE1371 Advanced Analog Circuits

Lecture 10

NOISE IN SC CIRCUITS

Richard Schreier
[Link]@[Link]

Trevor Caldwell
[Link]@[Link]

Course Goals

• Deepen Understanding of CMOS analog circuit

design through a top-down study of a modern
analog system
The lectures will focus on Delta-Sigma ADCs, but you
may do your project on another analog system.
• Develop circuit insight through brief peeks at
some nifty little circuits
The circuit world is filled with many little gems that
every competent designer ought to recognize.

ECE1371 10-2
 Date Lecture Ref Homework
2008-01-07 RS 1 Introduction: MOD1 & MOD2 S&T 2-3, A Matlab MOD2
2008-01-14 RS 2 Example Design: Part 1 S&T 9.1, J&M 10 Switch-level sim
2008-01-21 RS 3 Example Design: Part 2 J&M 14, S&T B Q-level sim
2008-01-28 TC 4 Pipeline and SAR ADCs J&M 11,13 Pipeline DNL
2008-02-04 ISSCC – No Lecture
2008-02-11 RS 5 Advanced '6 S&T 4, 6.6, 9.4, B CTMOD2; Proj.
2008-02-18 Reading Week – No Lecture
2008-02-25 RS 6 Comparator and Flash ADC J&M 7
2008-03-03 TC 7 SC Circuits Raz 12, J&M 10
2008-03-10 TC 8 Amplifier Design
2008-03-17 TC 9 Amplifier Design
2008-03-24 TC 10 Noise in SC Circuits S&T C
2008-03-31 RS 11 Switching Regulator
2008-04-07 Project Presentations
2008-04-14 TC 12 Matching & MM-Shaping Project Report

ECE1371 10-3

NLCOTD: Gain Booster CMFB

• Need CMFB for Gain Booster
One option is to use standard CT CMFB (Lecture 9)
Is there an easier way with less circuitry?

VB4
VB4 M11 M9 M10

VB3 M12
VB3
M7 M8

EFF OUT OUT

VB2
M5 M6
IN M1 M2 IN
B2

VB1 VB1
M3 M4 M3 M4

ECE1371 10-4
 Highlights
(i.e. What you will learn today)
1. How to analyze noise in switched-capacitor
circuits

2. Significance of switch noise vs. OTA noise

Power efficient solution
Impact of OTA architecture

3. Design example for '6 modulator

ECE1371 10-5

Review
• Previous analysis of kT/C noise
(ignoring OTA/opamp noise)
Phase 1: kT/C1 noise (on each side)
Phase 2: kT/C1 added to previous noise (on each side)
Total Noise (input referred): 2kT/C1
Differentially: 4kT/C1

ECE1371 10-6
 Review
• SNR
Total noise power: 4kT/C1
Signal power: V2/2
SNR: V2C1/8kT

• SNR (single-ended)
Total noise power: 2kT/C1 (sampling capacitor C1)
Signal power: V2/2 (signal from -V to V)
SNR: V2C1/4kT

ECE1371 10-7

Thermal Noise in OTAs

• Single-Ended Example
Noise current from each transistor is I n2 4 kTJ gm
Assume J 2 / 3

ECE1371 10-8
 Thermal Noise in OTAs
• Single-Ended Example
Thermal noise in single-ended OTA
Assuming paths match, tail current source M5 does
not contribute noise to output
8kT
PSD of noise voltage in M1 (and M2):
3 gm1
8kTgm 3
PSD of noise voltage in M3 (and M4):
3 gm2 1

Total input referred noise from M1 - M4

16kT § gm 3 · 16kT
Sn,eq ¨ 1 ¸ nf
3 gm1 © gm1 ¹ 3 gm1
Noise factor nf depends on architecture

ECE1371 10-9

OTA with capacitive feedback

• Analyze output noise in single-stage OTA
Use capacitive feedback in the amplification /
integration phase of a switched-capacitor circuit

n,eq

ECE1371 10-10
 OTA with capacitive feedback
• Transfer function of closed loop OTA
VOUT G
H ( s)
Vn,eq 1  s / Zo
where the DC Gain and 1st-pole frequency are
1 E gm1
G| 1  C1 / C2 Zo
E CO

Load capacitance CO depends on the type of OTA –

for a single-stage, it is CL+C1C2/(C1+C2), while for a
two-stage, it is the compensation capacitor CC

ECE1371 10-11

OTA with capacitive feedback

• Integrate total noise at output
f
2
³ Sn,eq (f ) H ( j 2S f ) df
2
V OUT
0

16kT Z o 2
nf G
3 gm1 4
4 kT
nf
3 E CO
4 kT
Minimum output noise for E=1 is nf
3CO

Not a function of gm1 since bandwidth is proportional

to gm1 while PSD is inversely proportional to gm1

ECE1371 10-12
 OTA with capacitive feedback
• Graphically…

Noise is effectively filtered by the equivalent brick

wall response with a cut-off frequency of Sfo/2
Total noise at VOUT is the integral of the noise within
the brick wall filter (area is simply Sfo/2 x 1/E2)

ECE1371 10-13

Sampled Thermal Noise

• What happens to noise once it gets sampled?
Total noise power is the same
Noise is aliased – folded back from higher
frequencies to lower frequencies
PSD of the noise increases significantly

1
OUT S
O,S

IN L
n,eq

ECE1371 10-14
 Sampled Thermal Noise
Vo,s Aliased
Noise

Vout

s o

• Same total area, but PSD is larger from 0 to fS/2

G2 Sn,eq 2
VOUT 4 kT 1
SVout (f ) nf
4W fS / 2 fS / 2 3 E CO fS / 2
1 S f3 dB
Low frequency PSD G2 Sn,eq is increased by
2W fS fS
ECE1371 10-15

Sampled Thermal Noise

• 1/f3dB is the settling time of the system, while
1/2fS is the settling period for a two-phase clock
1/ 2 fS

e W
 2  ( N  1)
S f3 dB
! ( N  1)ln2
fS
PSD is increased by at least ( N  1)ln2
If N = 10 bits, PSD is increased by 7.6, or 8.8dB

• This is an inherent disadvantage of sampled-

data compared to continuous-time systems
But noise is reduced by oversampling ratio after
digital filtering
ECE1371 10-16
 Noise in a SC Integrator
• Using the parasitic-insensitive SC integrator

• Two phases to consider

1) Sampling Phase
Includes noise from both I1 switches
2) Integrating Phase
Includes noise from both I2 switches and OTA
ECE1371 10-17

Noise in a SC Integrator
• Phase 1: Sampling
Ron1 ON 1

Ron ON 1
ON

C1
Ron2

Noise PSD from two switches: SRon ( f ) 8kTRON

Time constant of R-C filter: W 2RON C1
PSD of noise voltage across C1
8kTRON
SC 1 ( f )
1  (2S fW ) 2
ECE1371 10-18
 Noise in a SC Integrator
• Phase 1: Sampling
Integrated across entire spectrum, total noise power
in C1 is
8kTRON kT
VC21,sw 1
4W C1
Independent of RON (PSD is proportional to RON,
bandwidth is inversely proportional to RON)
After sampling, charge is trapped in C1

ECE1371 10-19

Noise in a SC Integrator
• Phase 2: Integrating

• Two noise sources - switches and OTA

Noise PSD from two switches: SRon ( f ) 8kTRON
16kT
Noise PSD from OTA: Svn,eq (f ) nf
3 gm1
Noise voltage across C1 charges to —2VRon – Vn,eq
ECE1371 10-20
 Noise in a SC Integrator
• What is the time-constant?
IN 2

Ron ON 1
OUT

C1 m1 L

1/ sC2  RL
Analysis shows that ZIN
1  gm1RL
1
For large RL, assume that ZIN
gm1

Resulting time constant W (2RON  1/ gm1 )C1

ECE1371 10-21

Noise in a SC Integrator
• Total noise power with both switches and OTA
on integrating phase
Svn,eq (f ) SRon (f )
VC21,op VC21,sw 2
4W 4W
16kT nf 8kTRON
3 gm1 4(2RON  1/ gm1 )C1 4(2RON  1/ gm1 )C1
4 kT nf kT x
3C1 (1  x) C1 (1  x)

Introduced extra parameter x 2RON gm1

ECE1371 10-22
 Noise in a SC Integrator
• Total noise power on C1 from both phases
VC21 VC21,op  VC21,sw 1  VC21,sw 2
4 kT nf kT x kT
 
3C1 (1  x) C1 (1  x) C1
kT § 4 nf / 3  1  2 x ·
¨ ¸
C1 © 1 x ¹
Lowest possible noise achieved if x o f
2 2kT
In this case, VC 1
C1
What was assumed to be the total noise was actually
the least possible noise!

ECE1371 10-23

Noise Contributions
• Percentage noise contribution from switches
and OTA (assume nf=1.5)
100
Switch
OTA
80
Noise Fraction (%)

60

40

20

0
0 2 4 6 8 10
x=2RONgm1

ECE1371 10-24
 Noise Contributions
• When gm1 >> 1/RON (x >> 1)…
Switch dominates both bandwidth and noise
Total noise power is minimized

• When gm1 << 1/RON (x << 1)…

OTA dominates both bandwidth and noise
Power-efficient solution
Minimize gm1 (and power) for a given settling
time and noise
kT § 4 ·
gm1 ¨ nf  1  2 x ¸
W VC21 © 3 ¹
Minimized for x=0
ECE1371 10-25

Maximum Noise
• How much larger can the noise get?
Depends on nf… (table excludes cascode noise)

Maximum
Architecture Relative VEFF’s nf +dB
Noise (x=0)
Telescopic/
VEFF,1=VEFF,n/2 1.5 [Link]/C1 1.76
[Link]
Telescopic/
VEFF,1=VEFF,n 2 [Link]/C1 2.63
[Link]
Folded
VEFF,1=VEFF,n/2 2.5 [Link]/C1 3.36
Cascode
Folded
VEFF,1=VEFF,n 4 [Link]/C1 5.01
Cascode
ECE1371 10-26
 Separate Input Capacitors
• Using separate input caps increases noise
Each additional input capacitor adds to the total noise
Separate caps help reduce signal dependent
disturbances in the DAC reference voltages
2

1 2
1
I
O
2 1

2
1a
DAC kT § 4 nf / 3  1  2 x · § C1a ·
VC21 ¨ ¸¨ 1   ... ¸
1
C1 © 1 x ¹© C1 ¹

ECE1371 10-27

Differential vs. Single-Ended

• All previous calculations assumed single-ended
operation
For same settling time, gm1,2 is the same, resulting in
the same total power [0dB]
Differential input signal is twice as large [gain 6dB]
Differential operation has twice as many caps and
therefore twice as much capacitor noise (assume
same size per side – C1 and C2) [lose ~1.2dB for
nf=1.5, x=0… less for larger nf]

• Net Improvement: ~4.8dB

ECE1371 10-28
 Differential vs. Single-Ended
• Single-Ended Noise
kT § 4 nf / 3  1  2 x ·
VC21,se ¨ ¸
C1 © 1 x ¹
• Differential Noise
VC21,diff VC21,op  VC21,sw 1  VC21,sw 2
4 kT nf 2kT x 2kT
 
3C1 (1  x) C1 (1  x) C1
kT § 4 nf / 3  2  4 x ·
¨ ¸
C1 © 1 x ¹
• Relative Noise (for nf=1.5, x=0)
VC21,diff 4 nf / 3  2  4 x 4
VC21,se 4 nf / 3  1  2 x 3
ECE1371 10-29

Noise in an Integrator
• What is the total output-referred noise in an
integrator?
Assume an integrator transfer function
kz 1
H ( z)
1  P (1  k )  (1  P ) z 1
C1 1
where k and P
C2 A
2

1 2
1
I
O
2 1
C1
OUT

ECE1371 10-30
 Noise in an Integrator
• Total output-referred noise PSD
2
SINT (f ) SC 1(f ) H ( z )  SOUT (f )

2 4 kT
where VOUT nf
3 E CO

2 kT § 4 nf / 3  1  2 x ·
and VC 1 ¨ ¸
C1 © 1 x ¹

Since all noise sources are sampled, white PSDs

Vx2
Sx
fS / 2
To find output-referred noise for a given OSR
fS /(2˜OSR )

³
2
ECE1371
VINT SINT (f )df 10-31
0

Noise in a '6 Modulator

• How do we find the total input-referred noise in
a '6 modulator?
1) Find all thermal noise sources
2) Find PSDs of the thermal noise sources
3) Find transfer functions from each noise source to
the output
4) Using the transfer functions, integrate all PSDs
from DC to the signal band edge fS/[Link]
5) Sum the noise powers to determine the total
output thermal noise
6) Input noise = output noise (assuming STF is ~1 in
the signal band)

ECE1371 10-32
 Noise in a '6 Modulator
• Example:
fS = 100MHz, T = 10ns, OSR = 32
SNR = 80dB (13-bit resolution)
Input Signal Power = 0.25V2 (-6dB from 1V2)
Noise Budget: 75% thermal noise
Total input referred thermal noise:
2
VTH 0.75 * 10( 6 SNR ) / 10 (43.4 PV )2

IN OUT

ECE1371 10-33

Noise in a '6 Modulator

1) Find all thermal noise sources

kT § 4 nfA / 3  1  2 xA · kT § 4 nfB / 3  1  2 xB ·
Vni2 1 ¨ ¸ Vni2 2 ¨ ¸
C1A © 1  xA ¹ C1B © 1  xB ¹
2 4 kT 4 kT
Vno 1 nfA 2
Vno nfB
3 E ACOA 2
3 E BCOB
2kT § Cf 2 Cf 3 · 2kT
Vn23 ¨ 1   ¸ (1  2  1)
ECE1371 Cf 1 © Cf 1 Cf 1 ¹ Cf 1 10-34
 Noise in a '6 Modulator
2) Find PSDs of the thermal noise sources
For each of the mean square voltage sources,
Vx2
Sx
fS / 2

3) Find transfer functions from each noise source

to the output
Assume ideal integrators
z 1
H A ( z ) HB ( z )
1  z 1
STF( z ) 1
1
NTF( z ) (1  z 1 )2
1  2H ( z)  H ( z )2
ECE1371 10-35

Noise in a '6 Modulator

3) Find transfer functions from each noise source
to the output
From input of HA(z) to output…
NTFi 1 ( z ) 2H ( z )  H ( z )2 NTF( z )
2H ( z )  H ( z )2
2 z  1  z 2
1  2H ( z)  H ( z)2

From output of HA(z) to output…

NTFo1 ( z ) 2  H ( z ) NTF( z )
2  H ( z)
(1  z 1 )(2  z 1 )
1  2H ( z)  H ( z)2

ECE1371 10-36
 Noise in a '6 Modulator
3) Find transfer functions from each noise source
to the output
From input of HB(z) to output…
NTFi 2 ( z ) H ( z ) NTF( z )
H ( z)
z 1 (1  z 1 )
1  2H ( z)  H ( z )2

From output of HB(z) to output (equal to transfer

function at input of summer to output)…

NTFo 2 ( z ) NTF( z ) (1  z 1 )2

ECE1371 10-37

Noise in a '6 Modulator

3) Find transfer functions from each noise source
to the output
Most significant is NTFi1
20
Signal Band

0
Magnitude (dB)

-20

|NTFi1|
|NTFo1|
-40
|NTFi2|
|NTFo2|
-60 -3 -2 -1
10 10 10
Normalized Frequency
ECE1371 10-38
 Noise in a '6 Modulator
4) Using the transfer functions, integrate all PSDs
from DC to the signal band edge fS/[Link]
Use MATLAB/Maple to solve the integrals…
fS /(2˜OSR )
Vni2 1 2
³
2
N i1 NTFi 1 ( f ) df
fS / 2 0

Vni2 1 ª 5fS 2fS § S ·º

 sin ¨ ¸»
fS / 2 «¬ 2 ˜ OSR S © OSR ¹ ¼
2 fS /(2˜OSR )
Vno 2
³
2
N o1
1
NTFo1 ( f ) df
fS / 2 0

§ S · § S · 9fS § S ·º
2
Vno 1 ª 7 fS 2fS
 sin ¨ ¸ cos ¨ ¸  sin ¨ ¸»
fS / 2 «¬ OSR S © OSR ¹ © OSR ¹ S © OSR ¹ ¼
ECE1371 10-39

Noise in a '6 Modulator

4) Using the transfer functions, integrate all PSDs
from DC to the signal band edge fS/[Link]

2 Vni2 2 ª fS fS § S ·º
N  sin ¨ ¸»
fS / 2 «¬ OSR S
i2
© OSR ¹ ¼

§ S · § S ·
2 2
2 Vno 2  Vn 3 ª 3fS fS
N o2
fS / 2 « OSR  S sin ¨ OSR ¸ cos ¨ OSR ¸
¬ © ¹ © ¹
4fS § S ·º
 sin ¨ ¸»
S © OSR ¹ ¼
(Some simplifications can be made for large OSR)

ECE1371 10-40
 Noise in a '6 Modulator
5) Sum the noise powers to determine the total
output thermal noise
Assume xA = xB = 0.1 and nfA = nfB = 1.5

2 2.9kT 1 2kT S2 2.9kT S 2

V |
TH  
C1A OSR E ACOA 3OSR 3 C1B 3OSR 3
2kT S4 8kT S 4
 
E BCOB 5OSR 5 Cf 1 5OSR5
With an OSR of 32, first term is most significant
(assume EA = EB = 1/3)

2 kT kT kT
VTH | 9.1u 10 2  6.0 u 10 4  2.9 u 10 4 
C1A COA C1B
ECE1371 10-41

Noise in a '6 Modulator

6) Input noise = output noise (assuming STF is ~1
in the signal band)
kT
2
VTH | 9.1u 10 2 (43.4 PV ) 2
C1A
=> C1A = 200fF

Assuming other capacitors are smaller than C1A,

then subsequent terms are insignificant and the
approximation is valid

If lower oversampling ratios are used, other terms

may become more significant in the calculation

ECE1371 10-42
 Noise in a Pipeline ADC
• Similar procedure to '6 modulator, except
transfer functions are much easier to compute

• Differences…
Input refer all noise sources
Gain from each stage to the input is a scalar
Noise from later stages will be more significant since
typical stage gains are as low as 2
Sample-and-Hold adds extra noise which is input
referred with a gain of 1
Entire noise power is added since the signal band is
from 0 to fS/2 (OSR=1)

ECE1371 10-43

Noise in a Pipeline ADC

• Example
If each stage has a gain G1, G2, … GN
2 2 2 2 2
2 2 Vno 1  Vni 2 Vno 2  Vni 3 VnoN
N i V
ni 1    2 2
G12 G12G22 G1 G2  GN2

S/H stage noise will add directly to Vni1

ECE1371 10-44
 NLCOTD: Gain Booster CMFB

ECE1371 10-45

What You Learned Today

1. Noise analysis for switched-capacitor circuits

2. Contributions of both switch noise and OTA

noise
Finding a power efficient solution
Significance of OTA architecture

3. '6 modulator design example

ECE1371 10-46
 Some Project Guidelines
• General:
1) Corners: Do not need to simulate
2) Noise analysis: use calculations to size the
capacitors, but use Cadence to find OTA noise
3) Clock Generator: don’t need to design non-
overlapping clock generator, but buffer the ideal
clocks and take into account the buffer size for
power calculations (if you have other clock phases
– not just I1 and I2 – you should indicate how you
would generate these)
4) Biasing: Ideal voltage source for VDD/VSS and
reference ladder edges; Ideally one current source
from which all currents are derived (at least use
only one current source per circuit block)
ECE1371 10-47

Some Project Guidelines

• Presentation: 15-20 minutes
12 Slides (1 title, 11 content)
Focus on major design issues and circuit blocks
(what you consider the most important design
decisions)

• Report
We should be able to replicate your circuit with the
information provided in the report
Give transistor sizes, preferably annotated on figures
Try to avoid Cadence schematics (if you use them,
make them more readable without all the unnecessary
annotations)
ECE1371 10-48