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VIETNAM NATIONAL UNIVERSITY HANOI (VNU)
VNU INFORMATION TECHNOLOGY INSTITUTE
Computer Architecture
Lecture 2: Instruction & Data representation
Duy-Hieu Bui, PhD
AIoT Laboratory
Email: hieubd@[Link]
[Link]
Content adapted from “Computer Organization and Design RISC-V
Edition: The Hardware Software Interface, Second Edition” by David A.
Patterson, John L. Hennessy, published by Morgan Kaufmann. © 2020
Elsevier Inc. All rights reserved.
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical instructions
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical instructions
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Instruction Set
• The repertoire of instructions of a computer
• Different computers have different instruction sets
– But with many aspects in common
• Early computers had very simple instruction sets
– Simplified implementation
• Many modern computers also have simple instruction
sets
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The RISC-V Instruction Set
• Used as the example throughout the book
• Developed at UC Berkeley as open ISA
• Now managed by the RISC-V Foundation
([Link])
• Typical of many modern ISAs
– See RISC-V Reference Data tear-out card
• Similar ISAs have a large share of embedded
core market
– Applications in consumer electronics, network/storage
equipment, cameras, printers, …
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Arithmetic Operations
• Add and subtract, three operands
– Two sources and one destination
add a, b, c // a gets b + c
• All arithmetic operations have this form
• Design Principle 1: Simplicity favors regularity
– Regularity makes implementation simpler
– Simplicity enables higher performance at lower cost
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Arithmetic Example
• C code:
f = (g + h) - (i + j);
• Compiled RISC-V code:
add t0, g, h // temp t0 = g + h
add t1, i, j // temp t1 = i + j
add f, t0, t1 // f = t0 - t1
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Register Operands
• Arithmetic instructions use register
operands
• RISC-V has a 32 × 64-bit register file
– Use for frequently accessed data
– 64-bit data is called a “doubleword”
• 32 x 64-bit general purpose registers x0 to x31
– 32-bit data is called a “word”
• Design Principle 2: Smaller is faster
– c.f. main memory: millions of locations
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RISC-V Registers
• x0: the constant value 0
• x1: return address
• x2: stack pointer
• x3: global pointer
• x4: thread pointer
• x5 – x7, x28 – x31: temporaries
• x8: frame pointer
• x9, x18 – x27: saved registers
• x10 – x11: function arguments/results
• x12 – x17: function arguments
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Register Operand Example
• C code:
f = (g + h) - (i + j);
– f, …, j in x19, x20, …, x23
• Compiled RISC-V code:
add x5, x20, x21
add x6, x22, x23
sub x19, x5, x6
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Memory Operands
• Main memory used for composite data
– Arrays, structures, dynamic data
• To apply arithmetic operations
– Load values from memory into registers
– Store result from register to memory
• Memory is byte addressed
– Each address identifies an 8-bit byte
• RISC-V is Little Endian
– Least-significant byte at least address of a word
– c.f. Big Endian: most-significant byte at least address
• RISC-V does not require words to be aligned in
memory
– Unlike some other ISAs
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Memory Operand Example
• C code:
A[12] = h + A[8];
– h in x21, base address of A in x22
• Compiled RISC-V code:
– Index 8 requires offset of 64
• 8 bytes per doubleword
ld x9, 64(x22)
add x9, x21, x9
sd x9, 96(x22)
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Registers vs. Memory
• Registers are faster to access than memory
• Operating on memory data requires loads and stores
– More instructions to be executed
• Compiler must use registers for variables as much as
possible
– Only spill to memory for less frequently used variables
– Register optimization is important!
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Immediate Operands
• Constant data specified in an instruction
addi x22, x22, 4
• Make the common case fast
– Small constants are common
– Immediate operand avoids a load instruction
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Unsigned Binary Integers
• Given an n-bit number
x = x n−1 2n−1 + x n−2 2n−2 + + x1 21 + x 0 20
• Range: 0 to +2n – 1
• Example
– 0000 0000 … 0000 10112
= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
• Using 64 bits: 0 to +18,446,774,073,709,551,615
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2s-Complement Signed Integers
• Given an n-bit number
x = − x n−12n−1 + x n−2 2n−2 + + x1 21 + x 0 20
• Range: –2n – 1 to +2n – 1 – 1
• Example
– 1111 1111 … 1111 11002
= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
• Using 64 bits: −9,223,372,036,854,775,808
to 9,223,372,036,854,775,807
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2s-Complement Signed Integers
• Bit 63 is sign bit
– 1 for negative numbers
– 0 for non-negative numbers
• –(–2n – 1) can’t be represented
• Non-negative numbers have the same unsigned
and 2s-complement representation
• Some specific numbers
– 0: 0000 0000 … 0000
– –1: 1111 1111 … 1111
– Most-negative: 1000 0000 … 0000
– Most-positive: 0111 1111 … 1111
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Signed Negation
• Complement and add 1
– Complement means 1 → 0, 0 → 1
x + x = 1111...1112 = −1
x + 1 = −x
• Example: negate +2
– +2 = 0000 0000 … 0010two
– –2 = 1111 1111 … 1101two + 1
= 1111 1111 … 1110two
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Sign Extension
• Representing a number using more bits
– Preserve the numeric value
• Replicate the sign bit to the left
– c.f. unsigned values: extend with 0s
• Examples: 8-bit to 16-bit
– +2: 0000 0010 => 0000 0000 0000 0010
– –2: 1111 1110 => 1111 1111 1111 1110
• In RISC-V instruction set
– lb: sign-extend loaded byte
– lbu: zero-extend loaded byte
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical instructions
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Representing Instructions
• Instructions are encoded in binary
– Called machine code
• RISC-V instructions
– Encoded as 32-bit instruction words
– Small number of formats encoding operation code
(opcode), register numbers, …
– Regularity!
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Hexadecimal
• Base 16
– Compact representation of bit strings
– 4 bits per hex digit
0 0000 4 0100 8 1000 c 1100
1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111
◼ Example: eca8 6420
◼ 1110 1100 1010 1000 0110 0100 0010 0000
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RISC-V R-format Instructions
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
• Instruction fields
– opcode: operation code
– rd: destination register number
– funct3: 3-bit function code (additional opcode)
– rs1: the first source register number
– rs2: the second source register number
– funct7: 7-bit function code (additional opcode)
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R-format Example
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
add x9,x20,x21
0 21 20 0 9 51
0000000 10101 10100 000 01001 0110011
0000 0001 0101 1010 0000 0100 1011 0011 two =
015A04B316
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RISC-V I-format Instructions
immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits
• Immediate arithmetic and load instructions
– rs1: source or base address register number
– immediate: constant operand, or offset added to base address
• 2s-complement, sign extended
• Design Principle 3: Good design demands good
compromises
– Different formats complicate decoding, but allow 32-bit
instructions uniformly
– Keep formats as similar as possible
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RISC-V S-format Instructions
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
• Different immediate format for store instructions
– rs1: base address register number
– rs2: source operand register number
– immediate: offset added to base address
• Split so that rs1 and rs2 fields always in the same place
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Stored Program Computers
• Instructions represented in The BIG Picture
binary, just like data
• Instructions and data stored
in memory
• Programs can operate on
programs
– e.g., compilers, linkers, …
• Binary compatibility allows
compiled programs to work
on different computers
– Standardized ISAs
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical operations
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Logical Operations
• Instructions for bitwise manipulation
Operation C Java RISC-V
Shift left << << slli
Shift right >> >>> srli
Bit-by-bit AND & & and, andi
Bit-by-bit OR | | or, ori
Bit-by-bit XOR ^ ^ xor, xori
Bit-by-bit NOT ~ ~
◼ Useful for extracting and inserting
groups of bits in a word
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Shift Operations
funct6 immed rs1 funct3 rd opcode
6 bits 6 bits 5 bits 3 bits 5 bits 7 bits
• immed: how many positions to shift
• Shift left logical
– Shift left and fill with 0 bits
– slli by i bits multiplies by 2i
• Shift right logical
– Shift right and fill with 0 bits
– srli by i bits divides by 2i (unsigned only)
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AND Operations
• Useful to mask bits in a word
– Select some bits, clear others to 0
and x9,x10,x11
x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000
x9 00000000 00000000 00000000 00000000 00000000 00000000 00001100 00000000
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OR Operations
• Useful to include bits in a word
– Set some bits to 1, leave others unchanged
or x9,x10,x11
x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000
x9 00000000 00000000 00000000 00000000 00000000 00000000 00111101 11000000
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XOR Operations
• Differencing operation
– Set some bits to 1, leave others unchanged
xor x9,x10,x12 // NOT operation
x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
x12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111
x9 11111111 11111111 11111111 11111111 11111111 11111111 11110010 00111111
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical instructions
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Conditional Operations
• Branch to a labeled instruction if a condition is
true
– Otherwise, continue sequentially
• beq rs1, rs2, L1
– if (rs1 == rs2) branch to instruction labeled L1
• bne rs1, rs2, L1
– if (rs1 != rs2) branch to instruction labeled L1
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Compiling If Statements
• C code:
if (i==j) f = g+h;
else f = g-h;
– f, g, … in x19, x20, …
• Compiled RISC-V code:
bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit //
unconditional
Else: sub x19, x20, x21
Exit: …
Assembler calculates addresses
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Compiling Loop Statements
• C code:
while (save[i] == k) i += 1;
– i in x22, k in x24, address of save in x25
• Compiled RISC-V code:
Loop: slli x10, x22, 3
add x10, x10, x25
ld x9, 0(x10)
bne x9, x24, Exit
addi x22, x22, 1
beq x0, x0, Loop
Exit: …
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Basic Blocks
• A basic block is a sequence of instructions with
– No embedded branches (except at end)
– No branch targets (except at beginning)
• A compiler identifies basic
blocks for optimization
• An advanced processor can
accelerate execution of basic
blocks
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More Conditional Operations
• blt rs1, rs2, L1
– if (rs1 < rs2) branch to instruction labeled L1
• bge rs1, rs2, L1
– if (rs1 >= rs2) branch to instruction labeled L1
• Example
– if (a > b) a += 1;
– a in x22, b in x23
bge x23, x22, Exit // branch if b >= a
addi x22, x22, 1
Exit:
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Signed vs. Unsigned
• Signed comparison: blt, bge
• Unsigned comparison: bltu, bgeu
• Example
– x22 = 1111 1111 1111 1111 1111 1111 1111 1111
– x23 = 0000 0000 0000 0000 0000 0000 0000 0001
– x22 < x23 // signed
• –1 < +1
– x22 > x23 // unsigned
• +4,294,967,295 > +1
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical instructions
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Procedure Calling
• Steps required
1. Place parameters in registers x10 to x17
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call (address in x1)
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Procedure Call Instructions
• Procedure call: jump and link
jal x1, ProcedureLabel
– Address of following instruction put in x1
– Jumps to target address
• Procedure return: jump and link register
jalr x0, 0(x1)
– Like jal, but jumps to 0 + address in x1
– Use x0 as rd (x0 cannot be changed)
– Can also be used for computed jumps
• e.g., for case/switch statements
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Leaf Procedure Example
• C code:
long long int leaf_example (
long long int g, long long int h,
long long int i, long long int j) {
long long int f;
f = (g + h) - (i + j);
return f;
}
– Arguments g, …, j in x10, …, x13
– f in x20
– temporaries x5, x6
– Need to save x5, x6, x20 on stack
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Leaf Procedure Example
• RISC-V code:
leaf_example:
addi sp,sp,-24
Save x5, x6, x20 on stack
sd x5,16(sp)
sd x6,8(sp)
sd x20,0(sp)
add x5,x10,x11
add x6,x12,x1 x5 = g + h
sub x20,x5,x6 x6 = i + j
addi x10,x20,0 f = x5 – x6
ld x20,0(sp) copy f to return register
ld x6,8(sp) Resore x5, x6, x20 from stack
ld x5,16(sp)
addi sp,sp,24
jalr x0,0(x1)
Return to caller
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Local Data on the Stack
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Register Usage
• x5 – x7, x28 – x31: temporary registers
– Not preserved by the callee
• x8 – x9, x18 – x27: saved registers
– If used, the callee saves and restores them
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Non-Leaf Procedures
• Procedures that call other procedures
• For nested call, caller needs to save on the stack:
– Its return address
– Any arguments and temporaries needed after the call
• Restore from the stack after the call
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Non-Leaf Procedure Example
• C code:
long long int fact (long long int n)
{
if (n < 1) return f;
else return n * fact(n - 1);
}
– Argument n in x10
– Result in x10
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Non-Leaf Procedure Example
• RISC-V code:
fact:
addi sp,sp,-16
sd x1,8(sp) Save return address and n on stack
sd x10,0(sp)
addi x5,x10,-1
bge x5,x0,L1 x5 = n - 1
addi x10,x0,1 if n >= 1, go to L1
addi sp,sp,16 Else, set return value to 1
jalr x0,0(x1) Pop stack, don’t bother restoring values
L1: addi x10,x10,-1
Return
jal x1,fact
n=n-1
addi x6,x10,0
call fact(n-1)
ld x10,0(sp)
ld x1,8(sp) move result of fact(n - 1) to x6
addi sp,sp,16 Restore caller’s n
mul x10,x10,x6 Restore caller’s return address
jalr x0,0(x1) Pop stack
return n * fact(n-1)
return
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Memory Layout
• Text: program code
• Static data: global variables
– e.g., static variables in C,
constant arrays and strings
– x3 (global pointer) initialized
to address allowing ±offsets
into this segment
• Dynamic data: heap
– E.g., malloc in C, new in Java
• Stack: automatic storage
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Local Data on the Stack
• Local data allocated by callee
– e.g., C automatic variables
• Procedure frame (activation record)
– Used by some compilers to manage stack storage
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Outline
• Introduction to Instruction Set
• Operations of the Computer Hardware
• Operands of Computer Hardware
• Signed and Unsigned numbers
• Representing instruction in the computers
• Logical instructions
• Instructions for Making Decisions
• Supporting Procedures in Computer Hardware
• Communicating with People
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Character Data
• Byte-encoded character sets
– ASCII: 128 characters
• 95 graphic, 33 control
– Latin-1: 256 characters
• ASCII, +96 more graphic characters
• Unicode: 32-bit character set
– Used in Java, C++ wide characters, …
– Most of the world’s alphabets, plus symbols
– UTF-8, UTF-16: variable-length encodings
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Byte/Halfword/Word Operations
• RISC-V byte/halfword/word load/store
– Load byte/halfword/word: Sign extend to 64 bits in rd
• lb rd, offset(rs1)
• lh rd, offset(rs1)
• lw rd, offset(rs1)
– Load byte/halfword/word unsigned: Zero extend to 64 bits in rd
• lbu rd, offset(rs1)
• lhu rd, offset(rs1)
• lwu rd, offset(rs1)
– Store byte/halfword/word: Store rightmost 8/16/32 bits
• sb rs2, offset(rs1)
• sh rs2, offset(rs1)
• sw rs2, offset(rs1)
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String Copy Example
• C code:
– Null-terminated string
void strcpy (char x[], char y[])
{ size_t i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
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String Copy Example
• RISC-V code:
strcpy:
addi sp,sp,-8 // adjust stack for 1
doubleword
sd x19,0(sp) // push x19
add x19,x0,x0 // i=0
L1: add x5,x19,x10 // x5 = addr of y[i]
lbu x6,0(x5) // x6 = y[i]
add x7,x19,x10 // x7 = addr of x[i]
sb x6,0(x7) // x[i] = y[i]
beq x6,x0,L2 // if y[i] == 0 then exit
addi x19,x19, 1 // i = i + 1
jal x0,L1 // next iteration of loop
L2: ld x19,0(sp) // restore saved x19
addi sp,sp,8 // pop 1 doubleword from stack
jalr x0,0(x1) // and return
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