COMPUTER ORGANIZATION AND ARCHITECTURE

UNIT-IV
INPUT-OUTPUT ORGANIZATION
I. INPUT-OUTPUT INTERFACE
II. ASYNCHRONOUS DATA TRANSFER
III. MODES OF TRANSFER
IV. PRIORITY INTERRUPT
V. DIRECT MEMORY ACCESS(DMA)

I. INPUT-OUTPUT INTERFACE

The input-output interface provides a means of transferring information between internal

memory and external peripherals. All the peripheral devices connected to the computer need
special communication links to communicate with the CPU. The need for special
communication links to resolve the following differences
a. Peripherals are electromechanical or electromagnetic devices and the operation of
these are different from the mode of operation of the processor. Hence, a signal
conversion is required.
b. The data transfer rate of peripheral devices is slower than that of processors. Hence,
synchronization has to be achieved between peripherals and processors.
c. Data codes of the peripherals differ from the data codes of the processor and
memory.
d. The operating modes of peripherals are different. Hence, each peripheral has to be
controlled so as not to disturb the operating mode of other peripherals.
To resolve such issues, the computer system requires special hardware between the CPU and
peripherals. This component is called INTERFACE.

I/O BUS AND INTERFACE MODULE

About the block diagram
 I/O bus consisting of a data bus to transfer Data, an Address Bus to transfer Address, and
a Control Bus to transfer Control information
 Peripheral can be any input or output devices
 The Interface unit acts as a communication link between the peripheral and the processor.

Address Bus
PERIPHERAL
PROCESSOR

INTERFACE

Data Bus

Control Bus

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 Each peripheral device has an interface that communicates with the processor.
 The interface unit consists of a Decode which decodes the address and control received from the I/O bus.
 Each peripheral device has a controller attached to it. The controller can be external or internal to the
peripheral device.
 Consider the figure below where the peripheral devices are connected to the I/O bus.
 The peripheral devices are a Keyboard, Printer, Magnetic Disc, and Magnetic Tapes. Each peripheral is
connected to the Interface. The I/O bus also is connected to this interface.
 To communicate with a particular peripheral,
 The processor places a device address on the address lines.
 Each device attached to the interface contains a Decoder circuit that monitors the address lines.
 When the interface unit detects its address, it activates the bus paths of connected peripherals.
 When one peripheral is connected, the other peripheral becomes inactive
 At the same time when the address is placed on the address line, the processor also places the
I/O commands.
 The interface selected responds to the I/O command and executes it.
 I/O COMMANDS are of 4 types
 Control Command: Each peripheral has its command. The control command is issued to activate
the peripheral and to inform it what to do.
 Status Command: it is used to check various status conditions. If there are errors during the
transmissions, corresponding bits of the status register are set.
 Output Command: This command causes the interface to respond by transferring data from the
data-bus into one of its registers.
 Input Command: the interface receives data from the peripheral and places it in the internal
register.

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I/O vs MEMORY BUS

I/O versus Memory Bus

The Processor communicates with the peripheral devices through an interface. I/O Bus is used for this
communication.
The processor also needs to communicate with the memory unit. A memory Bus is used for this
communication. Like the I/O bus, the memory bus consists of data lines, address lines, and read/ write
control lines. There are 3 ways of communication with Memory and I/O.
i. Use two separate buses, one for memory and the other for I/O
ii. Use one common bus for both memory and I/O but have separate control lines
iii. Use one common bus for memory and I/O with common control lines.
In the first method, the computer has independent sets of data, addresses, and control buses.ie., one for
memory access and the other for peripheral access. This is done for computers with separate I/O
processors (IOP) apart from the CPU.
The memory communicates with both the CPU and IOP through a memory bus. IOP also communicates
with the input and output peripherals through a separate I/O bus with its address, data, and control lines.
The main purpose of IOP is to provide an independent pathway for the transfer of information between
external devices and internal memory.

Isolated versus Memory-Mapped I/O

Most computers use one common bus to communicate between the memory or I/O and the CPU. The
memory and I/O transfers are distinguished by separate read and write lines. The CPU specifies whether
the address on the address lines is for a memory word or the interface register by enabling the write or
read lines.
I/O read and I/O write control lines are enabled during I/O transfer. Memory read and Memory Write
control lines are enabled during the Memory transfer. This configuration isolates all I/O interface
addresses from the address assigned to memory and is called the isolated I/O method.
Isolated I/O: in this configuration, the CPU has distinct input and output instructions and each of these
instructions is associated with the address of an interface register.
When the CPU fetches and decodes an opcode of input-output instruction, it places the address
associated with the instruction into the common address lines. At the same time, it enables the I/O read
(for input) and I/O write (for output) control lines. This informs the external components that the address
on the address line is for the interface register and not for memory word.
When the CPU fetches an instruction or operand from memory, it places the memory address on
the address lines and enables the memory read or memory write control lines. This informs the external
components that the address is for memory words but not for the interface register.
The isolated I/O method isolates memory and I/O addresses
Memory-mapped: is the other alternative used to the same address space for both memory and I/O. This
applies to the computer that uses only one read-and-write signal and does not distinguish between
memory and I/O addresses. This is called Memory-Mapped I/O.

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In memory-mapped I/O, there are no specific input and output instructions. The CPU can
manipulate the I/O data in the interface register with the same instructions used to manipulate memory
words.
Computers with memory-mapped I/O can use memory-type instructions to access I/O data. It
allows the computer to use the same instructions either for input-output transfers or memory transfers.
'The advantage is that the load and store instructions for reading and writing from memory can be used to
input and output data from I/O registers. In a typical computer, there are more memory-reference
instructions than 110 instructions. With memory-mapped I/O all instructions that refer to memory are also
available for I/O.
Example of I/O Interface:
Figure below shows an example I/O interface.
 It consists of a Status register, a Control register, 2 data registers called ports, a Bus buffer, and a
Timing & Control unit.
 The interface communicates with the CPU through the data bus. The chip-select and register-
select inputs determine the address assigned to the interface. I/O read and I/O write control lines
specify an input and output respectively. The 4 registers directly communicate with the I/O
device.


 The I/O data to and from the device can be transferred through port A or port B. The interface may
operate with an input device(keyboard), an output device(printer), or an input-output device
s(magnetic disc).
 A command is passed to the I/O device by sending a word to the appropriate interface register.
The control is sent to the control register, status information is received from the status register,
and the data is transferred to and from the Ports A and B
 The distinction between data, control, or status registers is determined by the interface register
with which the CPU communicates.
 The control register receives the control information from the CPU and places appropriate bits
into the control register. Based on the control information, a magnetic tape is instructed to rewind
or forward the tape.
 The bits in the status register are used to check for errors. For example, a status bit may indicate
data is received from port A and another status bit may indicate that the error occurred in the
received data.

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 The interface units communicate with the CPU through bidirectional data buses. The address bus
selects the interface unit through chip-select (CS) and register-select (RS0, RS1). RS0 and RS1
are connected to the least significant lines of the address bus.
 The selection of the registers is as per the table.


The content of the selected register is transferred into the CPU via the data bus
when the I/O read signal is enabled. The CPU transfers the binary information to the
selected register when the I/O write signal is enabled.

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II. ASYNCHRONOUS DATA-BUS

CPU and Interface are two separate units. If the registers in the interface share the same clock as the CPU
registers, the transfer between two units is said to be synchronous data transfer. In most of the cases, the internal
timing in each unit is independent from each other, i,e., they use separate clocks. Such type of data transfer is said
to be Asynchronous data transfer.

Asynchronous data transfer between two units requires a control signal to indicate the time at which the data is
received. One way of doing this is by STROBE PULSE and the other is by HANDSHAKE.

STROBE Control:

A strobe pulse is a 1-bit signal which informs the receiver that the data is transmitted by the transmitter.

The strobe pulse can be initiated either by the source (transmitter) or by the destination (receiver).

Consider the source-initiated data transfer as shown in the figure below.

 Initially, the data-bus doesn’t carry data and the strobe pulse is inactive.
 The Source unit then places the data on the data-bus (consists of one wire per bit). The source will wait
for some predefined time until the data is stable on the data-bus.
 It then validates (activates) the strobe signal.
 The data on the data-bus and the strobe signal are in an active state until the destination receives the data
and places data in its internal register.
 The source then removes the data on the data-bus and deactivates the strobe signal.
 Note: The destination will store the data in the internal register at the falling edge of the strobe pulse. i. e,
we need to ensure that the strobe pulse needs to be activated or deactivated when data is available on
the data-bus.
 The timing diagram for the above data transfer is shown below.

 The source can transfer the next set of data only when the strobe pulse becomes active.

Consider the destination-initiated data transfer as shown in the figure below.

 Initially, the data-bus doesn’t carry data and the strobe pulse is inactive.
 The destination unit first validates the strobe.
 The source responds by placing valid data on the data-bus.

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 The data must be available on the data-bus until the destination receives and stores it in the internal
register.
 Then, the destination deactivates the strobe signal and the source removes the data from the data-bus.
 Note: The destination will store the data in the internal register at the falling edge of the strobe pulse. i. e,
we need to ensure that the strobe pulse needs to be activated or deactivated when data is available on
the data-bus.
 The timing diagram for the above data transfer is shown below.

 The source can’t transfer the next set of data until the destination validates the strobe signal.

[ In many computers the strobe pulse is controlled by clock pulses.

If the Source is the CPU, the Destination is the Memory. A write operation is performed by the CPU and
a memory-write strobe signal is activated.

If the source is Memory, the destination is the CPU. A read operation is performed by the CPU and a memory-
read strobe signal is activated.]

In source-initiated and destination-initiated data transfer, the sender (source) may lack confirmation of whether
the data has been successfully received by the recipient (destination).

This drawback of using the strobe pulse can be eliminated by the use of HANDSHAKE where both sender and
receiver can confirm that data has been successfully transmitted and received

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HANDSHAKE:

This disadvantage of using the strobe pulse can be eliminated by the use of HANDSHAKE where both sender and
receiver can confirm that data has been successfully transmitted and received. The Handshake method solves this
problem by introducing an additional signal that provides the information on data received. This signal is
ACKNOWLEDGE.

 The HANDSHAKE method involves two-wire communication.

 One control wire/line is in the same direction as the data i.e., from source to destination, indicating that
data is on the data-bus. This control wire is data-valid generated by the source
 Other control wires are in opposite directions i.e., destination to source, where the destination
acknowledges the data received. This control wire is data-accepted and generated by the destination

Consider the Source Initiated data transfer as shown below

 Initially, the data-bus doesn’t carry data, and data valid, data-accepted are inactive.
 The source unit initiated the data transfer by placing the data on the data-bus.
 At the same time, the source unit validates the data-valid signal indicating the destination that valid data
is on the data-bus.
 Once the data is accepted by the destination unit, it activates the data-accepted signal
 The source learns that the destination has accepted the data deactivates the data-valid signal and
invalidates the data on the data-bus.
 The destination then deactivates the data-accepted signal indicating that it is not ready to accept data.
 The source does not send any data until the data-accepted is activated.
 In this process of data transfer, there is an arbitrary delay from one state to another.
 The slowest device decides the data transfer.
 The timing diagram of this operation is shown below

Consider the destination-initiated data transfer as shown below

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 Initially, the data-bus doesn’t carry data, and data valid, data-accepted are inactive.
 The destination unit initiates the data transfer by activating the ready-for-data line
 The source then places the data on the data-bus, it then activates the data-valid signal indicating the
destination that data is on the data-bus.
 Once the data is accepted by the destination unit, it deactivates the ready-for-data signal
 The source then learns that the destination has accepted the data deactivates the data-valid signal and
invalidates the data on data-bus.
 The source does not send any data until the ready-for-data is activated.
 The timing diagram of this operation is shown below

Asynchronous Serial Data Transfer:

The transfer of data between two units may be done in parallel or serial. In parallel data transmission, each bit of
the message has its path and the total message is transmitted at the same time. This means that an n-bit message
must be transmitted through n separate conductor paths. In serial data transmission, each bit in the message is
sent in sequence one at a time. This method requires the use of one pair of conductors or one conductor and a
common-ground

Parallel Data transfer is faster but requires many wires. Parallel data transfer for short-distance communications
where the speed is the highest priority.

In asynchronous serial data transfer, special bits are inserted at both ends of the character to be transmitted. With
this, each character consists of 3 parts: Start-bit, character-bits, and stop-bit.

Start-bit is one-bit. When start-bit=0, the data transfer is initiated by the source. When 1, no data is transferred
by source.

Character-bits are 8-bits. character-bit always follows the start-bit. Each bit in the character is transmitted serially
one after the other

Stop-bit is either 1-bit or 2-bit. In earlier communication links, the stop bit is 1-bit. The latest communication links
issue 2-bit stop-bits. Stop-bits should always be 11

Consider the example. Asynchronous data transfer of a character 11000101 as shown below

 As long as start-bit =1, the receiver understands that the transfer is nor initiated
 When star-bit=0, the receiver understands that the transmission started.
 The next 8-bits received pertain to the character.

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 Once the character bits are transmitted, the source has to send 11 as a stop bit
 The receiver now understands that the transmission is completed.

Consider an example of a terminal with a Keyboard and printer where the data entered through the keyboard
is to be printed on the printer.

 Whenever a key is pressed, the terminals send 11 bits (1 stop bit, 8 character bits, and 2 stop bits) of
data serially over the communication link.
 The terminal interface has a receiver and transmitter.
 The transmitter accepts 8-bit characters from the computer and sends an 11-bit message to
the printer line.
 The receiver accepts 11 bits from the keyboard and forwards the 8-bit character code to the
computer.
 Such a circuit with a transmitter and receiver is called an ASYNCHRONOUS COMMUNICATION
INTERFACE or UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART)

Asynchronous Communication Interface/Universal Asynchronous Receiver and Transmitter (UART)

The block diagram for UART is shown below.

 It functions both as a transmitter and receiver.

 Depending on the control byte loaded in the control register, the interface initiates a particular mode of
transfer.
 The transmitter register accepts data from the CPU through a data bus and transfers the data byte to the
shift register for serial transmission.
 The receiver portion receives the data serially and loads the data in the shift register. Data is then moved
to the receiver register.
 The bits in the status register are used for input and output flags and also record some errors
that occurred while transmitting the data.

 The chip Select (CS) and Register Select (RS) are used to select one of the four registers. The selection of
registers is shown in the table

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The transmitter operation is as follows:

 CPU reads the status register and checks the flag(F), if F is empty then
 the CPU transfers the character to the transmitter register.
 The first bit in the transmitter shift register is set to 0 to generate the start bit.
 The character’s 8 bits are transferred from the transmitter register to the shift register in parallel. The
transmitter register is now empty.
 An appropriate number of stop-bits are appended to the shift register.
 The 11-bit character can now be transferred serially(bit-by-bit) from the shift register at the specified baud
rate (BAUD RATE: the rate at which serial information is transmitted and is equivalent to the data
transferred in bits per second)

The receiver operation is as follows:

 The received data input is at 1 state when the line is idle.

 When the receiver data input receives a 0 which is the occurrence of start-bit.
 When the start bit is detected, the character bits are stored in the shift register at the speed specified by
the baud rate.
 After receiving, the interface checks for the parity bits and stop bits.
 Once the stop bits are received, then the character bits after removal of stop and start bits are moved into
the receiver register.
 The interface checks for any possible errors during transmission and sets appropriate bits in the status
register. The CPU can read the status register at any time to check if any errors have occurred

FIRST-IN, FIRST-OUT(FIFO) BUFFER

 A first-in, first-out (FIFO) buffer is a memory unit that stores information in such a manner that the item
first in is the item first out.
 A FIFO buffer comes with separate input and output terminals.
 The important feature of this buffer is that it can input data and output data at two different rates and the
output data are always in the same order in which the data entered the buffer.
 When placed between two units, the FIFO can accept data from the source unit at one rate of transfer and
deliver the data to the destination unit at another rate.
 If the source unit is slower than the destination unit, the buffer can be filled with data at a slow rate and
later emptied at a higher rate.
 If the source is faster than the destination, the FIFO is useful for those cases where the source data arrive
in bursts that fill out the buffer but the time between bursts is long enough for the destination unit to
empty some or all the information from the buffer.
 Thus, a FIFO buffer can be useful in some applications when data are transferred asynchronously. It piles
up data as they come in and gives them away in the same order when the data are needed.
 The logic diagram of a typical 4 x 4 FIFO buffer is shown in the figure above. It consists of four 4-bit
registers RI, I = 1,2,3,4, and a control register with flip-flops ft , i = 1,2,3,4, one for each register
 The FIFO can store four words of four bits each

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 A flip-flop Fi in the control register that is set to 1 indicates that a 4-bit data word is stored in the
corresponding register RI. A 0 in Fi indicates that the corresponding Register does not contain valid data.
 Whenever the Fi bit of the control register is set (Fi = 1) and the Fi+l bit is reset, a clock is generated causing
register R (I + 1) to accept the data from register RI. The same clock transition sets Fi+l to 1 and resets Fi to
0.
 Data are inserted into the buffer provided that the input-ready signal is enabled. This occurs when the first
control flip-flop F1 is reset, indicating that register R1 is empty. Data are loaded from the input lines by
enabling the clock in R 1 through the insert control line. The same clock sets F1, which disables the input
ready control, indicating that the FIFO is now busy and unable to accept more data.
 If the FIFO is full, Fl remains set and the input ready line stays in the 0 state. Note that the two control
lines input ready and insert constitute a destination-initiated pair of handshake lines.
 The data falling through the registers stack up at the output end. The output ready control line is enabled
when the last control flip-flop F4 is set, indicating that there are valid data in the output register R4.

 The output data from R4 are accepted by a destination unit, which then enables the delete control
signal This resets F4, causing output ready to disable, indicating that the data on the output are no
longer valid.
 Only after the delete signal goes back to a can the data from R3 move into R4. If the FIFO is empty,
there will be no data in R3 and F4 will remain in the reset state.
 Note that the two control lines output ready and delete constitute a source-initiated pair of
handshake lines.

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