UNIT-I

(PART-2)
BASIC COMPUTER ORGANIZATION AND DESIGN

1. INSTRUCTION CODES
2. COMPUTER REGISTERS and INSTRUCTIONS
3. TIMING AND CONTROL
4. INSTRUCTION CYCLE
5. MEMORY REFERENCE INSTRUCTION
6. INPUT-OUTPUT
7. INTERRUPTS

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 I. INSTRUCTION CODES:
Program portion
Instruction Code is a of memory binary code that specifies a sequence of
microoperations. All the (holds instructions) instruction codes are stored in the memory
in binary along with the data bits. The computer reads the instruction from
memory and places the codes on the control register, the control register in
turn decodes the binary codes and proceeds to execute the instruction.
Data portion
a. Operational of memory Code(opcode):
(holds operands)
An instruction code is divided into two parts. Each part has its
specific functionality. The basic part is operation code(opcode). The
opcode defines basic microoperations like add, shift, etc. The total
number of operations available in the computer defines the length of the opcode. For 2n distinct
operations, the opcode is n-bit length.

 For a computer with 64 distinct operations, the opcode is 6-bit long.

 If 111010 is the opcode for an ADD operation, the control unit decodes it as an addition
operation and instructs the control signal to fetch the operand from memory and add it to the
processor register.
 An opcode is referred as macrooperation as it specifies a set of microoperations.

An opcode of an instruction code defines a microoperation to be performed. This operation is

performed on the data present in the processor register or the data present in memory. For this reason,
the instruction code should also specify the registers and memory from where the operands have to be
fetched.
Memory is specified in the instruction code by their address and the Processor Register is
specified by assigning to the instruction another binary code of k-bits to point one of 2k registers.

b. Stored Program Organization:

The simplest way to organize a computer is to have a processor register and an instruction code
with two parts. One part specifies the operation code(opcode) and the other specifies the address. This
address tells the control unit where to find the operand from the memory. Once this operand is read, it
is transferred as data and is operated together with the content of the processor register.

Consider an example where the memory capacity is 4K words, which requires 12 address lines to
specify each memory cell. storing each instruction code in one 16-bit memory word requires a 12-bit
address and 4-bit opcode.

Instruction format

4K x 16 Memory

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 Since opcode is of 4bits, the processor has 24 (16) microoperations.
The control unit reads the 16-bit instruction from the program portion of the memory. It uses 12-
bit address portion to read the 16-bit operand from the data portion of memory and the operation
specified by the 4-bit portion is executed.

When a computer has only one processor register then it is defined as accumulator (AC) and
all the operations are performed with the memory and the accumulator. For the operations like
clear AC, increment AC memory is not required we do not require the operands from bits11-0,
operand is required only when memory is involved.

c. Addressing:
We know that the second part of the instruction code is an operand.
 If this part consists of an operand, then the instruction is said to have an immediate
operand
 If this part specifies the address of the operand, then the instruction is said to have
the direct address.
 If this part specifies the address of a memory word in which the address of the operand is
found is the indirect address.
In order to accommodate addressing mode, the 4-bit opcode is divided into 3-bit and 1-bit. This 1-
bit is reserved to distinguish between direct address and indirect address. The 3-bit is used to
specify an opcode. The operand is a12 bit value. The instruction format thus modifies as.

Instruction format for direct/indirect address

I=0  instruction is direct address mode

I=1  instruction is indirect address mode

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 Consider a direct addressing(I=0) instruction as shown below.
Here the instruction is places in address 22 in the memory. The flow of operation is as follows.
 I=0 specifies the instruction as direct address: bit15
 Opcode ADD specifies addition operation : bit14,13,12
 Address part specifies the address as 385 : bit 11-0
 Control then searches the address 385 in memory and fetches the operand
 This operand is added to the content of accumulator and the result is stored in
accumulator

Consider an indirect addressing(I=1) instruction as shown below.

Here the instruction is placed in address 22 in the memory. The flow of operation is as follows.
 I=1 specifies the instruction as an indirect address : bit15
 Opcode ADD specifies addition operation : bit14,13,12
 Address part specifies the address as 385 : bit 11-0
 Control finds the address of the operand as 1238
 Control finds the operand in address 1238
 This operand is added to the content of the accumulator and the result is stored in
the Accumulator

Effective address: is the address where the operand is found. In the above examples, the
effective address for direct address is 385 and for the indirect address is 1238

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 II. COMPUTER REGISTERS:

Computer instructions are stored in consecutive memory locations and are executed sequentially
one after the other. The control unit reads an instruction from the given address in memory,
decodes it, and executes it. It then continues to read the next set of instructions from memory,
decodes it, and executes and goes on.

To calculate the address of the next instruction after the execution of the present instruction, we
need a Program Counter (PC)

Once an instruction is fetched, the control unit requires a register to store the instruction code.

The computer requires a processor register to manipulate the data and a memory for holding the
memory address. Considering a memory of 4K words and each word contains 16 bits, the list of
a few registers used in a computer is shown in the table below

Sl. Register No. of bits Name of Register Function

Symbol
1 DR 16 Data Register Hold memory operand
2 AR 12 Address Register Hold address of memory
3 PC 12 Program Counter Holds address of instruction code
4 IR 16 Instruction Register Holds instruction code
5 AC 16 Accumulator Processor register
6 TR 16 Temporary Register Holds Temporary data
7 INPR 8 Input Register Holds input character
8 OUTR 8 Output Register Holds output character

The program counter holds the address of the next instruction to be executed, PC will hold the 12-
bit address.

Common Bus:
 The basic computer has 8 registers, a memory unit, and a control unit.
 A proper path needs to be provided for the transfer of information from one register to another,
and between memory and register.
 In doing so, a large number of wires are required to connect the output of one register to the
input of the remaining registers. This bulk use of wires can be eliminated by using common
bus
 The connection of the common bus to all registers and memory is shown in Fig.1
The block diagram involves 8 registers and memory.
 The input data coming from the input device is first moved to the Accumulator (AC) register
because of which the input register (INPR) is not connected to the common bus. The output
register (OUTR) receives the data on the common bus from the accumulator and sends the
data to the output device
 Excluding INPR and OUTR, the remaining devices are numbered from 0 through 7.
 In order to send data to and from memory/registers we have to select a particular component,
 8x1 MUX with 3 select lines(S2S1S0) is used for selection of components.

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  A 16-bit common bus is used for the transfer of data, address, and select bits.
S2S1S0 = 111 selects memory. Memory operations like read and write require a 12-bit address
from the Address Register (AR). When RD=1 and WR=0, the 16-bit code from the address
location specified by AR is placed on the bus. When RD=0 and WR=1, the 16-bit data from
the 16-bit common bus is placed in the memory location specified by the AR.
S2S1S0 = 001, the Address Register (AR) is selected. When LD=1, AR is loaded with the 12-bit
address. INR increments AR and CLR clears AR to zero.

Fig: 1: Data Flow using common bus to all registers and memory

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 S2S1S0 = 010, the Program Counter (PC) is selected. PC holds the 12-bit address of the next
instruction to be executed. With LD=1, the information on the common bus is loaded on the PC,
INR increments the PC, and CLR clears the PC to zero.
S2S1S0 = 011, the Data Register (DR) is selected. DR holds 16-bit data. With LD=1, the
information on the common bus is loaded into DR, INR increments the DR, and CLR clears the
DR to zero.
S2S1S0 = 101, the Instruction Register (IR) is selected. IR holds the 16-bit instruction code
from memory. With LD=1, the instruction code on the common bus is loaded into IR.
S2S1S0 = 110, the Temporary Register (TR) is selected. TR holds 16-bit data. With LD=1, the
16-bit data on the common bus is loaded on TR, INR increments TR and CLR clears TR to zero.
S2S1S0 = 100, the Accumulator (AC) is selected. AC holds the 16-bit data. The accumulator
receives three sets of data, the first set comes from the ALU executes Arithmetic, Logic, and Shift
operations, the second set comes from the DR, and the third set comes from INPR. Inputs from
ALU and DR are involved in operations like ADD, AND, etc. The result is stored in AC and if a
carry is generated is stored in flipflop (E).
All the registers are connected with a common clock. Content of any register can be placed on
the bus and an operation can be performed in the ALU during the same clock cycle. The clock
transition at the end of the cycle transfers the content of the bus into the destination register.

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 III. COMPUTER INSTRUCTIONS:

Basic computer has 3 instruction formats each of 16-bit in length.

1. Memory-reference instruction
2. Register-reference instruction
3. Input-output instruction
.
 Memory-Reference Instruction uses 12 bits to represent address, 1 bit for the addressing mode (I)
and 3 bits for opcode. we know that I=0 for direct and 1 for indirect addressing modes.

 Register-Reference Instruction is identified by the opcode bit-14, bit-13, bit-12 as 111 and bit15
as 0. These instructions refer to the operations on the accumulator. The remaining 12 bits are used
to specify the opcode of register-reference operations. Note: Memory is not involved in this
instruction type
 Input-Output Instructions is identified by the opcode bit-14, bit-13 as 111 and bit15 as 1. The
remaining 12 bits are used to specify the opcode of input-output operations. Note: Memory is not
involved in this instruction type.

Memory-reference instruction

Register-reference instruction

Input-Output instruction

 When a direct or indirect addressing mode is used, the opcode length is 3 bits which informs
that there are only 8 operations.
 But during the register-reference and input-output reference, bit11-0 refer the opcode for
remaining operations.
 The type of the instruction is identified by the opcode bits 15-12. If the opcode bits14-12 is
111, the control will check for bit-15. If bit15 is 0 then it refers to register-reference instruction
and if it is 0 then it refers to input-output instruction.

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 A basic computer with 25 instructions is discussed next.
Memory Reference Instruction
SYMBOL Hexadecimal code Comment
I=0 I=1
(Direct Addressing) (Indirect Addressing)
AND 0xxx 8xxx AND the data present in memory to AC
ADD 1xxx 9xxx ADD the data present in memory to AC
LDA 2xxx axxx LOAD the data from memory to AC
STA 3xxx bxxx STORE the data on AC to memory
BUN 4xxx cxxx Branch Unconditionally
BSA 5xxx dxxx Branch and Save return address
ISZ 6xxx exxx Increment and skip if zero

Register-Reference Instructions:

SYMBOL Hexadecimal Code Comment

CLA 7xxx clear AC

CLE 7xxx clear E
CMA 7xxx complement AC
CME 7xxx Complement E
CIR 7xxx Circular shift right AC
CIL 7xxx Circular shift left AC
INC 7xxx Increment AC
SPA 7xxx Skip next instruction if AC is positive
SNA 7xxx Skip next instruction if AC is negative
SZA 7xxx Skip next instruction if AC is zero
SZE 7xxx Skip next instruction if E=0
HLT 7xxx Halt Computer

Input-Output Reference Instructions:

SYMBOL Hexadecimal Code Comment

INP Fxxx Input character to AC

OUT Fxxx Output character from AC
SKI Fxxx Skip on input flag
SKO Fxxx Skip on output flag
ION Fxxx Interrupt on
IOF Fxxx Interrupt off

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 Instruction set Completeness
What are the types of instructions that are to be included in a computer?
A computer should have a set of instructions so that users can construct machine language
programs to evaluate any computable function. The set of instructions is said to be complete if the
computer includes a sufficient number of instructions in each of the following categories.
i. Instructions to move data between memory and register: The bulk of information is
always stored in memory, but the computations are done only in registers. For this,
a sufficient number of instructions are needed to move data between memory and registers
ii. Program control instructions together with instructions that check status conditions :
Decision-making capability is most important for a computer. If we compare 2 numbers, if
the first is greater than the second, we may go in one approach and if the first is smaller
than the second, we may go in a different approach. For this, we require program control
instructions like branch instructions to change the sequence of instructions.
iii. Input and output instructions: Input and output instructions are used for communications
between computer and user i.e., programs and data must be transferred to the memory and
the results after computation is sent back to the user.
iv. Arithmetic, Logic, and Shift Instructions: these are the basic operations the user wish to
compute.

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 IV. TIMING AND CONTROL

The computer operations are synchronized with a master clock, where the clock will decide
when to perform an operation. The clock pulses are applied to the flipflop and registers in the
systems as well as to the flipflops are registers present in the control unit.

The clock itself will not contribute to the execution of instructions. Along with the clock, we
require the register to be enabled; for this, we require a control signal. These control inputs are
generated in the control input and are well connected to the multiplexers in the common bus,
control inputs in the processor register, and microoperations in the accumulator.

There are two types of control organization.

i. Hardwired control
ii. Microprogrammed control

Hardwired Control Microprogrammed control

The control logic is implemented using logic Control information is stored in the control
gates, multiplexers, decoders, and other digital memory
circuits.
Design is optimized for faster operation The control memory is programmed to initiate
the microoperations
We need to make changes to wires connected For any modifications, we just need to
between different components for any reprogram
modifications.
Because of regular modifications, the design is The design her is very simple
complex

Fig. 2 shows the block diagram shown below and describes the control unit. It consists of
i. 3 x 8 Decoder to select a data bit from register
ii. 4 x 16 Decoder to generate timing network
iii. Sequence Counter (SC) for sequence generator
iv. Control logic gates
The instruction read from memory is placed in the instruction register (IR). The
instruction code is divided into 3 parts. Bit15, Bit14-12, Bit11-0. the bits14-12 are decoded
with 3 x 8 decoder. The 8 outputs are denoted by D7 through D0. Bit15 is loaded into the
flip-flop. Bits 0-11 are applied to the control gates as shown in Fig. 2
The 4-bit sequence counter can count from 0 to 15, the outputs of the SC are
connected to the 4 x 16 decoder which is further decoded to timing signals T 0, T1, …., T15.
The counter can reset to 0 using the CLR. Once the counter is cleared, the next timing
cycle is T0 as shown in the fig.3
Consider the case where the SC is incremented to generate timing signals T 0, T1, T2,
T3, and T4. At T4, SC is cleared to 0 when D 3 bit of decoder output is high. This is
expressed as

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 D3T4: SC0

Fig 2: control unit

Fig 3: Timing Diagram

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INSTRUCTION CYCLE:
The programs reside in the memory unit in a sequential order. These programs are executed in a cycle
for each instruction. These cycles are in turn divided as phases or subcycles. The following are the
phases through which as instruction execution goes through
1. Fetch an instruction from the memory
2. Decode the instructions (understand the operation to be performed and where to find the operands)
3. Read the effective address of the memory if the instruction is an indirect addressing mode.
4. Execute the instruction

The above phases are repeated for the instructions in the program and the execution will be
stopped when a HALT instruction occurs.

Functioning of Fetch and Decode phases

Initially, the PC is loaded with the address of the first instruction in the program and SC
is cleared to 0, when SC =0, the timing signal T 0 from the 4x16 decoder is connected to
the control logic circuit. For each clock pulse, SC is incremented by 1 and the timing signals T 1,
T2, T3, …… are made available to the control logic gate. The following statements explain the
fetch and decode phases
T0: AR PC
T1: IR [AR], PC=PC+1
T2: D0, D1, …. D7  Decode (12-14), ARIR (0-11), I  IR (15)

Fig 4: Flow of Fetch Instruction

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 Fig. 4 shows how a fetch phase is processed.
The operation of the fetch cycle starts with loading the address of the first instruction onto
the PC and setting the SC to 0. With SC=0 and the rising edge of the clock pulse, the decoded
timing signal is T0. Subsequent clock cycle will generate the timing signals T1, T2, T3, ….., T15 .
When T0=1:
 S2S1S0= 010, PC is selected
 With T0=1, LD pin of AR is 1 which makes the information present on common bus to
be loaded onto AR.
 Thus, AR PC

We now need to place the instruction code from the memory into IR register.
When T1=1:
 S2S1S0= 111, memory is selected
 Read pin of memory =1, this indicates that a read operation is to be done from memory
 The data present in the memory location indicated by AR is placed on the common bus
 At the same time, the LD pin of the PC is 1, hence PCPC+1
 Also, LD=1 for IR register, hence the data present of the common bus is moved to IR.
 Thus, IR[AR] and PCPC+1
When T2=1:
The instruction code is decoded as follows
 Bits 12-14 is decoded as D0, D1, …. D7: D0, D1, …. D7  Decode IR (12-14)
 Bit 15 refers to the type of memory addressing mode: I  IR (15)
 Bit 0-11 refers to the address bits: ARIR (0-11),
At the end of T1, the first instruction is placed in AR. At the end of T2, the decoding of
the instructions code is completed. The subsequent timing signals will then search for the
operands and execute the instructions.
After the execution of every instruction, SC should be cleared to zero SC0.
NOTE: During Memory-Reference instructions, the memory is involved in fetching the
instruction code as well as one of the operands, the registers are involved in finding the second
operand

Register-Reference Instructions:
For register reference instructions, Bits B 14B12B11 = 111 and B15=0. With B14B12B11 = 111, the
decoded output line is D7 and with B15=0 we have I=0. Bits B0 to B11 will specify one of the 12
operands. All these bits are transferred to AR during T2.
These instructions are executed during T3. Thus, the control function is D7’ I T3.

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 The bits through B0 to B11 are designated as Bi, where i=0 to 11.
Let D7’ I T3 = r, then
rB11 performs clear Accumulator operation
rB5 performs increment AC
the remaining Register reference instructions are shown in the table below.

NOTE: During Register-Reference instructions, the memory is involved only for fetching the
instruction code and the registers are involved for finding the operands

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 V. MEMORY REFERENCE INSTRUCTIONS

From Fig. 2, the decoded output signals D0 through D7 refer to each operation as listed above

The effective address is the address of the memory location where the operand is present. During
direct addressing mode(I=0), the effective address is placed in AR during T 2 and for indirect
addressing mode (I=1) it is placed in AR during T 3. Thus, the execution of memory reference
instructions will start at timing signal T4. The above microoperations are discussed as follows.
AND: This instruction performs the AND operation on the operands. One operand is present in
memory and the other is in the AC register, the result is then stored in AC. The sequence of
operations is as follows
D0T3 : DR  [AR]
D0T4: AC  AC ˄ DR, SC  0
In this, operation decoder D0 is active when the opcode is 000. For execution of this
instruction, we require 2 timing signals, during T 3 the operand is moved to DR and during T 4 the
AND operation is executed. Since the execution is complete the sequence counter has to reset at
the same clock cycle (SC0). After this, the control is transferred to timing signal T0.

ADD: This instruction adds the content of memory location to the content of AC and stores the
result in AC. The carry generated is stored in Flipflop E. The microoperation is as follows.
D1T3 : DR  [AR]
D1T4: AC  AC + DR, E  Cout, SC  0
In this, operation decoder D1 is active when the opcode is 001. For execution of this
instruction, we require 2 timing signals, during T 3 the operand is moved to DR and during T 4 the
ADD operation is executed. Since the execution is complete the sequence counter has to reset
(SC0) and the carry generated has to be stored in E at the same clock cycle. After this, the
control is transferred to timing signal T0.

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 LDA: this instruction loads the AC with the information present in memory. This also involves 2
timing cycles
D2T3 : DR  [AR]
D2T4: AC  DR, SC  0
In this, operation decoder D2 is active when the opcode is 010. For execution of this
instruction, we require 2 timing signals, during T 3 the operand is moved to DR, and during T 4 the
move the information from DR to AC. Since the execution is complete the sequence counter has to
reset (SC0) at the same clock cycle. After this, the control is transferred to timing signal T 0.
STA: this instruction stores the information on AC in the memory location. Since the information
is readily available in AC, we require one timing signal to place the data into memory locations.
D3T3 : [AR]  AC, SC  0
BUN: Branch Unconditionally.
D4T4 : PCAR, SC  0

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 VI. INPUT-OUTPUT INSTRUCTIONS

Instructions and data stored in the memory have to come from some input device and the
computational results have to be sent to the output device.

Figure below is the block diagram of the flow of input and output data. It uses a keyboard as
an input device and a printer as an output device. Each quantity of information is 8-bit in
length. INPR is the input register used to store the input data and OUTR is the output register
used to store the output data. Alphanumeric data is transferred serially from the keyboard to
INPR, but transmitted parallelly from INTR to AC. Similarly, data is loaded parallelly into
OUTR and transmitted serially from OUTR to the printer.

When we strike the keyboard, the 8-bit alphanumeric data is transmitted serially and placed in
8-bit INPR. Before this data is loaded to AC if another keyboard strike occurs, the older data is
replaced with new data. To avoid this, a control flipflop FGI (input flag) is used at the input
end. Similarly, a flip-flop FGO is used at the output end.

Initially, FGI is 0, as long as FGI=0 the data can be sent through the keyboard. This data is
transmitted serially and placed on the INPR register. At this moment, the FGI should be made
1 to avoid any new input data from the keyboard. When FGI=1, the data in the INPR is loaded
to AC parallelly. Once the data is loaded to INPR, FGI is cleared to zero.

At the output end the computer checks for FGO. If FGO = 1, the data from AC is loaded to
OUTR parallelly. At this time, FGO is reset to 0 so that the data on OUTR can be transmitted
serially to the printer.

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 Input-Output Instructions:

For input-output instructions, bit15=1 and Bits 14,13,12 is 111 and the execution takes places at
T3. Thus, the control signal is D7IT3. Let Bi represents one of the 6 operations represented by bits
6 to 11. The following table represent the input-output operations.

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