[Type text]

University of Mines & Technology

Computer Science & Engineering Department

Bsc. Computer Science and Engineering

Microprocessors & Microcontrollers

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University of Mines & Technology Computer Science & Engineering Department

 Bsc. Computer Science and Engineering Microprocessors & Microcontrollers

Course Outline ................................................................................................... 4

Course Objectives .............................................................................................. 4
Course Presentation .......................................................................................... 4
References and Recommended Textbooks ........................................................ 4
Course assessment ............................................................................................ 5
Attendance ........................................................................................................ 6
CHAPTER ONE.................................................................................................... 7
1 Overview of Microprocessor Systems and their basic structure ................ 7
1.2 General Architecture of a Microcomputer System ..................................................................... 7

1.3 Classification of Microprocessors and Microcontrollers .......................................................... 12

1.4 Types of Microprocessors /Microcontrollers ............................................................................ 14

1.5 Microprocessor and Microcontroller Data sheet descriptions ................................................. 15

CHAPTER TWO................................................................................................. 16
2 Intel 8085 Microprocessor Architecture and Its Operational Features .... 16
Chapter objectives and expected results.......................................................................................... 16

3.1 Intel 8085 Internal Architecture ................................................................................................ 16

3.1.1 Functional Units of Intel 8085 Microprocessor ...................................................................... 16

3.1.2 Pin Diagram of 8085 Microprocessor ...................................................................................... 19
3.1.3 Intel 8085 Addressing modes ................................................................................................... 21
3.1.4 Interrupts on 8085.............................................................................................................. 22
3.1.5 8085 Instruction Sets................................................................................................................. 24
3.1.6 Instruction Format .................................................................................................................... 41

CHAPTER THREE .............................................................................................. 44

3. Intel 8086 Microprocessor Architecture ................................................... 44
Chapter objectives and expected results.......................................................................................... 44

3.1 Intel 8086 Microprocessor Architecture and Operational Functions ....................................... 44

3.2 Features of Intel 8086 ................................................................................................................ 45

3.3 Architecture of Intel 8086 .......................................................................................................... 46

3.4 Intel 8086 Pin Diagram and Functions ....................................................................................... 54

Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa,
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 Bsc. Computer Science and Engineering Microprocessors & Microcontrollers

3.5 Intel 8086 Instruction Set ........................................................................................................... 58

3. 6 Intel 8086 Interrupts ................................................................................................................. 64

3.7 Intel 8086 Addressing Modes .................................................................................................... 67

3.8 Memory address space and data organization ......................................................................... 69

CHAPTER FOUR................................................................................................ 74
4. Multiprocessor Architecture ..................................................................... 74
4.1 Multiprocessor Configuration Overview ................................................................................... 74

4.2 8087 Numeric Data Processor.................................................................................................... 77

4.2.1 8087 Architecture ...................................................................................................................... 78

4.2.2 8087 Pin Description .................................................................................................................. 79

CHAPTER FIVE .................................................................................................. 82

5. Interfacing Input and Output devices to the Microprocessor .................. 82
5.1 Input and Output Interfaces ...................................................................................................... 82

5.2 8279 - Programmable Keyboard ................................................................................................ 84

5.2.1 8279 Pin Description .......................................................................................................... 86

5.2.2 Operational Modes of 8279 ...................................................................................................... 88
5.3 8257 DMA Controller ................................................................................................................. 89

5.3.1 8257 Architecture ...................................................................................................................... 90

Figure 5.4 Architecture of 8257 ........................................................................................................... 90
5.3.2 8257 Pin Description................................................................................................................... 91
Figure 5.5 Pin Diagram 8257 Controller.............................................................................................. 91

CHAPTER SIX .................................................................................................... 94

6. Microcontrollers........................................................................................ 94
Chapter objectives and expected results.......................................................................................... 94

6.1 Overview of Microcontrollers .................................................................................................... 94

6.2 Intel 8051 Architecture .............................................................................................................. 97

6.2.1 Intel 8051 Pin Description ........................................................................................................ 97

6.2.2 Microcontrollers 8051 Input Output Ports ............................................................................. 99
6.2.3 Microcontrollers - 8051 Interrupts ........................................................................................ 101
END OF SECOND SEMESTER EXAMINATION ................................................................................... 104

Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa,
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 Bsc. Computer Science and Engineering Microprocessors & Microcontrollers

END OF SECOND SEMESTER EXAMINATION ................................................................................... 112

Course Outline
Microprocessor and Microcontroller Systems is an undergraduate Computer Science and
Engineering course. The course is design to look at:

o The introduction and evolution of some Microprocessors and Microcontrollers;

o Overview Intel 8080/8085 and Intel 8086/8088 hardware and instruction sets;
o Overview of the 8051 and AVR hardware and instruction sets;
o Assembly Language Programming.

Course Objectives
At the end of this course students are expected to:

o Be able to differentiate between microprocessors and microcontrollers with examples;

o Be able to describe the architecture and organization of specific microprocessors
/microcontrollers and its instruction set;
o Be able to write structured, well-commented, understandable programs in assembly
language that can run on specific microprocessors / microcontrollers;
o Understand techniques for interfacing I/O devices to the microprocessor
/microcontroller, including several specific standard I/O devices.

Course Presentation
The course is presented through lectures supported with handouts and tutorials. The tutorial
will be in the form of problem solving and discussions and will constitute an integral part of
each lecture. The student can best understand and appreciate the subject by attending all
lectures and laboratory work, by practicing, reading references and handouts and by
completing all assignments and course work on schedule.

References and Recommended Textbooks

a. Muhammad Mazidi and Janice Mazidi, Prentice Hall, 4th Edition, 2003. The 80x86
IBM PC and Compatible Computers (Volume I and II): Assembly Language, Design
and Interfacing

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 Bsc. Computer Science and Engineering Microprocessors & Microcontrollers

b. Walter A. Triebel and Avtar Singh, Prentice Hall, 4th Edition, 2003. The 8088 and
8086 Microprocessors: Programming, Interfacing, Software, Hardware and
Applications
c. Kip R. Irvine, Prentice Hall, 4th Edition, 2003, Assembly Language for Intel-Based
Computers
d. John Crisp, 2nd Edition, Introduction to Microprocessors and microcontrollers
e. http://www.emu8086.com
f. www.cs.sfu.ca
g. www.wikipedia.com
h. www.microsoft.com
i. www.cs.ucf.edu

Course assessment

Factor Weight Location Date Time

Exercises 10 % In class

Grading Course 5% Assignment 4 Weeks

System Work

Attendance 10 % In class Random

Quizzes 15 % DTBA Date to be Announced 2 Hrs

Final Exam 60 % (TBA) To Be Announced 3 Hrs

(TBA)

Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa,
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Attendance
UMaT rules and regulations say that, attendance is MANDANTORY for every student. A
total of FIVE (5) attendances shall be taken at random to the 10%. The only acceptable
excuse for absence is the one authorized by the Dean of Student on their prescribed form.
However, a student can also ask permission from me to be absent from a particular class with
a tangible reason. A student who misses all the five random attendances marked WOULD
not be allowed to take the final exams

Office Hours

I will be available in my office every Tuesday to answering students’ questions and provide
guidance on any issues related to the course.

Please Note the Following:

 Students must feel free to ask questions in class. Students should not hesitate to email
me with any questions whatsoever.
 Students must endeavour to attend all lectures, lab works and do all their assignments
and coursework.
 Students must be seated and fully prepared for lectures at least 5 minutes before
scheduled time.
 Under no circumstance a student should be late more than 15 minutes after scheduled
time
 NO student shall be admitted into the lecture room more than 15 minutes after the
start of lectures unless pre-approved by me.
 All cell phones, IPods, MP3/MP4s, PDAs etc MUST remain switched off throughout
the lecture period.
 There shall be no eating or gum chewing in class
 Plagiarism shall NOT be accepted in this course so be sure to do your referencing
properly

Thank You

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CHAPTER ONE

1 Overview of Microprocessor Systems and their basic structure

Chapter One Objectives and expected results
Chapter objectives are:

▪ Overview of the Microprocessors;

▪ Examples of microprocessors and hardware and their applications;
▪ Understanding and discussion of the microprocessor basic structure and
design.

At the end of the chapter, students are expected to:

o Understand what the microprocessor looks like;
o Describe the basic functions of the microprocessor;
o Know the various examples of microprocessor trends on the market;
o List and describe the functions of the various components of the microprocessor.
1.2 General Architecture of a Microcomputer System
The hardware of a microcomputer system can be divided into four functional sections:
• the Input device;
• Microprocessing device;
• Memory Unit; and
• Output device.

Figure 1.1 Block Diagram of a Basic Microcomputer

At the heart of every microcomputer is processing unit called a microprocessor or a
microcontroller.

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Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable
of performing ALU (Arithmetic Logical Unit) operations and communicating with the other
devices connected to it.

Microprocessor consists of an ALU, register array, and a control unit. ALU performs
arithmetical and logical operations on the data received from the memory or an input device.

The microprocessor follows a sequence: Fetch, Decode, and then Execute. Initially, the
instructions are stored in the memory in a sequential order. The microprocessor fetches those
instructions from the memory, then decodes it and executes those instructions till STOP
instruction is reached. Later, it sends the result in binary to the output port. Between these
processes, the register stores the temporarily data and ALU performs the computing
functions.

Typically, a microprocessor does not have any RAM, ROM, and I/O on the CPU chip itself.
A typical computer is built around this CPU having the architecture below in figure 1.2.

Figure 1.2 General-purpose microprocessor systems

A microcontroller on the order hand (sometimes abbreviated µC, uC or MCU) is a small

computer on a single integrated circuit containing a processor core, memory, and
programmable input/output peripherals.

Basically, a micro-controller is a device which integrates a number of the components of a

microprocessor system onto a single microchip.

A micro-controller combines onto the same microchip:

• The CPU core;

• Memory (both RAM & ROM);
• Some peripheral digital I/O and more.

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Some characteristic of microcontrollers are as follows:

1. Microcontrollers are "embedded" inside some other device (often a consumer product) so
that they can control the features or actions of the product. Another name for a
microcontroller, therefore, is "embedded controller."

2. Microcontrollers are dedicated to one task and run one specific program. The program is
stored in ROM (read-only memory) and generally does not change.

3. Microcontrollers are often low-power devices. A desktop computer is almost always

plugged into a wall socket and might consume 50 watts of electricity. A battery-operated
microcontroller might consume 50 milli-watts.

4. A microcontroller has a dedicated input device and often (but not always) has a small LED
or LCD display for output. A microcontroller also takes input from the device it is controlling
and controls the device by sending signals to different components in the device. For
example, the microcontroller inside a TV takes input from the remote control and displays
output on the TV screen. The controller controls the channel selector, the speaker system and
certain adjustments on the picture tube electronics such as tint and brightness. The engine
controller in a car takes input from sensors such as the oxygen and knock sensors and
controls things like fuel mix and spark plug timing. A microwave oven controller takes input
from a keypad, displays output on an LCD display and controls a relay that turns the
microwave generator on and off.

5. A microcontroller is often small and low cost. The components are chosen to minimize size
and to be as inexpensive as possible.

6. A microcontroller is often, but not always, ruggedized in some way. The microcontroller
controlling a car's engine, for example, has to work in temperature extremes that a normal
computer generally cannot handle.

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Figure 1.3 illustrates the basic diagram of micro-controller.

Figure 1.3 basic diagram of a microcontroller.

From the figure 1.3, we have got the CPU, Memory (RAM & ROM) and I/O devices all
connected via a bus system. All these things are integrated onto the same silicon real estate so
they are of the same chip itself.

Apart from the CPU, Memory and I/O devices mention above there are other components of
microcontrollers as well and these are:

• Timer module: A timer module allows the micro-controller to perform tasks for
certain time periods. A timer in a typical general-purpose computer is programmed to
work for a certain time period with respect to the system clock and after that typically
a timer can generate an interrupt to the processor so that there can be switching from
one task to another.
• Serial I/O ports: The serial I/O ports allow data flow between the micro-controller
and devices which support serial interfaces.
• Analog to Digital Controllers (ADC): The Analog to Digital Controllers allow the
micro-controller to convert external input which may come in Analog form to the
Digital form for subsequent processing by the microcontroller.
• Digital to Analog Controllers (DAC): This converts the digital signal from the micro-
controller to Analog form to the external world.

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Figure 1.4 shows a detailed block diagram of a microcontrollers.

Figure 1.4 detailed block diagram of a microcontroller.

A microprocessor and a microcontroller are both essentially processors that are designed to
run computers. The type of the computer machinery that the two run is different, though
essentially the main task of both the microprocessor and the microcontroller is the same. Both
are generally termed as the core of any machinery that has a computerized form. One is a
specialized form of processor whereas the other is found in all computers.

The major differences between a microprocessor and a microcontroller are as follows:

Microprocessor Micro-controller

1. CPU on a microprocessor is a stand- 1. CPU, RAM, ROM, I/O and Timer are
alone, with RAM, ROM, I/O and timer all on a single chip.

been separate.
2. Designer can decide on the amount of 2. Has fix amount of on chip ROM, RAM
ROM, RAM and I/O ports and I/O ports
3. Very expensive 3. Low cost, small packaging
4. A microprocessor has more 4. A microcontroller is more specific to
generalized functions its task.
5. A microprocessor may not also be 5. Micro-controllers can be
programmed to handle real-time tasks programmed and reprogrammed
6. Limited I/O capabilities 6. Lots of I/O capabilities
7. Used for general-purpose computers 7. Use for applications in which cost,
power and space are critical
8. High power consumption 8. Low power consumption
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Input and Output units are the means by which the MPU communicates with the outside
world.

• Input unit: keyboard, mouse, scanner, etc.

• Output unit: monitor, printer, etc.

Memory unit:
o Primary: is normally smaller in size and is used for temporary storage of active
information. Typically, ROM and RAM.
o Secondary: is normally larger in size and used for long-term storage of information.
Like Hard disk, Floppy, CD, etc.

1.3 Classification of Microprocessors and Microcontrollers

The microprocessor and microcontrollers are characterized regarding bus-width, instruction
set, and memory structure. For the same family, there may be different forms with different
sources. Over time, five standard bus widths have evolved: 4-bit, 8-bit, 16- bit, 32-bit, 64-bit.

Classification According to Number of Bits

The bits in microprocessor and microcontroller are 8-bits, 16-bits and 32-bits microcontroller.
In an 8-bit microprocessor or microcontroller, the point when the internal bus is 8-bit then the
ALU is performs the arithmetic and logic operations.

The 16-bit microprocessor and microcontroller perform greater precision and performance as
compared to 8-bit. For example, 8-bit microcontrollers can only use 8 bits, resulting in a final
range of 0×00 – 0xFF (0-255) for every cycle. In contrast, 16-bit microcontrollers with its 16-
bit data width has a range of 0×0000 – 0xFFFF (0-65535) for every cycle. A longer timer
most extreme worth can likely prove to be useful in certain applications and circuits. It can
automatically operate on two 16-bit numbers.

The 32-bit microprocessor and microcontroller use the 32-bit instructions to perform the
arithmetic and logic operations. These are used in automatically controlled devices including
implantable medical devices, engine control systems, office machines, appliances and other
types of embedded systems.

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Classification According to Memory Devices

The memory devices are divided into two types, they are:

• Embedded memory;
• External memory.

Embedded memory microcontroller: When an embedded system has a microcontroller unit

that has all the functional blocks available on a chip is called an embedded microcontroller.
For example, 8051 having program & data memory, I/O ports, serial communication,
counters and timers and interrupts on the chip is an embedded microcontroller.

External Memory Microcontroller: When an embedded system has a microcontroller unit that
has not all the functional blocks available on a chip is called an external memory
microcontroller. For example, 8031 has no program memory on the chip is an external
memory microcontroller.

Classification According to Instruction Set

CISC: CISC is a Complex Instruction Set Computer. It allows the programmer to use one
instruction in place of many simpler instructions.

RISC: The RISC is stands for Reduced Instruction set Computer, this type of instruction sets
reduces the design of microprocessor for industry standards. It allows each instruction to
operate on any register or use any addressing mode and simultaneous access of program and
data.

Classification According to Memory Architecture

Memory architecture of microcontroller are two types, they are namely:

• Harvard memory architecture microcontroller;

• Princeton memory architecture microcontroller.

Harvard Memory Architecture Microcontroller: The point when a microprocessor or

microcontroller unit has a dissimilar memory address space for the program and data
memory, the microprocessor or microcontroller has Harvard memory architecture in the
processor.

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Princeton Memory Architecture Microcontroller: The point when a microprocessor or
microcontroller has a common memory address for the program memory and data memory,
the microcontroller has Princeton memory architecture in the processor.

1.4 Types of Microprocessors /Microcontrollers

There are so many manufacturers of Microprocessors, but only two companies have been
produces popular microprocessors: Intel and Motorola. Table 1.1 lists some of types that
belong to these companies (families) of microprocessors.

Table 1.1 Types of microprocessors

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Note that the 8086 has data bus width of 16-bit, and it is able to address 1Megabyte of
memory. It is important to note that 80286, 80386, 80486, and Pentium-Pentium4
microprocessors are upward compatible with the 8086 Architecture. This mean that
8086/8088 code will run on the 80286, 80386, 80486, and Pentium Processors, but the
reverse in not true if any of the new instructions are in use.
Beside these general-purpose microprocessors, there are special-purpose microprocessors
that are used in embedded control applications. This type of embedded microprocessors is
called microcontroller. The 8080, 8051, 8048, 80186, 80C186XL, AVR, PIC are some
examples of microcontrollers.

1.5 Microprocessor and Microcontroller Data sheet descriptions

A typical data sheet of a microprocessor or microcontroller is a literature containing
information on IC packaging, pin diagram, and the function of each IC pin. The architecture
of the CPU is diagrammed, along with a description of the major features. Timing diagrams
appear in the literature along with the processor’s instruction set. The data sheet also
diagrams typical systems using the microprocessor or microcontroller.

The microprocessor is typically housed in a 40-pin dual-in-line package integrated circuit

(40-pin DIP IC). Examples of such packages are illustrated below in figure 1.5.

Figure 1.5a plastic 40-pin DIP microprocessor

Figure 1.5b Ceramic 40-pin DIP microprocessor

A pin diagram, such as the one shown in figure 1.6, is included on microprocessor data
sheets. The manufacturer then details the name and use of each pin on the microprocessor.

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CHAPTER TWO

2 Intel 8085 Microprocessor Architecture and Its Operational Features

Chapter objectives and expected results
The objectives of this chapter are:

o To introduce the Intel 8085 microprocessor;

o To learn about the internal organization and operations of the Intel 8085
microprocessor;
o To know the instruction set and program on the Intel 8085 microprocessor.

At the end of the chapter, students are expected to:

o Understand the operations of the Intel 8085 microprocessor;
o Know the internal organization of the 8085 processor;
o Know how to programme the Intel 8085 microprocessor.

3.1 Intel 8085 Internal Architecture

The Intel 8085 microprocessor is an 8-bit microprocessor designed by Intel in 1977 using
NMOS technology.

It has the following configurations:

1. 8-bit data bus;
2. 16-bit address bus, which can address up to 64KB;
3. A 16-bit program counter;
4. A 16-bit stack pointer;
5. Six 8-bit registers arranged in pairs: BC, DE, HL;
6. Requires +5V supply to operate at 3.2 MHZ single phase clock.

It is used in washing machines, microwave ovens, mobile phones, etc.

3.1.1 Functional Units of Intel 8085 Microprocessor

The Intel 8085 microprocessor consists of the following functional units:

Accumulator: It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.

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Arithmetic and Logic Unit (ALU): As the name suggests, it performs arithmetic and logical
operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.

General Purpose Register: There are 6 general purpose registers in 8085 processor, i.e. B, C,
D, E, H & L. Each register can hold 8-bit data. These registers can work in pair to hold 16-bit
data and their pairing combination is like B-C, D-E & H-L.

Program Counter (PC): It is a 16-bit register used to store the memory address location of
the next instruction to be executed. Microprocessor increments the program whenever an
instruction is being executed, so that the program counter points to the memory address of the
next instruction that is going to be executed.

Stack Pointer: It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.

Temporary Register: It is an 8-bit register, which holds the temporary data of arithmetic and
logical operations.

Flag Register or Status Register: It is an 8-bit register having five 1-bit flip-flops, which
holds either 0 or 1 depending upon the result stored in the accumulator.

These are the set of 5 flip-flops:

1. Sign (S)
2. Zero (Z)
3. Auxiliary Carry (AC)
4. Parity (P)
5. Carry (C)

Its bit position is shown in the following table 1.1

Table 1.1 Flag bit positions

Instruction register and decoder: It is an 8-bit register. When an instruction is fetched from
memory then it is stored in the Instruction register. Instruction decoder decodes the
information present in the Instruction register.
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Timing and control unit: It provides timing and control signal to the microprocessor to
perform operations.

Following are the timing and control signals, which control external and internal circuits −

1. Control Signals: READY, RD’, WR’, ALE

2. Status Signals: S0, S1, IO/M’
3. DMA Signals: HOLD, HLDA
4. RESET Signals: RESET IN, RESET OUT

Interrupt control: As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming request.
After the request is completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessors: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.

Serial Input/output control: It controls the serial data communication by using these two
instructions: SID (Serial input data) and SOD (Serial output data).

Address buffer and address-data buffer: The content stored in the stack pointer and program
counter is loaded into the address buffer and address-data buffer to communicate with the
CPU. The memory and I/O chips are connected to these buses; the CPU can exchange the
desired data with the memory and I/O chips.

Address bus and Data bus: Data bus carries the data to be stored. It is bidirectional, whereas
address bus carries the location to where it should be stored and it is unidirectional. It is used
to transfer the data & Address I/O devices.

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The architecture of 8085 is depicted in figure 2.1:

Figure 2.1 8085 Architecture

3.1.2 Pin Diagram of 8085 Microprocessor

The following image depicts the pin diagram of 8085 Microprocessor.

Figure: Pin Diagram 8085 Architecture

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The pins of an 8085 microprocessor can be classified into seven groups and they are as
follows:

Address bus: A15-A8, it carries the most significant 8-bits of memory/IO address.

Data bus: AD7-AD0, it carries the least significant 8-bit address and data bus.

Control and status signals: These signals are used to identify the nature of operation. There
are 3 control signal and 3 status signals.

Three control signals are RD, WR & ALE.

1. RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
2. WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
3. ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.

Three status signals are IO/M, S0 & S1.

IO/M: This signal is used to differentiate between IO and Memory operations, i.e.
when it is high indicates IO operation and when it is low then it indicates memory
operation.
S1 & S0: These signals are used to identify the type of current operation.

Power supply: There are 2 power supply signals − VCC & VSS. VCC indicates +5v power
supply and VSS indicates ground signal.

Clock signals: There are 3 clock signals, i.e. X1, X2, CLK OUT.

• X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
• CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.

Interrupts & externally initiated signals: Interrupts are the signals generated by external
devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e.
TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
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 • INTA − It is an interrupt acknowledgment signal.
• RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
• RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
• READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
• HOLD − This signal indicates that another master is requesting the use of the address
and data buses.
• HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after
the HOLD signal is removed.

3.1.3 Intel 8085 Addressing modes

Addressing modes are the manner of specifying effective address. These are the instructions
used to transfer the data from one register to another register, from the memory to the
register, and from the register to the memory without any alteration in the content.
Addressing modes in 8085 is classified into 5 groups:

1. Immediate addressing mode: In this mode, the 8/16-bit data is specified in the
instruction itself as one of its operands. For example: MVI K, 20F: means 20F is
copied into register K.
2. Register addressing mode: In this mode, the data is copied from one register to
another. For example: MOV K, B: means data in register B is copied to register K.
3. Direct addressing mode: In this mode, the data is directly copied from the given
address to the register. For example: LDB 5000K: means the data at address 5000K is
copied to register B.
4. Indirect addressing mode: In this mode, the data is transferred from one register to
another by using the address pointed by the register. For example: MOV K, B: means
data is transferred from the memory address pointed by the register to the register K.
5. Implied addressing mode: This mode doesn’t require any operand; the data is
specified by the opcode itself. For example: CMP.

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3.1.4 Interrupts on 8085
Interrupts are the signals generated by the external devices to request the microprocessor
to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and
INTR.

Interrupt are classified into following groups based on their parameter:

• Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
• Non-Vector interrupt − In this type of interrupt, the interrupt address is not
known to the processor so, the interrupt address needs to be sent externally by the
device to perform interrupts. For example: INTR.
• Maskable interrupt − In this type of interrupt, we can disable the interrupt by
writing some instructions into the program. For example: RST7.5, RST6.5,
RST5.5.
• Non-Maskable interrupt − In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the program. For example: TRAP.
• Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.

Note − NTA is not an interrupt, it is used by the microprocessor for sending

acknowledgement. TRAP has the highest priority, then RST7.5 and so on.

Interrupt Service Routine (ISR): A small program or a routine that when executed,
services the corresponding interrupting source is called an ISR.
TRAP: It is a non-maskable interrupt, having the highest priority among all interrupts.
By default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR
and sends the data to backup memory. This interrupt transfers the control to the location
0024H.

RST7.5: It is a maskable interrupt, having the second highest priority among all
interrupts. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 003CH address.

22
 RST 6.5: It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 0034H address.

RST 5.5: It is a maskable interrupt. When this interrupt is executed, the processor saves
the content of the PC register into the stack and branches to 002CH address.

INTR: It is a maskable interrupt, having the lowest priority among all interrupts. It can be
disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur:
1. The microprocessor checks the status of INTR signal during the execution of each
instruction.
2. When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
3. When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.

The Intel 8085 Non-Vectored Interrupt Process:

1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt and
sends INTA (Interrupt acknowledge) signal to the device that interrupted
4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next
instruction on the stack and the program is transferred to ‘call’ location (ISR
Call) specified by the RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt within the
program.
8. RET instruction at the end of the ISR allows the MP to retrieve the return
address from the stack and the program is transferred back to where the
program was interrupted.

23
3.1.5 8085 Instruction Sets
An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions, called the instruction set, determines what
functions the microprocessor can perform.

These instructions can be classified into the following five functional categories: data transfer
(copy) operations, arithmetic operations, logical operations, branching operations, and
machine-control operations.

Data Transfer (Copy) Operations:

The instructions copy data from a location called a source to another location called a
destination, without modifying the contents of the source. In technical manuals, the term data
transfer is used for this copying function. However, the term transfer is misleading; it creates
the impression that the contents of the source are destroyed when, in fact, the contents are
retained without any modification. Following is the table 1.1 showing the list of Data-transfer
instructions with their meanings.

Table 1.1 List Data Transfer Instructions

Opcode Operand Meaning Explanation

This instruction copies the

Copy from the contents of the source

Rd, Sc
source (Sc) to register into the destination
MOV
M, Sc
the destination register without any
Dt, M (Dt) alteration.

Example − MOV K, L

The 8-bit data is stored in

Rd, data Move the destination register or
MVI
immediate 8-bit memory.
M, data
Example − MVI K, 55L

Load the The contents of a memory

LDA 16-bit address
accumulator location, specified by a 16-

24
 bit address in the operand,
are copied to the
accumulator.

Example − LDA 2034K

The contents of the

designated register pair
point to a memory location.
Load the
This instruction copies the
LDAX B/D Reg. pair accumulator
contents of that memory
indirect
location into the
accumulator.

Example − LDAX K

The instruction loads 16-bit

Load the data in the register pair

LXI Reg. pair, 16-bit data register pair designated in the register

immediate or the memory.

Example − LXI K, 3225L

The instruction copies the

contents of the memory
location pointed out by the

Load H and L address into register L and

LHLD 16-bit address
registers direct copies the contents of the
next memory location into
register H.

Example − LHLD 3225K

The contents of the

accumulator are copied into
the memory location
STA 16-bit address 16-bit address
specified by the operand.

This is a 3-byte instruction,

the second byte specifies

25
 the low-order address and
the third byte specifies the
high-order address.

Example − STA 325K

The contents of the

accumulator are copied into
Store the
the memory location
STAX 16-bit address accumulator
specified by the contents of
indirect
the operand.

Example − STAX K

The contents of register L

are stored in the memory
location specified by the
16-bit address in the
operand and the contents
of H register are stored into
the next memory location
Store H and L by incrementing the
SHLD 16-bit address
registers direct operand.

This is a 3-byte instruction,

the second byte specifies
the low-order address and
the third byte specifies the
high-order address.

Example − SHLD 3225K

The contents of register H

are exchanged with the
Exchange H
contents of register D, and
XCHG None and L with D
the contents of register L
and E
are exchanged with the
contents of register E.

26
 Example − XCHG

The instruction loads the

contents of the H and L
registers into the stack
pointer register. The
Copy H and L
contents of the H register
SPHL None registers to the
provide the high-order
stack pointer
address and the contents
of the L register provide
the low-order address.

Example − SPHL

The contents of the L

register are exchanged
with the stack location
pointed out by the contents
of the stack pointer
Exchange H
register.
XTHL None and L with top
of stack The contents of the H
register are exchanged
with the next stack location
(SP+1).

Example − XTHL

The contents of the register

pair designated in the
operand are copied onto
the stack in the following
Push the
sequence.
PUSH Reg. pair register pair
The stack pointer register
onto the stack
is decremented and the
contents of the high order
register (B, D, H, A) are
copied into that location.

27
 The stack pointer register
is decremented again and
the contents of the low-
order register (C, E, L,
flags) are copied to that
location.

Example − PUSH K

The contents of the

memory location pointed
out by the stack pointer
register are copied to the
low-order register (C, E, L,
status flags) of the
operand.

Pop off stack to The stack pointer is

POP Reg. pair
the register pair incremented by 1 and the
contents of that memory
location are copied to the
high-order register (B, D,
H, A) of the operand.

The stack pointer register

is again incremented by 1.

Example – POP K

Output the data The contents of the

from the accumulator are copied into

OUT 8-bit port address accumulator to the I/O port specified by

a port with 8bit the operand.

address Example − OUT K9L

Input data to The contents of the input

accumulator port designated in the
IN 8-bit port address
from a port operand are read and
with 8-bit loaded into the

28
 address accumulator.

Example – IN 5KL

Arithmetic Operations:

These instructions perform arithmetic operations such as addition, subtraction, increment, and
decrement.

• Addition - Any 8-bit number, or the contents of a register or the contents of a

memory location can be added to the contents of the accumulator and the sum is
stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the
contents of register B cannot be added directly to the contents of the register C). The
instruction DAD is an exception; it adds 16-bit data directly in register pairs.
• Subtraction - Any 8-bit number, or the contents of a register, or the contents of a
memory location can be subtracted from the contents of the accumulator and the
results stored in the accumulator. The subtraction is performed in 2's compliment, and
the results if negative, are expressed in 2's complement. No two other registers can be
subtracted directly.
• Increment/Decrement - The 8-bit contents of a register or a memory location can be
incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such
as BC) can be incremented or decrement by 1. These increment and decrement
operations differ from addition and subtraction in an important way; i.e., they can be
performed in any one of the registers or in a memory location.

Following is the table 1.2 showing the list of Arithmetic instructions with their meanings.

Table 1.2 List Arithmetic Instructions

Opcode Operand Meaning Explanation

The contents of the register

Add register or
R
or memory are added to
ADD memory, to the
M the contents of the
accumulator
accumulator and the result

29
 is stored in the
accumulator.

Example − ADD K.

The contents of the register

or memory & M the Carry
flag are added to the
Add register to
R contents of the
ADC the accumulator
accumulator and the result
M
with carry
is stored in the
accumulator.

Example − ADC K

The 8-bit data is added to

the contents of the
Add the
accumulator and the result
ADI 8-bit data immediate to
is stored in the
the accumulator
accumulator.

Example − ADI 55K

The 8-bit data and the

Carry flag are added to the
Add the
contents of the
immediate to
ACI 8-bit data accumulator and the result
the accumulator
is stored in the
with carry
accumulator.

Example − ACI 55K

The instruction stores 16-

Load the bit data into the register

LXI Reg. pair, 16bit data register pair pair designated in the

immediate operand.

Example − LXI K, 3025M

30
 The 16-bit data of the

Add the register specified register pair are

DAD Reg. pair pair to H and L added to the contents of

registers the HL register.

Example − DAD K

The contents of the register

or the memory are

Subtract the subtracted from the

R register or the contents of the
SUB
memory from accumulator, and the result
M
the accumulator is stored in the
accumulator.

Example − SUB K

The contents of the register

or the memory & M the

Subtract the Borrow flag are subtracted

R source and from the contents of the
SBB
borrow from the accumulator and the result
M
accumulator is placed in the
accumulator.

Example − SBB K

The 8-bit data is subtracted

Subtract the from the contents of the

SUI 8-bit data immediate from accumulator & the result is

the accumulator stored in the accumulator.

Example − SUI 55K

The contents of register H

Subtract the
are exchanged with the
immediate from
SBI 8-bit data contents of register D, and
the accumulator
the contents of register L
with borrow
are exchanged with the

31
 contents of register E.

Example − XCHG

The contents of the

designated register or the
Increment the
R memory are incremented
INR register or the
by 1 and their result is
M
memory by 1
stored at the same place.

Example − INR K

The contents of the

designated register pair are
Increment
incremented by 1 and their
INX R register pair by
result is stored at the same
1
place.

Example − INX K

The contents of the

designated register or
Decrement the
R memory are decremented
DCR register or the
by 1 and their result is
M
memory by 1
stored at the same place.

Example − DCR K

The contents of the

designated register pair are
Decrement the
decremented by 1 and their
DCX R register pair by
result is stored at the same
1
place.

Example − DCX K

The contents of the

Decimal adjust
DAA None accumulator are changed
accumulator
from a binary value to two

32
 4-bit BCD digits.

If the value of the low-

order 4-bits in the
accumulator is greater than
9 or if AC flag is set, the
instruction adds 6 to the
low-order four bits.

If the value of the high-

order 4-bits in the
accumulator is greater than
9 or if the Carry flag is set,
the instruction adds 6 to
the high-order four bits.

Example − DAA

Logical Operations:

These instructions perform various logical operations with the contents of the accumulator.

• AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of a

memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents
of the accumulator. The results are stored in the accumulator.
• Rotate- Each bit in the accumulator can be shifted either left or right to the next
position.
• Compare- Any 8-bit number or the contents of a register, or a memory location can
be compared for equality, greater than, or less than, with the contents of the
accumulator.
• Complement - The contents of the accumulator can be complemented. All 0s are
replaced by 1s and all 1s are replaced by 0s.

The following table 1. 3 shows the list of Logical instructions with their meanings.

33
Table 1.3 List of Logical Instructions

Opcode Operand Meaning Explanation

Compare the
R The contents of the operand (register
CMP register or
or memory) are M compared with the
M memory with the
contents of the accumulator.
accumulator

Compare
The second byte data is compared with
CPI 8-bit data immediate with
the contents of the accumulator.
the accumulator

Logical AND The contents of the accumulator are

R
register or logically AND with M the contents of the
ANA
M memory with the register or memory, and the result is
accumulator placed in the accumulator.

Logical AND The contents of the accumulator are

ANI 8-bit data immediate with logically AND with the 8-bit data and
the accumulator the result is placed in the accumulator.

Exclusive OR The contents of the accumulator are

R
register or Exclusive OR with M the contents of the
XRA
memory with the register or memory, and the result is
M
accumulator placed in the accumulator.

Exclusive OR The contents of the accumulator are

XRI 8-bit data immediate with Exclusive OR with the 8-bit data and
the accumulator the result is placed in the accumulator.

Logical OR The contents of the accumulator are

R
register or logically OR with M the contents of the
ORA
M memory with the register or memory, and result is
accumulator placed in the accumulator.

Logical OR The contents of the accumulator are

ORI 8-bit data immediate with logically OR with the 8-bit data and the
the accumulator result is placed in the accumulator.

Each binary bit of the accumulator is

rotated left by one position. Bit D7 is
Rotate the
RLC None placed in the position of D0 as well as
accumulator left
in the Carry flag. CY is modified
according to bit D7.

Each binary bit of the accumulator is

rotated right by one position. Bit D0 is
Rotate the
RRC None placed in the position of D7 as well as
accumulator right
in the Carry flag. CY is modified
according to bit D0.

34
 Each binary bit of the accumulator is
rotated left by one position through the
Rotate the
Carry flag. Bit D7 is placed in the Carry
RAL None accumulator left
flag, and the Carry flag is placed in the
through carry
least significant position D0. CY is
modified according to bit D7.

Each binary bit of the accumulator is

rotated right by one position through
Rotate the
the Carry flag. Bit D0 is placed in the
RAR None accumulator right
Carry flag, and the Carry flag is placed
through carry
in the most significant position D7. CY
is modified according to bit D0.

Complement The contents of the accumulator are

CMA None
accumulator complemented. No flags are affected.

Complement The Carry flag is complemented. No

CMC None
carry other flags are affected.

STC None Set Carry Set Carry

Branching Operations:

This group of instructions alters the sequence of program execution either conditionally or
unconditionally.

• Jump - Conditional jumps are an important aspect of the decision-making process in

the programming. These instructions test for a certain condition (e.g., Zero or Carry
flag) and alter the program sequence when the condition is met. In addition, the
instruction set includes an instruction called unconditional jump.
• Call, Return, and Restart - These instructions change the sequence of a program
either by calling a subroutine or returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.

The following table 1.4 shows the list of Branching instructions with their meanings.

Table 1.4 List of Branch Instructions

Opcode Operand Meaning Explanation

JMP The program sequence

16-bit Jump is transferred to the

35
 address unconditionally memory address given
in the operand.

Opcode Description Flag

Status

Jump on
JC CY=1
Carry

Jump on no
JNC CY=0
Carry

Jump on
JP S=0
positive
The program sequence
is transferred to the
Jump on 16-bit Jump memory address given
JM S=1 address conditionally in the operand based on
minus
the specified flag of the
PSW.

Jump on
JZ Z=1
zero

Jump on no
JNZ Z=0
zero

Jump on
JPE P=1
parity even

Jump on
JPO P=0
parity odd

The program sequence

Opcode Description Flag is transferred to the
Status memory address given
16-bit Unconditional in the operand. Before
address subroutine call transferring, the address
Call on of the next instruction
CC CY=1 after CALL is pushed
Carry onto the stack.

36
 Call on no
CNC CY=0
Carry

Call on
CP S=0
positive

Call on
CM S=1
minus

Call on
CZ Z=1
zero

Call on no
CNZ Z=0
zero

Call on
CPE P=1
parity even

Call on
CPO P=0
parity odd

The program sequence

Return from
is transferred from the
RET None subroutine
subroutine to the calling
unconditionally
program.

Opcode Description Flag

Status
The program sequence
is transferred from the
subroutine to the calling
Return from
Return on program based on the
RC CY=1 None subroutine
Carry specified flag of the PSW
conditionally
and the program
execution begins at the
new address.
Return on
RNC CY=0
no Carry

37
 Return on
RP S=0
positive

Return on
RM S=1
minus

Return on
RZ Z=1
zero

Return on
RNZ Z=0
no zero

Return on
RPE P=1
parity even

Return on
RPO P=0
parity odd

The contents of registers

H & L are copied into the
Load the
program counter. The
program
PCHL None contents of H are placed
counter with
as the high-order byte
HL contents
and the contents of L as
the low order byte.

The RST instruction is

used as software
instructions in a
program to transfer the
program execution to
one of the following
eight locations.
RST 0-7 Restart

Instruction Restart
Address

RST 0 0000H

38
 RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

The 8085 has

additionally 4 interrupts,
which can generate RST
instructions internally
and doesn’t require any
external hardware.
Following are those
instructions and their
Restart addresses −

Interrupt Restart
Address

TRAP 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

39
Machine Control Operations:

These instructions control machine functions such as Halt, Interrupt, or do nothing. The
microprocessor operations related to data manipulation can be summarized in four functions:

2. copying data
3. performing arithmetic operations
4. performing logical operations
5. testing for a given condition and alerting the program sequence

Some important aspects of the instruction set are noted below:

1. In data transfer, the contents of the source are not destroyed; only the contents of the
destination are changed. The data copy instructions do not affect the flags.
2. Arithmetic and Logical operations are performed with the contents of the
accumulator, and the results are stored in the accumulator (with some expectations).
The flags are affected according to the results.
3. Any register including the memory can be used for increment and decrement.
4. A program sequence can be changed either conditionally or by testing for a given
data condition.

Following is the table 1.5 showing the list of Control instructions with their meanings.

Table 1.5 Control Instructions

Opcode Operand Meaning Explanation

NOP None No operation No operation is
performed, i.e., the
instruction is fetched
and decoded.
HLT None Halt and enter wait The CPU finishes
state executing the current
instruction and stops
further execution. An
interrupt or reset is
necessary to exit
from the halt state.
DI None Disable interrupts The interrupt enable
flip-flop is reset and
all the interrupts are
disabled except
TRAP.
EI None Enable interrupts The interrupt enable
40
 flip-flop is set and all
the interrupts are
enabled.
RIM None Read interrupt mask This instruction is
used to read the
status of interrupts
7.5, 6.5, 5.5 and read
serial data input bit.
SIM None Set interrupt mask This instruction is
used to implement
the interrupts 7.5,
6.5, 5.5, and serial
data output.

3.1.6 Instruction Format

An instruction has two parts: one is task to be performed, called the operation code
(Opcode), and the second is the data to be operated on, called the operand. The operand (or
data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal
register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is
implicit.

Instruction word size

The 8085-instruction set is classified into the following three groups according to word size:

1. One-word or 1-byte instructions;

2. Two-word or 2-byte instructions;
3. Three-word or 3-byte instructions.

One-Byte Instructions

A 1-byte instruction includes the Opcode and operand in the same byte. Operand(s) are
internal register and are coded into the instruction.

For example:

Task Opcode Operand Binary Hex code

code
Copy the contents of the accumulator MOV C, A 0100 1111 4FH
in the register C.

41
Add the contents of register B to the ADD B 1000 0000 80H
contents of the accumulator.
Invert (compliment) each bit in the CMA 0010 1111 2FH
accumulator.

These instructions are stored in 8- bit binary format in memory; each requires one memory
location.

MOV Rd, Rs;

Rd <-- Rs copies contents of Rs into Rd.

Example: MOV A, B

ADD R

A <-- A + R

Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second byte
specifies the operand. Source operand is a data byte immediately following the Opcode. For
example:

Task Opcode Operand Binary Hex Code

Code
Load an 8-bit data byte in MVI A, Data 0011 1110 3E First Byte
the accumulator. Data Second Byte
DATA

Assume that the data byte is 32H. The assembly language instruction is written as

Mnemonics Hex code

MVI A, 32H 3E 32H

The instruction would require two memory locations to store in memory.

MVI R, data
42
R<-- data

Example: MVI A, 30H coded as 3EH 30H as two contiguous bytes. This is an example of
immediate addressing.

ADI data

A <-- A + data

OUT port where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data
but points directly to where it is located this is called direct addressing.

Three-Byte Instructions

In a three-byte instruction, the first byte specifies the Opcode, and the following two bytes
specify the 16-bit address. Note that the second byte is the low-order address and the third
byte is the high-order address.

Opcode + data byte + data byte

For example:

Task Opcode Operand Binary code Hex

code
Transfer the JMP 2085H
program 1100 0011 C3 First byte
sequence to
the memory 1000 0101 85 Second Byte
location
2085H. 0010 0000 20 Third Byte

This instruction would require three memory locations to store in memory. Three-byte
instructions - Opcode + data byte + data byte

LXI Rp, data16

43
Rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data bytes are
16-bit data in L H order of significance.

Rp <-- data16

Example:

LXI H, 0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.

LDA addr

A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H
21H. This is also an example of direct addressing.

CHAPTER THREE

3. Intel 8086 Microprocessor Architecture

Chapter objectives and expected results
The objectives of this chapter are:

o To study about the architecture of 8086/8088;

o To study about the segment registers and memory addressing of 8086/8088;
o To learn the various addressing modes supported by 8086/8088;
o To study the various types of instructions provided by 8086/8088;
o To study the pin diagram and the signals of various pins of 8086/8088.

At the end of the chapter, students are expected to:

o Understand the operations of the Intel 8086/8088 microprocessor;

o Know the internal organization of the 8086/8088 processor;
o Know how to programme the Intel 8086/8088 microprocessor.

3.1 Intel 8086 Microprocessor Architecture and Operational Functions

The Intel 8086 Microprocessor is an enhanced version of 8085Microprocessor that was
designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data
lines that provides up to 1MB storage. It consists of powerful instruction set, which provides
operations like multiplication and division easily.

44
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum
mode is suitable for system having multiple processors and Minimum mode is suitable for
system having a single processor.

3.2 Features of Intel 8086

The most prominent features of the Intel 8086 microprocessor are as follows:

1. It has an instruction queue, which is capable of storing six instruction bytes from the
memory resulting in faster processing.

2. It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus,
and 16-bit external data bus resulting in faster processing.

3. It is available in 3 versions based on the frequency of operation:

o 8086 → 5MHz

o 8086-2 → 8MHz

o (c)8086-1 → 10 MHz

4. It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.

5. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.

6. Execute stage executes these instructions.

7. It has 256 vectored interrupts.

8. It consists of 29,000 transistors.

The comparison between 8085 & 8086 Microprocessor are as follows:

• Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

• Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.

• Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of

memory.

• Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an

instruction queue.

45
 • Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a
pipelined architecture.

• I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536
I/O's.

• Cost − The cost of 8085 is low whereas that of 8086 is high.

3.3 Architecture of Intel 8086

The figure 3.1 depicts the architecture of a 8086 Microprocessor

Figure 3.1 Detailed Architecture of 8086 Microprocessor

The Intel 8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)
and BIU (Bus Interface Unit).

The Execution Unit (EU)

46
The Execution Unit (EU) of 8086 microprocessor has control unit, instruction decoder,
Arithmetic and Logical Unit (ALU), general registers, flag register, pointers and index
registers.

Control unit is responsible for the co-ordination of all other units of the processor. It
generates timing and control signals which are necessary for the execution of instructions. It
controls the data flow between CPU and peripherals (including memory). It provides status,
control and timing signals which are required for the operation of memory and I/O devices. It
directs the internal operations of the processor. In short, we can say that it controls the entire
operations of the microprocessor and peripherals connected to the microprocessor. Hence you
can understand that control unit is like the brain of an 8086 based microcomputer system.

The EU of 8086 has a 16-bit ALU. ALU performs various arithmetic and logical operations
over the data. It takes care of all manipulations required over the data to produce the required
output. Some frequently performed operations are addition, subtraction, logical AND, logical
OR, logical XOR, complement, left shift, right shift etc.

The instruction decoder translates the instructions fetched from the memory into a series of
actions that are carried out by the EU. Instruction decoding is the process of segregating the
instruction into opcode and operands.

Registers:

Various registers present in the EU can be divided into three categories namely:

• General registers;
• Flag register and
• Pointers and index register.

General Registers

General registers are used for temporary storage and manipulation of data and instructions.
Data remain in the registers till they are sent to the memory or I/O devices. The various
general registers are shown in figure 3.2.

47
 Figure 3.2 General registers of 8086

Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL contains the low-order byte of the word, and
AH contains the high-order byte. Accumulator can be used for I/O operations and string
manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL contains the low-order byte of the word, and BH contains
the high-order byte. BX register usually contains a data pointer used for based, based indexed
or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined together
and used as a 16-bit register CX. When combined, CL register contains the low-order byte of
the word, and CH contains the high-order byte. Count register can be used as a counter in
string manipulation and shift/rotate instructions.

Data register consists of two 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains high-
order word of the initial or resulting number.

Flag Register

This register is a 16-bit register containing a collection of 9 flags as shown in figure 4.4. Each
of these flip flops holds 1-bit flag that indicates certain conditions which arises during
arithmetic and logic operations.

48
 Figure 3.3 Flag Register of 8086

The meanings of each flag are shown as follows:

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.

Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables Maskable interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero.

Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is
even.

Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during
last result calculation.

Since flag register reflects the happenings inside the 8086 microprocessors, it is called the
Program Status Word (PSW). The contents of PSW, accumulator and other registers are
saved in the stack during the handling of interrupt. Flag registers can be summarized as
follows.

49
Pointers and Index registers

Pointer registers are used to point to a particular location either in memory or stack from
which the data is to be read or to which the data is to be written.

Index registers are useful in implementing sophisticated addressing modes (identifying the
location of the operands). The EU of 8086 has the set of pointers and index registers as
shown in figure 3.4

Figure 3.4 Pointers and Index registers of 8086

The functions of pointers and index registers are explained as follows:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.

50
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data addresses in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data addresses in string manipulation instructions.

Bus Interface Unit (BIU)

BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the
memory as well as writing data to the ports and the memory. EU has no direction connection
with System Buses so this is possible with the BIU. EU and BIU are connected with the
Internal Bus.

It has the following functional parts:

• Instruction queue − BIU contains the instruction queue. BIU gets up to 6 bytes of
next instructions and stores them in the instruction queue. When EU executes
instructions and is ready for its next instruction, then it simply reads the instruction
from this instruction queue resulting in increased execution speed.

• Fetching the next instruction while the current instruction executes is

called pipelining.

• Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor to
access memory locations. It also contains 1 pointer register IP, which holds the
address of the next instruction to executed by the EU.

o CS − It stands for Code Segment. It is used for addressing a memory location

in the code segment of the memory, where the executable program is stored.

o DS − It stands for Data Segment. It consists of data used by the program and
is accessed in the data segment by an offset address or the content of other
register that holds the offset address.

o SS − It stands for Stack Segment. It handles memory to store data and

addresses during execution.

51
 o ES − It stands for Extra Segment. ES is additional data segment, which is
used by the string to hold the extra destination data.

• Instruction pointer − It is a 16-bit register used to hold the address of the next
instruction to be executed.

How to calculate Absolute Address or Effective Address (Physical Address):

The value in any register considered being a Segment register is multiplied by 16 (or shifted
one hexadecimal byte to the left; add an extra 0 to the end of the hex number) and then the
value in an Offset register is added to it. So, the Absolute address for any combination of
Segment and Offset pairs is found by using the formula

Physical Memory Location = (Segment value * 16) + Offset Value

Examples.

1. The Absolute or Linear address for the Segment: Offset pair, F000:FFFD can be computed
quite easily in your mind by simply inserting a zero at the end of the Segment value (which is
the same as multiplying by 16 ) and then adding the Offset value:

F0000

+ FFFD

------

FFFFD or 1,048,573(decimal)

2. Calculate effective address given 923F:E2FF ->

923F0

+ E2FF

------

A06EF or 657,135(decimal)

If we compute the Absolute Memory location for the largest value that can be expressed
using a Segment: Offset reference:
52
 FFFF0

+ FFFF

-------

10FFEF or 1,114,095 (decimal)

In reality, it wasn't until quite some time after the 8086, that such a large value actually
corresponded to a real Memory location. Once it became common for PCs to have over 1MB
of memory, programmers developed ways to use it to their advantage and this last byte
became part of what's now called the HMA (High Memory Area). But until that time, if a
program tried to use a Segment: Offset pair that exceeded a 20-bit Absolute address (1MB),
the CPU would truncate the higher bits, effectively mapping any value over FFFFFh
(1,048,575) to an address within the first Segment. Thus, 10FFEFh was mapped to FFFEh.

One of the downsides in using Segment: Offset pairs is the fact that a large number of these
pairs refer to the same exact memory locations. For example, every Segment: Offset pair
below, refers to exactly the same location in memory:

0007:7B90 0008:7B80 0009:7B70 000A:7B60 000B:7B50 000C:7B40

0047:7790 0048:7780 0049:7770 004A:7760 004B:7750 004C:7740

0077:7490 0078:7480 0079:7470 007A:7460 007B:7450 007C:7440

01FF:5C10 0200:5C00 0201:5BF0 0202:5BE0 0203:5BD0 0204:5BC0

07BB:0050 07BC:0040 07BD:0030 07BE:0020 07BF:0010 07C0:0000

All the above Segment: Offset pairs are only some of the many ways to refer to the single
absolute memory location of 7C00h.

As a matter of fact, there may be up to 4096 different Segment: Offset pairs for addressing a
single byte in Memory; depending upon its particular location. For absolute addresses 0h
through FFEFh (o through 65,519), the number of different pairs can be computed as follows:

• Divide the absolute address by 16 (which shifts all the hex digits one place to the
right)
• Throw away any fractional remainder and add 1

53
This is the same thing as saying: Add 1 to the segment number if the offset is 000Fh (15) or
less. For example, the byte in memory referenced by the Segment: Offset pair 0040:0000 has
a total of 41h (or 65) different pairs that might be used. For the Absolute address 7C00h,
which was mentioned above, there's a total of: 7C00 / 10h --> 7C0 + 1 = 7C1 (or 1,985)
relative ways to address this same memory location using Segment: Offset pairs. For the
absolute addresses from FFF0h (65,520) all the way through FFFFFh (1,048,575), there will
always be 4,096 Segment: Offset pairs one could use to refer to these addresses. That's a little
over 88% of the memory that can be accessed using Segment: Offsets. The last 65,520 bytes
that can be accessed by this method are collectively called the High Memory Area (HMA).
For each 16 bytes higher in the HMA that we point to, there is one less Segment: Offset pair
available to reference that paragraph.

Since BIU takes care of the interaction with memory and other peripherals EU is able to
concentrate in the processing of data. Moreover, the maintenance of the instruction queue
enables the 8086-microprocessor unit (MPU) to achieve pipelining. Overall, the performance
of 8086 is improved considerably.

3.4 Intel 8086 Pin Diagram and Functions

The Intel 8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline
Package) chip. Figure 3.5 shows the pin configuration of the 8086 Microprocessor.

Figure 3.5 Pin diagram of 8086

54
Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus

AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.

Address/status bus

A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries
4-bit address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.

Read ($\overline {RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.

RESET

It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

INTR

It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.
55
NMI

It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.

$\overline {TEST}$

This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/$\overline {MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.

INTA

It is an interrupt acknowledgement signal and id available at pin 24. When the

microprocessor receives this signal, it acknowledges the interrupt.

ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The Transreceiver is a device used to separate data from the address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction
of data flow through the Transreceiver. When it is high, data is transmitted out and vice-a-
versa.

M/IO

This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.

WR

It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
56
HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD

This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table.

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,
and 28. Following is the table showing their status.

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

57
 0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin
29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.

3.5 Intel 8086 Instruction Set

The 8086 microprocessor supports 8 types of instructions −

• Data Transfer Instructions

• Arithmetic Instructions
• Bit Manipulation Instructions
• String Instructions
• Program Execution Transfer Instructions (Branch & Loop Instructions)
58
 • Processor Control Instructions
• Iteration Control Instructions
• Interrupt Instructions

Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group:

Instruction to transfer a word

• MOV − Used to copy the byte or word from the provided source to the provided
destination.

• PPUSH − Used to put a word at the top of the stack.

• POP − Used to get a word from the top of the stack to the provided location.

• PUSHA − Used to put all the registers into the stack.

• POPA − Used to get words from the stack to all registers.

• XCHG − Used to exchange the data from two locations.

• XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

• IN − Used to read a byte or word from the provided port to the accumulator.

• OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

• LEA − Used to load the address of operand into the provided register.

• LDS − Used to load DS register and other provided register from the memory

• LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

• LAHF − Used to load AH with the low byte of the flag register.

• SAHF − Used to store AH register to low byte of the flag register.

• PUSHF − Used to copy the flag register at the top of the stack.

• POPF − Used to copy a word at the top of the stack to the flag register.

59
Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.

Following is the list of instructions under this group:

Instructions to perform addition

• ADD − Used to add the provided byte to byte/word to word.

• ADC − Used to add with carry.

• INC − Used to increment the provided byte/word by 1.

• AAA − Used to adjust ASCII after addition.

• DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

• SUB − Used to subtract the byte from byte/word from word.

• SBB − Used to perform subtraction with borrow.

• DEC − Used to decrement the provided byte/word by 1.

• NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.

• CMP − Used to compare 2 provided byte/word.

• AAS − Used to adjust ASCII codes after subtraction.

• DAS − Used to adjust decimal after subtraction.

• Instruction to perform multiplication

• MUL − Used to multiply unsigned byte by byte/word by word.

• IMUL − Used to multiply signed byte by byte/word by word.

• AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

• DIV − Used to divide the unsigned word by byte or unsigned double word by word.

• IDIV − Used to divide the signed word by byte or signed double word by word.

• AAD − Used to adjust ASCII codes after division.

• CBW − Used to fill the upper byte of the word with the copies of sign bit of the
lower byte.
60
 • CWD − Used to fill the upper word of the double word with the sign bit of the lower
word.
Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e.
operations like logical, shift, etc.

Following is the list of instructions under this group:

Instructions to perform logical operation

• NOT − Used to invert each bit of a byte or word.

• AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.

• OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.

• XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with
the corresponding bit in another byte/word.

• TEST − Used to add operands to update flags, without affecting operands.

Instructions to perform shift operations

• SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.

• SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.

• SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into
the new MSB.
Instructions to perform rotate operations

• ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to
Carry Flag [CF].

• ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to
Carry Flag [CF].

• RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.

• RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to
LSB.

61
String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.

Following is the list of instructions under this group:

• REP − Used to repeat the given instruction till CX ≠ 0.

• REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

• REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF

= 1.

• MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to

another.

• COMS/COMPSB/COMPSW − Used to compare two string bytes/words.

• INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the

provided memory location.

• OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided

memory location to the I/O port.

• SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in
AL or string word with a word in AX.

• LODS/LODSB/LODSW − Used to store the string byte into AL or string word into
AX.
Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It

includes the following instructions −

Instructions to transfer the instruction during an execution without any condition −

• CALL − Used to call a procedure and save their return address to the stack.

• RET − Used to return from the procedure to the main program.

• JMP − Used to jump to the provided address to proceed to the next instruction.

Instructions to transfer the instruction during an execution with some conditions −

• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

• JAE/JNB − Used to jump if above/not below instruction satisfies.

• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.

62
 • JC − Used to jump if carry flag CF = 1

• JE/JZ − Used to jump if equal/zero flag ZF = 1

• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.

• JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.

• JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.

• JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.

• JNC − Used to jump if no carry flag (CF = 0)

• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0

• JNO − Used to jump if no overflow flag OF = 0

• JNP/JPO − Used to jump if not parity/parity odd PF = 0

• JNS − Used to jump if not sign SF = 0

• JO − Used to jump if overflow flag OF = 1

• JP/JPE − Used to jump if parity/parity even PF = 1

• JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag
values.

Following are the instructions under this group:

• STC − Used to set carry flag CF to 1

• CLC − Used to clear/reset carry flag CF to 0

• CMC − Used to put complement at the state of carry flag CF.

• STD − Used to set the direction flag DF to 1

• CLD − Used to clear/reset the direction flag DF to 0

• STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.

• CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following
is the list of instructions under this group −
63
 • LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX =
0

• LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX

=0

• LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 &

CX = 0

• JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions

These instructions are used to call the interrupt during program execution.

• INT − Used to interrupt the program during execution and calling service specified.

• INTO − Used to interrupt the program during execution if OF = 1

• IRET − Used to return from interrupt service to the main program

3. 6 Intel 8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that
interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the
microprocessor on how to handle the interrupt. The figure 3.6 shows the types of interrupts
we have in the 8086 microprocessors.

Figure 3.6 8086 Interrupts

Hardware Interrupts

Hardware interrupt is caused by any peripheral device by sending a signal through a

specified pin to the microprocessor.

64
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.
NMI

It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these actions take place:

• Completes the current instruction that is in progress.

• Pushes the Flag register values on to the stack.

• Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.

• IP is loaded from the contents of the word location 00008H.

• CS is loaded from the contents of the next word location 0000AH.

• Interrupt flag and trap flag are reset to 0.

INTR

The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends ‘0’ on
INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bits, say X, from the programmable
interrupt controller.

These actions are taken by the microprocessor:

• First completes the current instruction.

• Activates INTA output and receives the interrupt type, say X.

• Flag register value, CS value of the return address and IP value of the return address
are pushed on to the stack.

• IP value is loaded from the contents of word location X × 4

• CS is loaded from the contents of the next word location.

65
 • Interrupt flag and trap flag is reset to 0

Software Interrupts

Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes:

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.

Its execution includes the following steps:

• Flag register value is pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the
stack.

• IP is loaded from the contents of the word location ‘type number’ × 4

• CS is loaded from the contents of the next word location.

• Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly
for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers.
i.e.

• TYPE 0 interrupt represents division by zero situation.

• TYPE 1 interrupt represents single-step execution during the debugging of a

program.

• TYPE 2 interrupt represents non-maskable NMI interrupt.

• TYPE 3 interrupt represents break-point interrupt.

• TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.

INT 3-Break Point Interrupt Instruction

66
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution of
program and follows the break-point procedure.

Its execution includes the following steps −

• Flag register value is pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the
stack.

• IP is loaded from the contents of the word location 3×4 = 0000CH

• CS is loaded from the contents of the next word location.

• Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is
4. If the overflow flag is reset then, the execution continues to the next instruction.

Its execution includes the following steps:

• Flag register values are pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the
stack.

• IP is loaded from the contents of word location 4×4 = 00010H

• CS is loaded from the contents of the next word location.

• Interrupt flag and Trap flag are reset to 0

3.7 Intel 8086 Addressing Modes
The different ways in which a source operand is denoted in an instruction is known
as addressing modes. There are 8 different addressing modes in 8086 programming.

Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as
immediate addressing mode.

Example

67
MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH

Register addressing mode

It means that the register is the source of an operand for an instruction.

Example

MOV CX, AX; copies the contents of the 16-bit AX register into
; the 16-bit CX register),
ADD BX, AX

Direct addressing mode

The addressing mode in which the effective address of the memory location is written
directly in the instruction.

Example

MOV AX, [1592H], MOV AL, [0300H]

Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset
address held in any of the following registers: BP, BX, DI & SI.

Example

MOV AX, [BX]; Suppose the register BX contains 4895H, then the contents
; 4895H are moved to AX
ADD CX, {BX}

Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents of
the BX/BP registers and 8-bit/16-bit displacement.

Example

MOV DX, [BX+04], ADD CL, [BX+08]

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Indexed addressing mode
In this addressing mode, the operands offset address is found by adding the contents of SI or
DI register and 8-bit/16-bit displacements.

Example

MOV BX, [SI+16], ADD AL, [DI+16]

Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base
register to the contents of an Index register.

Example

ADD CX, [AX+SI], MOV AX, [AX+DI]

Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base register
contents. An Index registers contents and 8 or 16-bit displacement.

Example

MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

3.8 Memory address space and data organization

Intel 8086 can support 1Mbyte of external memory that organized as individual bytes of data
stored at consecutive addresses over the address range 0000016 to FFFFF16. The 8086 can
access any two consecutive bytes as a word of data. The lower-addressed byte is the least
significant byte of the word, and the higher- addressed byte is its most significant byte.

The word of data is at an even-address boundary if its least significant byte is in even
address. It’s also called aligned word. The word of data is at an odd-address boundary if its
least significant byte is in odd address. It’s also called misaligned word, as shown in Figure
3.7.

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 Figure 3.7 Aligned and misaligned

To store double word four locations are needed. The double word that it’s least significant
byte store at an address that is a multiple of 4 (e.g. 016, 416, 816 ...) as shown in Figure 3.8.

Figure 3.8 Aligned and misaligned

Even though the 8086 has a 1Mbyte address space, not all this memory is active at one time.
Actually, the 1Mbytes of memory are partitioned into 64Kbyte (65,536) segments. Each
segment is assigned a Base Address that identifies its starting point (identify its lowest
address byte-storage location).

Only four of these 64Kbyte segments are active at a time: the code segment, stack segment,
data segment, and extra segment. The addresses of these four segments are held in four
segment registers: CS (code segment), SS (stack segment), DS (data segment), and ES (extra
segment). These registers contain a 16-bit base address that points to the lowest addressed
byte of the segment (see Figure 3.9).

Note that the segment registers are user accessible. This means that the programmer can
change their contents through software.
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There is one restriction on the value assigned to a segment as base address: it must reside on a
16-byte address boundary. This is because the memory address is 20 bits while the segment
register width is 16 bits. Four bits (0000) must be added to the segment register content to
evaluate the segment starting address.

Figure 3.9 Software model of Intel 8086

Example:

Let the segment registers be assigned as follow:

CS = 0009H, DS = 0FFFH, SS = 10E0, and ES = 3281H.

We note here that code segment and data segment are overlapped while other segments are
disjointed (see Figure 3.10).

71
 Figure 3.10 Overlapped and disjointed segments

`Generating a memory address

In 8086, logical address is described by combining two parts: Segment address and offset.

• Segment address is 16-bit data from one of the segment registers (CS, SS, DS and
ES).
• Offset address is 16-bit data from one of the indexes and pointer registers (DI, SI, SP
and BP). Also, it could be base register BX.

To express the 20-bit Physical Address of memory:

1. Multiply Segment register by 10H (or shift it to left by four bit)

2. Add it to the offset (see Figure 3.11)

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 Figure 3.11 generating a memory address

Actually, many different logical addresses map to the same physical address location in
memory.

The stack is implemented in the memory and it is used for temporary storage of information
such as data and addresses. The stack is 64Kbytes long and is organized from a software
point of view as 32Kwords (see figure 3.12).

Figure 3.12 Stack segment of memory

• SS register points to the lowest address word in the stack

• SP and BP points to the address within stack
• Data transferred to and from the stack are word-wide, not byte-wide.
• The first address in the Stack segment (SS: 0000) is called End of Stack.
• The last address in the Stack segment (SS: FFFE) is called Bottom of Stack.
• The address (SS: SP) is called Top of Stack.
• POP instruction is used to read word from the stack.
• PUSH instruction is used to write word to the stack.
• When a word is to be pushed onto the top of the stack:
✓ The value of SP is first automatically decremented by two
✓ And then the contents of the register written into the stack.
• When a word is to be popped from the top of the stack the
✓ the contents are first moved out the stack to the specific register
✓ Then the value of SP is first automatically incremented by two.

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CHAPTER FOUR

4. Multiprocessor Architecture
Chapter objectives and expected results
The objectives of this chapter are:

o To learn how the multiprocessors function together;

o To understand the various multiprocessor configurations;

At the end of the chapter, students are expected to:

o Know and understand the various multiprocessor configurations available.

4.1 Multiprocessor Configuration Overview

Multiprocessor means a multiple set of processors that executes instructions simultaneously.
There are three basic multiprocessor configurations:

1. Coprocessor configuration
2. Closely coupled configuration
3. Loosely coupled configuration

Coprocessor Configuration

A Coprocessor is a specially designed circuit on microprocessor chip which can perform the
same task very quickly, which the microprocessor performs. It reduces the work load of the
main processor. The coprocessor shares the same memory, IO system, bus, control logic and
clock generator. The coprocessor handles specialized tasks like mathematical calculations,
graphical display on screen, etc.

The 8086 and 8088 can perform most of the operations but their instruction set is not able to
perform complex mathematical operations, so in these cases the microprocessor requires the
math coprocessor like Intel 8087 math coprocessor, which can easily perform these
operations very quickly. Figure 4.1 shows the block diagram of Coprocessor configuration.

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 Figure 4.1 Block diagram Coprocessor Configuration

How is the coprocessor and the processor connected?

• The coprocessor and the processor are connected via TEST, RQ-/GT- and QS0 &
QS1 signals.

• The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins
are connected to the coprocessor’s 3 pins of the same name.

• TEST signal takes care of the coprocessor’s activity, i.e. the coprocessor is busy or
idle.

• The RT-/GT-is used for bus arbitration.

• The coprocessor uses QS0 & QS1 to track the status of the queue of the host
processor.

Closely Coupled Configuration

Closely coupled configuration is similar to the coprocessor configuration, i.e. both share the
same memory, I/O system bus, control logic, and control generator with the host processor.
However, the coprocessor and the host processor fetches and executes their own
instructions. The system bus is controlled by the coprocessor and the host processor
independently. Figure 4.2 shows the block diagram of Closely Coupled Configuration.

75
 Figure 4.2 Block diagram Coprocessor Configuration

How is the processor and the independent processor connected?

• Communication between the host and the independent processor is done through
memory space.

• None of the instructions are used for communication, like WAIT, ESC, etc.

• The host processor manages the memory and wakes up the independent processor by
sending commands to one of its ports.

• Then the independent processor accesses the memory to execute the task.

• After completion of the task, it sends an acknowledgement to the host processor by

using the status signal or an interrupt request.

Loosely Coupled Configuration

Loosely coupled configuration consists of the number of modules of the microprocessor-

based systems, which are connected through a common system bus. Each module consists of
their own clock generator, memory, I/O devices and are connected through a local bus.
Figure 4.3 shows the block diagram of Loosely Coupled Configuration.

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 Figure 4.3 Block diagram Coprocessor Configuration

Advantages

• Having more than one processor results in increased efficiency.

• Each of the processors have their own local bus to access the local memory/I/O
devices. This makes it easy to achieve parallel processing.

• The system structure is flexible, i.e. the failure of one module doesn’t affect the
whole system failure; faulty module can be replaced later.

4.2 8087 Numeric Data Processor

8087 numeric data processor is also known as Math co-processor, Numeric processor
extension and Floating-point unit. It was the first math coprocessor designed by Intel to
pair with 8086/8088 resulting in easier and faster calculation.

Once the instructions are identified by the 8086/8088 processor, then it is allotted to the
8087 co-processor for further execution.

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The data types supported by 8087 are:

• Binary Integers

• Packed decimal numbers

• Real numbers

• Temporary real format

The most prominent features of 8087 numeric data processor are as follows:

• It supports data of type integer, float, and real types ranging from 2-10 bytes.

• The processing speed is so high that it can calculate multiplication of two 64-bits real
numbers in ~27 µs and can also calculate square-root in ~35 µs.

• It follows IEEE floating point standards.

4.2.1 8087 Architecture

8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric
Extension Unit (NEU).

• The control unit handles all the communication between the processor and the
memory such as it receives and decodes instructions, reads and writes memory
operands, maintains parallel queue, etc. All the coprocessor instructions are ESC
instructions, i.e., they start with ‘F’, the coprocessor only executes the ESC
instructions while other instructions are executed by the microprocessor.

• The numeric extension unit handles all the numeric processor instructions like
arithmetic, logical, transcendental, and data transfer instructions. It has 8 register
stacks, which holds the operands for instructions and their results.

The architecture of 8087 coprocessor is shown in figure 4.4.

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 Figure 4.3 Architecture block diagram of 8087 coprocessor

4.2.2 8087 Pin Description

Figure 4.4 Pin Diagram of 8087

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The following list provides the Pin Description of 8087:

• AD0 – AD15 − These are the time multiplexed address/data lines, which carry
addresses during the first clock cycle and data from the second clock cycle onwards.

• A19 / S6 – A16/S − These lines are the time multiplexed address/status lines. It
functions in a similar way to the corresponding pins of 8086. The S 6, S4 and S3 are
permanently high, while the S5 is permanently low.

• $\overline {BHE}$/S7 − During the first clock cycle, the $\overline {BHE}$/S7 is
used to enable data on to the higher byte of the 8086 data bus and after that works as
status line S7.

• QS1, QS0 − These are queue status input signals which provides the status of
instruction queue, their conditions as shown in the following table:

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

• INT − It is an interrupt signal, which changes to high when an unmasked exception

has been received during the execution.

• BUSY − It is an output signal, when it is high it indicates a busy state to the CPU.

• READY − It is an input signal used to inform the coprocessor whether the bus is
ready to receive data or not.

• RESET − It is an input signal used to reject the internal activities of the coprocessor
and prepare it for further execution whenever required by the CPU.

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 • CLK − The CLK input provides the basic timings for the processor operation.

• VCC − It is a power supply signal, which requires +5V supply for the operation of
the circuit.

• S0, S1, S2 − These are the status signals that provide the status of the operation which
is used by the Bus Controller 8087 to generate memory and I/O control signals.
These signals are active during the fourth clock cycle.

S2 S1 S0 Queue Status

0 X X Unused

1 0 0 Unused

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

• RQ/GT1 & RQ/GT0 − These are the Request/Grant signals used by the 8087
processors to gain control of the bus from the host processor 8086/8088 for operand
transfers.

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CHAPTER FIVE

5. Interfacing Input and Output devices to the Microprocessor

Chapter objectives and expected results
The objectives of this chapter are:

o To learn how the microprocessor interacts with the outside world;

o To understand how these, I/O devices interface with the microprocessor;
o To know Input and Output system of Intel 8085/8086 microprocessors.

At the end of the chapter, students are expected to:

o Understand the Input and Output System of the microprocessor;
o Know how these I/O devices interface;

5.1 Input and Output Interfaces

There is absolutely no point in having a computer at all unless there is some mechanism for
entering data into the computer and outputting data from it. A microprocessor system is
pointless unless it can communicate with the outside world. It does this through an
INTERFACE which is usually a plug or socket.

Interface is the path for communication between two components.

Interfacing is of two types, memory interfacing and I/O interfacing.

Memory Interfacing

When we are executing any instruction, we need the microprocessor to access the memory
for reading instruction codes and the data stored in the memory. For this, both the memory
and the microprocessor require some signals to read from and write to registers.

The interfacing process includes some key factors to match with the memory requirements
and microprocessor signals. The interfacing circuit therefore should be designed in such a
way that it matches the memory signal requirements with the signals of the microprocessor.

I/O Interfacing

There are various communication devices like the keyboard, mouse, printer, etc. So, we
need to interface the keyboard and other devices with the microprocessor by using latches

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and buffers. This type of interfacing is known as I/O interfacing. Figure 5.1 shows how a
microprocessor can be interface with memory and input/output devices.

Figure 5.1 Block Diagram of Memory and I/O Interfacing

8085 Interfacing Pins

Following is the list of 8085 pins used for interfacing with other devices −

• A15 - A8 (Higher Address Bus)

• AD7 - AD0(Lower Address/Data Bus)

• ALE

• RD

• WR

• READY

Ways of Communication − Microprocessor with the Outside World?

There are two ways of communication in which the microprocessor can connect with the
outside world.

• Serial Communication Interface

• Parallel Communication interface

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Serial Communication Interface − In this type of communication, the interface gets a
single byte of data from the microprocessor and sends it bit by bit to the other system
serially and vice-a-versa.

Parallel Communication Interface − In this type of communication, the interface gets a

byte of data from the microprocessor and sends it bit by bit to the other systems in
simultaneous (or) parallel fashion and vice-a-versa.

5.2 8279 - Programmable Keyboard

8279 programmable keyboard/display controller is designed by Intel that interfaces a
keyboard with the CPU. The keyboard first scans the keyboard and identifies if any key has
been pressed. It then sends their relative response of the pressed key to the CPU and vice-a-
versa.

Ways the Keyboard is Interfaced with the CPU:

The Keyboard can be interfaced either in the interrupt or the polled mode.

In the Interrupt mode, the processor is requested service only if any key is pressed,
otherwise the CPU will continue with its main task.

In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether
any key is pressed or not with key pressure.

How the 8279 Keyboard Works:

The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the
key-codes. These key-codes are de-bounced and stored in an 8-byte FIFORAM, which can
be accessed by the CPU. If more than 8 characters are entered in the FIFO, then it means
more than eight keys are pressed at a time. This is when the overrun status is set.

If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else
the CPU checks the status in polling to read the entry. Once the CPU reads a key entry, then
FIFO is updated, and the key entry is pushed out of the FIFO to generate space for new
entries. The architectural diagram is shown in figure 5.2.

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 Figure 5.2 Architecture Block Diagram of 8271 Programmable Keyboard

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is
low. Its data buffer interfaces the external bus of the system with the internal bus of the
microprocessor. The pins A0, RD, and WR are used for command, status or data read/write
operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation
of the circuit.

Scan Counter

It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the
keyboard and display.

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In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is
directly transferred to the sensor RAM along with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed
key is entered into the RAM as per their sequence. The status logic generates an interrupt
request after each FIFO read operation till the FIFO gets empty.

In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is
loaded with the status of their corresponding row of sensors into the matrix. When the
sensor changes its state, the IRQ line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word
currently read/written by the CPU to/from the display RAM.

5.2.1 8279 Pin Description

The following figure 5. 3 shows the pin diagram of 8279 programable keyboard.

Figure 5.3 Pin Diagram 8279

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Data Bus Lines, DB0 - DB7
These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.

CLK

The clock input is used to generate internal timings required by the microprocessor.

RESET

As the name suggests this pin is used to reset the microprocessor.

CS Chip Select

When this pin is set to low, it allows read/write operations, else this pin should be set to
high.

A0

This pin indicates the transfer of command/status information. When it is low, it indicates
the transfer of data.

RD, WR

This Read/Write pin enables the data buffer to send/receive data over the data bus.

IRQ

This interrupt output line goes high when there is data in the FIFO sensor RAM. The
interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.

Vss, Vcc

These are the ground and power supply lines of the microprocessor.

SL0 − SL3

These are the scan lines used to scan the keyboard matrix and display the digits. These lines
can be programmed as encoded or decoded, using the mode control register.

RL0 − RL7

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These are the Return Lines which are connected to one terminal of keys, while the other
terminal of the keys is connected to the decoded scan lines. These lines are set to 0 when any
key is pressed.

SHIFT

The Shift input line status is stored along with every key code in FIFO in the scanned
keyboard mode. Till it is pulled low with a key closure, it is pulled up internally to keep it
high

CNTL/STB - CONTROL/STROBED I/P Mode

In the keyboard mode, this line is used as a control input and stored in FIFO on a key
closure. The line is a strobe line that enters the data into FIFO RAM, in the strobed input
mode. It has an internal pull up. The line is pulled down with a key closure.

BD

It stands for blank display. It is used to blank the display during digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The
data from these lines is synchronized with the scan lines to scan the display and the
keyboard.

5.2.2 Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.

Input Mode

This mode deals with the input given by the keyboard and this mode is further classified into
3 modes.

• Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using
either encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the
decoded scan, a 4×8 keyboard can be interfaced. The code of key pressed with
SHIFT and CONTROL status is stored into the FIFO RAM.

• Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the
processor using either encoder or decoder scans. In the encoder scan, 8×8 sensor
matrix or with decoder scan 4×8 sensor matrix can be interfaced.
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 • Strobed Input − In this mode, when the control line is set to 0, the data on the return
lines is stored in the FIFO byte by byte.

Output Mode

This mode deals with display-related operations. This mode is further classified into two
output modes:

• Display Scan − This mode allows 8/16-character multiplexed displays to be

organized as dual 4-bit/single 8-bit display units.

• Display Entry − This mode allows the data to be entered for display either from the
right side/left side.

5.3 8257 DMA Controller

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data directly to/from memory without any
interference of the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data
transfer is initiated only after receiving HLDA signal from the CPU.

How DMA Operations are Performed:

Following is the sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.

• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.

• Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through
HLDA signal.

• Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.

Features of 8257

Here is a list of some of the prominent features of 8257 −

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 • It has four channels which can be used over four I/O devices.

• Each channel has 16-bit address and 14-bit counter.

• Each channel can transfer data up to 64kb.

• Each channel can be programmed independently.

• Each channel can perform read transfer, write transfer and verify transfer operations.

• It generates MARK signal to the peripheral device that 128 bytes have been
transferred.

• It requires a single-phase clock.

• Its frequency ranges from 250Hz to 3MHz.

• It operates in 2 modes, i.e., Master mode and Slave mode.

5.3.1 8257 Architecture
The following figure 5.4 shows the architecture of 8257:

Figure 5.4 Architecture of 8257

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5.3.2 8257 Pin Description
The following figure 5.5 shows the pin diagram of an 8257 DMA controller −

Figure 5.5 Pin Diagram 8257 Controller

DRQ0−DRQ3

These are the four individual channel DMA request inputs, which are used by the peripheral
devices for using DMA services. When the fixed priority mode is selected, then DRQ0 has
the highest priority and DRQ3 has the lowest priority among them.
DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting peripheral
about the status of their request by the CPU. These lines can also act as strobe lines for the
requesting devices.

Do − D7

These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to 8257
and status word from 8257. In the master mode, these lines are used to send higher byte of
the generated address to the latch. This address is further latched using ADSTB signal.

IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal
registers of 8257 in the Slave mode. In the master mode, it is used to read data from the
peripheral devices during a memory write cycle.

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IOW

It is an active low bi-direction tri-state line, which is used to load the contents of the data bus
to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal
count register. In the master mode, it is used to load the data to the peripheral devices during
DMA memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3

These are the four least significant address lines. In the slave mode, they act as an input,
which selects one of the registers to be read or written. In the master mode, they are the four
least significant memory address output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master
mode.

READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait
states.

HRQ

This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with
HOLD input of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus has
been granted to the requesting peripheral by the CPU when it is set to 1.

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MEMR

It is the low memory read signal, which is used to read the data from the addressed memory
locations during DMA read cycles.

MEMW

It is the active-low three state signal which is used to write the data to the addressed memory
location during DMA write operation.

ADST

This signal is used to convert the higher byte of the memory address generated by the DMA
controller into the latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK
output to the selected peripheral device.

Vcc

It is the power signal which is required for the operation of the circuit.

93
CHAPTER SIX

6. Microcontrollers
Chapter objectives and expected results
The objectives of this chapter are:

o To understand how a microcontroller works;

o To how the microcontroller differs from a microprocessor;
o To learn about the 8051 microcontrollers.

At the end of the chapter, students are expected to:

o Understand the Input and Output System of the 8051 microcontrollers;
o Know how these I/O devices interface;
6.1 Overview of Microcontrollers
A microcontroller is a small and low-cost microcomputer, which is designed to perform the
specific tasks of embedded systems like displaying microwave’s information, receiving
remote signals, etc.

The general microcontroller consists of the processor, the memory (RAM, ROM, EPROM),
Serial ports, peripherals (timers, counters), etc.

Difference between Microprocessor and Microcontroller

The following table highlights the differences between a microprocessor and a

microcontroller:

Microcontroller Microprocessor

Microcontrollers are used to execute a single task within an application. Microprocessors

are used for big
applications.

Its designing and hardware cost are low. Its designing and
hardware cost

94
 are high.

Easy to replace. Not so easy to

replace.

It is built with CMOS technology, which requires less power to operate. Its power
consumption is
high because it
has to control the
entire system.

It consists of CPU, RAM, ROM, I/O ports. It doesn’t consist

of RAM, ROM,
I/O ports. It uses
its pins to
interface to
peripheral
devices.

Types of Microcontrollers
Microcontrollers are divided into various categories based on memory, architecture, bits and
instruction sets. Following is the list of their types:

Bit

Based on bit configuration, the microcontroller is further divided into three categories.

• 8-bit microcontroller − This type of microcontroller is used to execute arithmetic

and logical operations like addition, subtraction, multiplication division, etc. For
example, Intel 8031 and 8051 are 8 bits microcontroller.

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 • 16-bit microcontroller − This type of microcontroller is used to perform arithmetic
and logical operations where higher accuracy and performance is required. For
example, Intel 8096 is a 16-bit microcontroller.

• 32-bit microcontroller − This type of microcontroller is generally used in

automatically controlled appliances like automatic operational machines, medical
appliances, etc.

Memory

Based on the memory configuration, the microcontroller is further divided into two
categories.

• External memory microcontroller − This type of microcontroller is designed in

such a way that they do not have a program memory on the chip. Hence, it is named
as external memory microcontroller. For example: Intel 8031 microcontroller.

• Embedded memory microcontroller − This type of microcontroller is designed in

such a way that the microcontroller has all programs and data memory, counters and
timers, interrupts, I/O ports are embedded on the chip. For example: Intel 8051
microcontroller.

Instruction Set

Based on the instruction set configuration, the microcontroller is further divided into two
categories.

• CISC − CISC stands for complex instruction set computer. It allows the user to insert
a single instruction as an alternative to many simple instructions.

• RISC − RISC stands for Reduced Instruction Set Computers. It reduces the
operational time by shortening the clock cycle per instruction.

Applications of Microcontrollers

Microcontrollers are widely used in various different devices such as −

• Light sensing and controlling devices like LED.

• Temperature sensing and controlling devices like microwave oven, chimneys.

• Fire detection and safety devices like Fire alarm.

96
 • Measuring devices like Volt Meter.

6.2 Intel 8051 Architecture

The 8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller. It is
built with 40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM
storage, 2 16-bit timers. It consists of are four parallel 8-bit ports, which are programmable
as well as addressable as per the requirement. An on-chip crystal oscillator is integrated in
the microcontroller having crystal frequency of 12 MHz. The figure 6.1 shows the
architecture of the Intel 8051.

Figure 6.1 Architecture Block Diagram of Intel 8051

In the figure 6.1, the system bus connects all the support devices to the CPU. The system
bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals. All other
devices like program memory, ports, data memory, serial interface, interrupt control, timers,
and the CPU are all interfaced together through the system bus.

6.2.1 Intel 8051 Pin Description

97
The pin diagram of 8051 microcontroller is explain using the figure 6.2.

Figure 6.2 Pin Diagram of Intel 8051

• Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other
functions. It is internally pulled up, bi-directional I/O port.

• Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial
values.

• Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like
interrupts, timer input, control signals, serial communication signals RxD and TxD,
etc.

• Pins 18 & 19 − These pins are used for interfacing an external crystal to get the
system clock.

98
 • Pin 20 − This pin provides the power supply to the circuit.

• Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order
address bus signals are also multiplexed using this port.

• Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read
a signal from the external program memory.

• Pin 30 − This is EA pin which stands for External Access input. It is used to
enable/disable the external memory interfacing.

• Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to
demultiplex the address-data signal of port.

• Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order
address and data bus signals are multiplexed using this port.

• Pin 40 − This pin is used to provide power supply to the circuit.

6.2.2 Microcontrollers 8051 Input Output Ports

The Intel 8051 microcontrollers has 4 I/O ports each of 8-bit, which can be configured as
input or output. Hence, total 32 input/output pins allow the microcontroller to be connected
with the peripheral devices.

• Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as
per the logic state.

o Input/output (I/O) pin − All the circuits within the microcontroller must be
connected to one of its pins except P0 port because it does not have pull-up
resistors built-in.

o Input pin − Logic 1 is applied to a bit of the P register. The output FE

transistor is turned off and the other pin remains connected to the power
supply voltage over a pull-up resistor of high resistance.

• Port 0 − The P0 (zero) port is characterized by two functions −

o When the external memory is used then the lower address byte (addresses
A0A7) is applied on it, else all bits of this port are configured as input/output.

99
 o When P0 port is configured as an output then other ports consisting of pins
with built-in pull-up resistor connected by its end to 5V power supply, the
pins of this port have this resistor left out.

Input Configuration

If any pin of this port is configured as an input, then it acts as if its “floats”, i.e. the input has
unlimited input resistance and in-determined potential.

Output Configuration

When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0
to a port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the
external output will keep on “floating”.

In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup
resistor.

Port 1

P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be
configured as general I/O only. It has a built-in pull-up resistor and is completely compatible
with TTL circuits.

Port 2

P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.

Port 3

In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.

Pins Current Limitations

• When pins are configured as an output (i.e. logic 0), then the single port pins can
receive a current of 10mA.

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 • When these pins are configured as inputs (i.e. logic 1), then built-in pull-up resistors
provide very weak current, but can activate up to 4 TTL inputs of LS series.

• If all 8 bits of a port are active, then the total current must be limited to 15mA (port
P0: 26mA).

• If all ports (32 bits) are active, then the total maximum current must be limited to
71mA.

6.2.3 Microcontrollers - 8051 Interrupts

Interrupts are the events that temporarily suspend the main program, pass the control to the
external sources and execute their task. It then passes the control to the main program where
it had left off.

8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be
enabled or disabled by setting bits of the IE register and the whole interrupt system can be
disabled by clearing the EA bit of the same register.

IE (Interrupt Enable) Register

This register is responsible for enabling and disabling the interrupt. EA register is set to one
for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their
meanings are shown in the following figure.

It disables all interrupts. When EA = 0 no interrupt will be

EA IE.7
acknowledged and EA = 1 enables the interrupt individually.

- IE.6 Reserved for future use.

- IE.5 Reserved for future use.

ES IE.4 Enables/disables serial port interrupt.

101
ET1 IE.3 Enables/disables timer1 overflow interrupt.

EX1 IE.2 Enables/disables external interrupt1.

ET0 IE.1 Enables/disables timer0 overflow interrupt.

EX0 IE.0 Enables/disables external interrupt0.

IP (Interrupt Priority) Register

We can change the priority levels of the interrupts by changing the corresponding bit in the
Interrupt Priority (IP) register as shown in the following figure.

• A low priority interrupt can only be interrupted by the high priority interrupt, but not
interrupted by another low priority interrupt.

• If two interrupts of different priority levels are received simultaneously, the request
of higher priority level is served.

• If the requests of the same priority levels are received simultaneously, then the
internal polling sequence determines which request is to be serviced.

- IP.6 Reserved for future use.

- IP.5 Reserved for future use.

PS IP.4 It defines the serial port interrupt priority level.

PT1 IP.3 It defines the timer interrupt of 1 priority.

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PX1 IP.2 It defines the external interrupt priority level.

PT0 IP.1 It defines the timer0 interrupt priority level.

PX0 IP.0 It defines the external interrupt of 0 priority level.

TCON Register
TCON register specifies the type of external interrupt to the microcontroller.

103
 UNIVERSITY OF MINES AND TECHNOLOGY, TARKWA
END OF SECOND SEMESTER EXAMINATION
2013/2014 ACADEMIC YEAR, APRIL 2014

BSc. COMPUTER SCIENCE & ENGINEERING

INTRODUCTION TO MICROPROCESSORS AND CONTROL SYSTEMS

CE 268

TIME: 3 HOURS

Name: …………………………………………………………. Index Number:

…………………………..

INSTRUCTIONS: Attempt All questions in SECTIONS A, SECTION B and SECTION

C. You are advised not to spend more than 1 hour on SECTION A.

SECTION A

Answer All Questions on the question paper by circling or ticking (√) the correct answers.
Each question carries 0.5 Mark. An incorrect answer attracts a -0.5 Mark so do not guess.

1. Which interrupt has the highest priority?

a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, b) INTR, TRAP
RST7.5
c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising b) RST7.5 is a raising c) a & b.
edge-trigging interrupt. edge-trigging interrupt.
7. Which are software interrupts?
a) RST 0 – 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?

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a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 b) Because 8085 c) a & b.
processor has 8 bit ALU. processor has 8 bit data
bus.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is b) The interrupt is c) a & b
done or not Masked or not
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes c) sometimes yes,
sometimes no
b) No
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
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c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory c) I/O
b) Odd bank memory d) DMA
21. In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI c) TYPE 255
b) DIV 0 d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output c) Support of coprocessor
b) Address capability d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H
25. What is the output of the following code ?
AL= 00110100 BL= 00111000
ADD AL, BL
AAA
a) AL = 6CH c) 12
b) 12H d) C6H

26. What is the output of the following code

PUSH AL
a) Decrement SP by 2 & push a word to c) Decrement SP by 2 & push a AL to
stack stack
b) Increment SP by 2 & push a word to d) Illegal
stack
27. What is the output of the following code
AX = 37D7H, BH = 151 decimal
DIV BH
a) AL = 65H, AH= 94 decimal b) AL= 5EH, AH= 101 decimal
106
c) AH= E5H, AL= 5EH d) AL= 56H, AH= 5EH
28. The conditional branch instruction JNS performs the operations when if __ ?

a) ZF =0 c) PF=0
b) SF=0 d) CF=0
29. The XOR operation is classified as a(n) ____________________ instructions.
a) Branch. c) Logical.
b) Arithmetic. d) Subroutine

30. The flags are mostly closely associated with ________________ .

a) Insruction Decoder. c) PC.
b) Accumulator. d) ALU.
[TOTAL=30 marks]

SECTION B

Answer All Questions

Q1. List the internal registers in 8085 microprocessor and their abbreviations and lengths.
Describe the primary function of each register.
Q2. Differentiate between NMI and MI interrupts.
Q3. What is the length of bytes reserved for the following directive STORE DW 100 DUP
(0)
Q4. List all the registers associated with the four segment registers.
Q5. List the internal registers in 8086 Microprocessor.
Q6. What are the main blocks in BIU and EU ?
Q7. Explain the coordination between BIU an EU.
Q8. Bring out the differences between 8086 and 8088 processors.
Q9. State all the features of 8080 microprocessor.
Q10. Describe the operation performed by the instruction OUT 47h, AL.

[TOTAL= 25 marks]

SECTION C

Write an ALP to add two 32-bit binary numbers starting at locations ‘F100’ and ‘F200’ and
store the result starting at location ‘F300’.
RESULTS:

107
 BEFORE EXECUTION:
Addr. Of 1st Data Addr. Of 2nd Data Addr. Of the Data
32-bit 32-bit result
number number
F100 01 F200 AA F300 XX
F101 02 F201 BB F301 XX
F102 03 F202 CC F302 XX
F103 04 F203 DD F303 XX

AFTER EXECUTION:
Addr. Of 1st Data Addr. Of 2nd Data Addr. Of the Data
32-bit 32-bit result
number number
F100 01 F200 AA F300 AB
F101 02 F201 BB F301 BD
F102 03 F202 CC F302 CF
F103 04 F203 DD F303 E1

[ TOTAL = 15 marks]
Mr. T. Kwantwi

SECTION A
1. C 16. C
2. C 17. C
3. C 18. B
4. B 19. D
5. B 20. B
6. B 21. A
7. A 22. B
8. B 23. A
9. A 24. B
10. C 25. C
11. B 26. D
12. B 27. B
13. A 28. B
14. B 29. C
15. B 30. D

108
 SECTION B
Q1. Internal registers of 8085 microprocessor, their abbreviations and size lengths and functions
of each:

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store
operations.
• Flag Register has five 1-bit flags.
• Sign - set if the most significant bit of the result is set.
• Zero - set if the result is zero.
• Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
• Parity - set if the parity (the number of set bits in the result) is even.
• Carry - set if there was a carry during addition, or borrow during
subtraction/comparison/rotation.
General Registers
• 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a
pair the C register contains low-order byte. Some instructions may use BC register as a
data pointer.
• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a
pair the E register contains low-order byte. Some instructions may use DE register as a
data pointer.
• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a
pair the L register contains low-order byte. HL register usually contains a data pointer
used to reference memory addresses.
• Stack pointer is a 16 bit register. This register is always decremented/incremented by 2
during push and pop.
• Program counter is a 16-bit register used to point to the next instruction to be executed

Q2. Difference between NMI and MI Interrupts is

The interrupt which can be ignored by the processor, while performing its operations are called
maskable interrupts. Generally maskable interrupts are the interrupts that comes from the
peripheral devices, where as the non maskable interrupts are the interrupts which cannot be
ignored. Generally these types of interrupts are specified to be software interrupts. The examples
of maskable are: mouse click, memory read etc the examples of non maskable.

Q3. Length of bytes reserved for the directive STORE DW 100 DUP (0) is 100 words are
reserved with a value of 0 in each location.
Q4. Registers associated with the four segment registers.
They are:
Code segment – CS;

109
Data segment – DS;
Stack segment – SS; and
Extended segment - ES
Q5. The internal registers in 8086 microprocessor are as follows:
The 8086 has four groups of the user accessible internal registers. They are the instruction
pointer, four data registers, four pointer and index register, four segment registers.
Instruction Pointer – IP
Data registers - Accumulator (A), Base register (BX), Count register (CX), and Data register
(DX)
Pointer and Index registers – stack pointer (SP), base pointer (BP), destination index (DI) and
source index (SI)
Segment registers – CS, DS, SS and ES
Q6. Main blocks in BIU and EU
BIU contains Instruction queue, Segment registers, Instruction pointer, and Address adder
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
Q7. Explanation of coordination between BIU and EU
The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The instruction
bytes are transferred to the instruction queue whiles EU executes instructions from the
instruction system byte queue. Both units operate asynchronously to give the 8086 an
overlapping instruction fetch and execution mechanism which is called as Pipelining. This
results in efficient use of the system bus and system performance.

Q8. Differences between 8086 and 8088 processors

8086 8088
1. 8086 has 16-bit data lines 8088 has 8-bit data lines
2. 8086 is available in three clock Whereas 8088 is available in 2 clock
speed 5 MHz, 8 MHz and 10 MHz speeds 5 MHz and 8 MHz
3. Memory space of 8086 is organised Memory space of 8088 is implemented as a
as two 512KB banks single 1M*8 memory bank
4. The 8086 has 6-bit instruction 8088 has 4-bit instruction queue
queue
5. 8086 has BHE (Bank High Enable ) The 8088 has SSO status signal
6. The 8086 can read/write 8-bit or The 8088 can read/write 8-bit data at a
16-bit data at a time time
7. The I/O voltages level for 8086 is The I/O voltages level for 8088 is

110
 measured at 2.5 mA measured at 2 mA
8. 8086 draws maximum supply 8086 draws maximum supply current of
current of 360 mA 360 mA

Q9. Features of 8080 processor

❑ The 8080 has a 16-bit address bus and an 8-bit data bus.
❑ It has seven 8-bit registers (six which could also be combined as three 16-bit registers),
❑ Has a 16-bit stack pointer to memory
❑ Has a 16-bit program counter.
❑ It also has 256 I/O ports (so I/O devices could be connected without needing to allocate
any addressing space as is required for memory mapped devices) and a signal pin that
allowed the stack to occupy a separate bank of memory.
Q10. Operation perform by the instruction OUT 47h, AL
Outputs the content of register AL to the port 47h

SECTION C
An ALP program adding two 32-bit binary numbers starting at location F100 and F200 and
storing the result starting at location F300

START: LXI H, F100

LXI B, F200
LXI D, F300
STC
CMC
MVI A, 04
LOOP: STA F400
LDAX B
ADC M
STAX D
INX H
INX B

111
 INX D
LDA F400
DCR A
JNZ LOOP
MVI A,00
RAL
STAX D
HL

UNIVERSITY OF MINES AND TECHNOLOGY, TARKWA

END OF SECOND SEMESTER EXAMINATION
2012/2013 ACADEMIC YEAR, APRIL 2013

BSc. COMPUTER SCIENCE & ENGINEERING

INTRODUCTION TO MICROPROCESSORS AND CONTROL SYSTEMS

CE 268

TIME: 3 HOURS

Name: …………………………………………………………. Index Number:

…………………………..

INSTRUCTIONS: Attempt All questions in SECTIONS A, SECTION B and SECTION C.

You are advised not to spend more than 1 hour on SECTION A. All
Sections carry 20 Marks.

SECTION A

Answer All Questions on the question paper by circling or ticking (√) the correct answers.
Each question carries 0.5 Mark. An incorrect answers attracts a -0.5 Mark so do not guess.

1. Which programming technique is used when a repetitive tasks must be performed by a

microprocessor
a) Subroutine.
b) Return.
c) Branching.
d) Looping.

2. Operations using the register indirect addressing mode are specified with _______________
instructions.
a) 1 byte.

112
 b) 2 bytes.
c) 3 bytes.
d) 4 bytes.

3. The most popular word size for a microprocessor is ?

a) 4 bits.
b) 8 bits.
c) 16 bits.
d) 32 bits.

4. The microprocessor is normally housed in a __________________ DIP integrated circuit.

a) 40 pin.
b) 50 pin.
c) 60 pin.
d) 120 pin

5. The generic microprocessor contains a zero and a carry flag. These are located in the
_____________.
a) Interrupt control.
b) Status register.
c) Instruction register.
d) Program counter.

6. What does the operation INC do to the contents of a register in the microprocessor
a) Add 1
b) Substract 1
c) Compare
d) Shift bits 1 place to the left

7. Finding and correcting errors in a program is a process commonly called.

a) Failure logging
b) Proofing
c) Routing
d) Debugging

8. A typical assembly language program statement is divided into four fields namely.
a) Mnemonic, operation, label, and comment.
b) Op-code, comment, mnemonic and operand.
c) Operand, label source, comment and op-code
d) Label, mnemonic, operand and comment

9.The following are all 16-bit registers accept.

a) SP
b) IP
c) AL

113
 d) AX

10. After defining and analyzing the problem, the next step in programming is to create
______________ showing the problem’s solution
a) Documentation.
b) Flowchart.
c) Source file.
d) Object file

11. Linkage of parts within a microprocessor based system is called.

a) Interconnection.
b) Linking.
c) Interfacing.
d) Allaigning

12. A technique by which each I/O device is periodically sampled to determine whether it is
“Ready” and needs servicing is called.
a) Polling
b) Interrupt
c) Mapping
d) Writing
13. The 8085 microprocessor uses a ___________________ power supply.
a) +50V. c) -5V.
b) +5V. d) +3V

14. Which of the following is an 8-bit microprocessor.

a) INTEL 8086 c) INTEL 8085
b) INTEL 8088 d) INTEL 80486

15. What is the size of the program counter

a) 4 bits d) 4 bytes
b) 8 bits
c) 2 bytes
16. Which interrupt has the highest priority?
a) INTR
b) TRAP
c) RST 6.5
d) None of the above

17. The 8088 microprocessor differs with the 8086 microprocessor in.
a) Data width on the output.
b) Address capability.
c) Support of coprocessor
d) Support of MAX/MIN mode

18. The Motorola 68000 microprocessor is.

114
 a) 16 bits c) 64 bits
b) 32 bits d) 8 bits

19. Which of the following is an illegal 8086 instruction.

a) MOV AX, [BX]. c) ADD BX, [DX].
b) INC [BX]. d) ADD [BX], 1

20. The load operation, LDA 210AH uses which type of addressing mode.
a) Immediate c) Direct
b) Inherent d) Indirect

21. Many times ______________ instructions are used in a program just before a conditional
branch operation.
a) Load. c) Compare.
b) Move. d) Store.
22. In writing a machine language version of a program, instructions are assigned sequential
program memory ______________ .
a) Addresses
b) Interrupts
c) Words
d) Segments
23. The values in the following are not affected by a compare operation except.
a) Accumulator
b) Program Counter
c) Status register
d) Memory Addresses
24. An assembly language program is translated to machine code by
a) an assembler
b) a compiler
c) an Interpreter
d) a linker Object.
25. Which of the following is considered as a general-purpose data register.
a) A c) BP
b) SI d) PC
e)
26. In 8086, an example for a Non-maskable interrupt is.
a) TRAP c) INTR
b) RST 6.5 d) None.
27. Which of the following microprocessor structure is pipelined?
a) All X80 processors

115
 b) All X85 processors
c) All X86 processors
d) All above
28. In 8086 microprocessor the overflow flag is set when.
a) The sum is more than 16 bits.
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
d) None of the above
29. The XOR operation is classified as a(n) ____________________ instructions.
a) Branch. c) Logical.
b) Arithmetic. d) Subroutine
e) .

30. The flags are mostly closely associated with ________________ .

a) Insruction Decoder. c) PC.
b) Accumulator. d) ALU.

31. Read/Write memories are many times classed as either.

a) Static or Stable c) Static or Dynamic
b) Stable or Dynamic d) Dynamic or Temporal

32. A microprocessor’s decision-making operations are called the ___________________

instructions.
a) Subroutine c) Loop
b) Branch d) Data transfer
33. In a generic microprocessor, which time period is shorter?
a) Instruction cycle.
b) Operation cycle.
c) Machine cycle.
d) None of the above.

34. What does a microprocessor speed depends on ?

a) Clock.
b) Data bus width.
c) Address bus width.
d) Size of program memory.
35. Which of the following is a hardware interrupt?
a) RST 5.5, RST 6.5, RST 7.5

116
 b) INTR
c) TRAP
d) a, b & c
36. To copy the hexadecimal number A to the bh register you write.
a) mov 0bh, ah c) mov bh, ah
b) mov bh, 0ah d) mov bh, [ah]
37. Which of the following is an illegal instruction.
a) MOV AX, 30000
b) INC AL, 1
c) AND BX, BX
d) ADD AX, 30
38. The effect of the following instructions
push ax
add ax, 4
pop bx
mov cx, ax
push bx
pop ax
on the ax register is
a) leave it with its original value
b) add 4 to it
c) clear it
d) double it
39. Why is the 8080 microprocessor called a 1 byte processor?
a) Because 8080 microprocessor has 1 byte ALU.
b) Because 8080 microprocessor has 1 byte data bus.
c) Because 8080 microprocessor has 8 bits address bus.
d) a & b.

40. Which of the following is an illegal 8086 instruction.

a) Mov 20, bx
b) Inc al
c) And bx, bx
d) Add ax, 30
[TOTAL=20 marks]

117
 SECTION B

Answer All Questions on the question paper by filling in with the correct answers.

1. The devices that provide the means for a computer to communicate with the user or other
computers are reffered to as _______________________.
2. The software used to drive microprocessor-based system is called
___________________________.
3. The circuits in the 8085A microprocessor that provide the arithmetic and logic functions
are called _________________________________.
4. The number of buses connected as part of the 8086 microprocessor is
______________________.
5. Single-bit indicators that may be set or cleared to show the results of logical or arithmetic
operations are the ______________________.
6. The technique of assigning a memory address to each I/O device in the computer system
is called ___________________________.
7. The first 8-bit microprocessor was introduced in the year _________________.
8. In a DMA write operation the data is transferred
__________________________________.
9. The number of times the instruction sequence below will loop before coming out of loop
is _________________.
MOV AL, 00H;
A1: INC AL;
JNZ A1
10. In the instruction FADD, F stands for ____________________.
11. Itanium processor of Intel is a ________ bit microprocessor.
12. The name of a memory device example whose content can be erased using ultra violet
rays is ____________________.
13. The ____________________ is used to keep track of the memory address of the next op-
code to be run in a program.
14. The 8085A is a(an) _______________ parallel CPU.
15. The content of register AL after the following instructions have been executed will be
____________________________.
MOV BL, 8C;
MOV AL, 7E;
ADD AL, BL;
16. The 8088 microprocessor has __________ bit address bus.
17. A machine cycle consists of one or more _________________________.
18. The stack in memory of a computer system is normally organized as _____________.
19. I/O mapped systems identify their input/output devices by giving them an 8-bit
_________________.
20. The following are the basic sections of a microprocessor unit registers, ALU and
_____________________.

[TOTAL= 20 marks]

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 SECTION C

Answer ALL QUESTIONS in this section.

1. Describe the operation performed by the instruction OUT 47h, AL.

[2 marks]
2. What do you mean by external and internal data bus? How are these two related in 8088
processor.
[4 marks]
3. What is the purpose of the carry (C) flag and zero (Z) flag.
[2 marks]
4. Explain the following instructions
i. MOV iii. CMP
ii. NEG iv. CMA
[8 marks]
5. Write an assembly language code program to find two’s complement of an 8-bit number
using the 8086 instruction set.
[4 marks]

[ TOTAL = 20 marks]
Mr. T. Kwantwi

119