Day 1

Half Adder – Verilog Project

Aditya Kumar
[Link] ECE (Minor in CS)
june

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 Description

The Half Adder is one of the simplest and most fundamental combinational logic circuits
used in digital electronics. It performs the addition of two single-bit binary numbers,
producing a sum and a carry output. Unlike a full adder, the half adder does not con-
sider any carry input from the previous stage, which makes it suitable only for the least
significant bit (LSB) addition in a multi-bit binary operation.

The logic used in a half adder is derived from basic Boolean algebra, with the Sum
calculated using an XOR gate and the Carry using an AND gate. The half adder
serves as the foundational block for understanding more complex arithmetic circuits like
full adders, multi-bit adders, and Arithmetic Logic Units (ALUs) in digital processors.

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 RTL Code (Verilog)

module half adder (

input A,
input B,
output Sum,
output Carry
);
assign Sum = A ^ B; // XOR gate for sum
assign Carry = A & B; // AND gate for carry
endmodule

Explanation: The XOR operator ( ˆ ) produces 1 when inputs are different —

giving us the binary sum. The AND operator ( & ) outputs 1 only when both A and B
are 1 — this forms the carry output. This RTL code defines a clean, synthesizable design
using a structural coding style and is efficient and simple for simulation.

Testbench
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module tb half adder;

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reg A, B;
wire Sum, Carry;
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half adder uut (

.A(A),
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.B(B),
.Sum(Sum),
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.Carry(Carry)
);
initial begin
$display("A B | Sum Carry");
A = 0; B = 0; #10;
$display("%b %b | %b %b", A, B, Sum, Carry);
A = 0; B = 1; #10;
$display("%b %b | %b %b", A, B, Sum, Carry);
A = 1; B = 0; #10;
$display("%b %b | %b %b", A, B, Sum, Carry);
A = 1; B = 1; #10;
$display("%b %b | %b %b", A, B, Sum, Carry);
end
endmodule

Explanation: This testbench simulates all 4 input combinations: (00, 01, 10, 11)
and prints the corresponding Sum and Carry values. The delays of #10 ensure that each
combination has enough time to propagate before output is read.

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Simulation Results
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Explanation: The waveform and result table confirm that the Half Adder is working
as expected. The Sum is 1 when inputs differ, and Carry is 1 only when both inputs are
1.

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Figure 1: Result

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Schematic (Logic Diagram)
Components Used:

• 1 XOR gate – to produce Sum

• 1 AND gate – to produce Carry

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Figure 2: Schematic
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Applications
• Basic arithmetic logic for LSB addition in processors.

• Digital calculator logic blocks.

• Base unit in designing Full Adders and ALUs.

• Used for FPGA and Verilog practice labs.

• Common teaching example for Boolean logic and truth tables.

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 Advantages
• Simple: Only two gates required.

• Fast: Minimum propagation delay.

• Beginner-friendly: Best for learning combinational circuits.

• Reusable: Can be used inside complex designs like ripple carry adders.

Disadvantages
• No Carry Input: Cannot process multi-bit carry chaining.

• Not Standalone for full addition: Limited to 1-bit.

• Less scalable without modification or chaining with other logic.

Tools Used
• Vivado Design Suite – for writing Verilog and simulating the design.
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• Verilog HDL – for hardware logic implementation.

• Testbench Simulation – to verify functional correctness.

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Conclusion
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The implementation of the Half Adder was a great starting point in my Verilog learning
journey. Through this project, I got hands-on experience in designing and simulating a
basic combinational circuit that performs simple binary addition.

Working on this helped me understand how XOR and AND gates are used together
to build meaningful logic. Writing the Verilog code, testing it with a testbench, and
analyzing the output waveforms in Vivado gave me more clarity on how digital circuits
behave during simulation.

This small but important step boosted my confidence to take on more complex designs
like Full Adders, Multiplexers, and Counters in the upcoming days. Overall, this Day 1
project laid a strong foundation for exploring digital logic design with HDL.