Interfacing with 8255A Programmable Peripheral Interface(PPI) [MODE 0 and MODE 1]
OBJECTIVES
To interface the 8255A Programmable Peripheral Interface with the 8085 microprocessor system.
To implement and analyze Mode 0 and Mode 1 operations for input and output using 8255A ports.
To understand and configure the control word register for programming different port functions.
THEORY
8255A - Programmable Peripheral Interface
The 8255A is a general purpose programmable I/O device designed to transfer the data from I/O to interrupt I/O
under certain conditions as required. It can be used with almost any microprocessor. It consists of three 8-bit
bidirectional I/O ports (24I/O lines) which can be configured as per the requirement.
Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
Port B is similar to PORT A.
Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT C. Group B
includes PORT B and lower PORT C. These two groups can be programmed in three different modes, i.e. the first
mode is named as mode 0, the second mode is named as Mode 1 and the third mode is named as Mode 2.
Control Word Register
To configure the 8255A, a Control Word is sent to its control register using the 8085. Control register is an 8-bit
register where control word is kept. The control word specifies:
Mode selection (Mode 0 or Mode 1)
Input/output settings for each port
Group configurations
Control Word is an 8-bit data that stored in control register. Control Words are two types:
BSR Control Word
Mode definition Control Word.
BSR Control Word
If bit D7 of control word is set as logic 0 then 8255 will be configured as BSR (Bit Set Reset) mode. In this mode we
can set or reset the pins of Port C by selection.
Mode Definition Control Word
If bit D7 of control word is set as logic 1 then 8255 will be configured as Mode Definition mode.
Programming on Mode 0
The ports A, B and C can be configured as simple input or output ports by writing the appropriate control word in the
control word register. In the control word, D7 is set to '1' (to define a mode set operation) and D6, D5, and D2 are all
set to '0' configure all the ports in Mode 0 operation. The status of bits D4, D3, D1 and D0 then determine whether
the corresponding ports are to be configured as Input or Output.
Programming on BSR Mode
Any of the eight bits of port C can be set or reset using a single output instruction. This feature reduces software
requirements in control-based applications. When Port C is being used as Status / Control for Port A or B, these bits
can be set or reset by using Bit Set/Reset. Word in the control register when D7 = 0 is recognized as BSR control word
and does not affect the I/O operations of Port A and B.
Programming on Mode 1
In Mode 1, handshake signals are exchanged between the MPU and peripherals prior to data transfer. Two ports (A
and B) function as 8-bit I/O ports. They can be configured either as input or output ports. Each port uses three lines
from port C as handshake signals The remaining two lines of port C can be used for simple I/O functions. When Port
A is to be programmed as an input port, PC3, PC4, and PC5 are used for control, PC6 and PC7 can be Input or Output,
as programmed by bit D3 (Cupper) of the control word. When Port A is programmed as an output port, PC3, PC6, PC7
are used for control and PC4 and PC5 can be Input or Output, as programmed by bit D3 (Cupper) of the control word.
When Port B is to be programmed as an input or output port, PC0, PC1 and PC2 are all used for control.
MODE 1: INPUT
The peripheral first loads data into Port A by making the STBA input low. This latches the data placed by the
peripheral on the common data bus into Port A. Port A acknowledges reception of data by making IBFA (Input Buffer
Full) high. IBFA is set when the STBA input is made low. INTRA is an active output signal which can be used to
interrupt the CPU so that the CPU can suspend its current operation and read the data written into Port A by the
peripheral. INTRA can be enabled or disabled by the INTEA flip-flop which is controlled by BIT Set- Reset operation of
PC4. INTRA is set (if enabled by setting the INTEA flip-flop) after the STBA has gone high again, and if IBFA is high. On
receipt of the interrupt, the CPU can be made to read Port A. The falling edge of the RD input resets IBFA and it goes
low. This can be used to indicate to the peripheral that the input buffer is empty and thatdata can again be loaded
into it.
MODE 1: OUTPUT
The OBFA output (Output Buffer Full) goes low on the rising edge of the WR signal (when the CPU writes data into
the 8255). The OBFA output from 8255 can be used as a strobe input to the peripheral to latch the contents of Port A.
The peripheral responds to the receipt of data by making the ACKA input of the 8255 low, thus acknowledging that it
has received the data sent out by the CPU through Port A. The ACKA low resets the OBFA signal, which can be polled
by the CPU through OBFA of the status word to load the next data when it is high again. INTRA is an active high
output of the 8255 which is made high (if the associated INTE flip-flop is set) when ACKA is made high again by the
peripheral, and when OBFA goes high again (see timing diagram in Figure below). It can be used to interrupt the CPU
whenever the output buffer is empty. It is reset by the falling edge of WR when the CPU writes data onto Port A. It
can be enabled or disabled by writing a '1' or a '0' respectively to PC6 in the BSR mode. INTEB is controlled by writing
a '1' or '0' to PC2 in the BSR mode. The status word is accessed by issuing a Read to Port C.
Interfacing with 8085 Microprocessor
The 8255A is memory-mapped or I/O-mapped into the 8085 system.
Address decoding is used to select the appropriate 8255 port.
Data is transferred through IN and OUT instructions in 8085.
In Mode 1, Port C lines are connected to external devices for handshaking.
Applications
Interfacing keyboards, LEDs, sensors, switches, ADC/DAC.
Controlling stepper motors.
Data acquisition systems.
Real-time signal monitoring.
DISCUSSION AND CONCLUSION
In this lab activity, we interfaced the 8255A Programmable Peripheral Interface (PPI) with the 8085 microprocessor
using Mode 0 and Mode 1 operations. We programmed ports A, B, and C for basic input and output tasks in Mode 0
and explored handshaking and interrupt-driven I/O in Mode 1. The experiment helped us understand the
configuration of the control word register and how data transfer works between the microprocessor and external
devices. This practical exposure strengthened our knowledge of I/O interfacing and demonstrated the flexibility of
the 8255A in managing different types of peripheral communication.
