Bigger Decoder/Encoder using smaller
DFT BASICS COURSE Decoder/Encoder
syllabus(6 weeks) Comparators
Implementing multi bit Comparators using 1-
VLSI Design flow bit Comparator
Specification Sequential logic
RTL coding, lint checks Latch, Flipflop
RTL integration Latch, Flipflop using Gates or Mux’s
Connectivity checks Different types of FFs
Functional Verification FF Truth table
Synthesis & STA Excitation tables
Gate level simulations Realization of FF’s using other FF’s
Power aware simulations Applications of FF’s, Latches
Placement and Routing Counters
DFT Shift registers
Custom layout Synchronizers for clock domain crossing
Post silicon validation FSM’s
Digital Design – Deep dive Mealy, Moore FSM
Combinational logic Different encoding styles
Number systems Frequency dividers
Radix conversions Frequency multiplication
K-maps, min-terms, max terms STA
Logic gates Setup time, Hold time, timing closure
Realization of logic gates using mux’s and fixing setup time and hold time violations
universal gates Launch flop, capture flop
Compliments (1/2/9/10’s complement) Linux operating system
Arithmetic operations using compliments Installing Linux platform in Windows
Boolean expression minimization, Dmorgan Linux basics
theorems Linux versus Windows
POS and SOP Linux Terminal
Conversion and realization File and Directory management
Adders Changing file permissions
Half adder Absolute path and relative path
Full adder Working with directories
Subtractor GVIM – major keyboard shortcuts
Half subtractor Text display commands
Full subtractor Root configuration files
Multiplexers Environment variables
Realizing bigger Mux’s using smaller Mux’s Text processing commands
Implementing Adders and subtractors using grep, fgrep
Multiplexers xargs
Decoders and Encoders SEd
Implementing Decoders and Encoders using AWK
Mux and Demux Pipes and filters
Connecting to server
Process management Clock generation with frequency , Jitter and
LSF duty cycle
Ping Memory coding and test bench setup
FTP Running simulations, analysing waveforms,
CTAGs debugging concepts
File compress and extract DFT main course syllabus (16 weeks)
Soft links Design For Testability (Below is DFT Main
TCL Scripting course weekly schedule)
Introduce TCL DFT Basics
Why TCL? SoC Scan architecture overview
TCL Script Processing Types of Scan
Understand TCL uses and strengths ATPG DRC Debug
Writing simple TCL scripts ATPG Simulation Mismatch Debug
TCL for VLSI scripting DFT Diagnosis
TCL : Main Features JTAG
TCL in EDA MemoryBIST
TCL shell (tclsh) LogicBIST
Working with TCL scripts (UNIX) Scan and ATPG
TCL Interpreter in SoC Design Tools Test compression technigues
TCL Scripting for SoC Design Hierarchical Scan Design
TCL Commands
Variables Week1
Substitution and Command Evaluation Introduction to DFT
Operators Roles in DFT
Mathematical Functions Full SOC flow – DFT
Procedures DFT Architecture and Basics
Control flow : if, if-else, switch, for, foreach, Test Plan
while, break and continue Different DFT schemes
string, string operations Comparison between Functional and DFT
List, List manipulation Vectors
Arrays, array methods Defect, Fault and Error
Working with files Revision of Digital Concepts
Command line arguments Week-2
Regular expressions Understanding of SCAN Insertion
Complete TCL Scripts Scan methodology
TCL Packages Types of Scan
Verilog basics Top-down and Bottom-up Approach
Verilog language constructs Scan insertion Flow
Combinational logic implementation using Scan operation
Verilog Clocking structure relation in SCAN
Testbench coding for combinational logic DFT rule checks – Clock and Reset
Sequential logic implementation using Week-3
Verilog Scan insertion Scripts
Testbench coding for sequential logic Multiple Clock domains
DFT Rule Checks – Advanced (Tristate, PRC, Transition delay faults (TDF)
XS) Path delay faults (PDF)
Precautions for building a proper scan chain Hands-on TDF ATPG
Edge and Domain Mixing significance Week-8
Scan Configurations Types of patterns
Scan chain Balancing Formats of patterns
Lock up and Terminal lockup latches Fault grading
Hands-on Scan insertion LOC , LOS and LOES
Explanation about Netlist and Library files On chip clock control
Assignments Advantages
Week-4 Dis-advantages
Hook-Up Scan sub chains Internal structure
Introduction to compression Week-9
Compression Architecture Introduction to Validation
Decompressor and Compactor Simulations flow
LFSR Tools for simulation
Compression Ratio Simulation mismatches debug
Masking Logic No timing and Timing based Simulations
One hot Decoder Hands-on Simulations
Internal scan chains Week-10
DRC Analysis Flat Models
Scan Reorder Introduction to JTAG/IJTAG
Control signals Introductions to PADS
Week-5 BS Insertion
Modular Compression JTAG/IJTAG FSM
Introduction to Synthesis Instructions of JTAG/IJTAG
Hands-on Compression Week-11
Assignments Introduction to MBIST
ATPG Tools Introduction Memory faults
Fault Models Memory grouping
Fault Categories Memory basics
Algorithms used in ATPG Algorithms
Week-6 Zero-one, CHBK , MATS .MARCH ,SMARCH
ATPG Flow ..etc
Coverage Analysis MBIST Insertion on RTL
Fault Classes Hands on BIST insertion
ATPG DRC’s Assignments
Hands-on Stuck-at ATPG Week-12
Assignments Discussion of Interview questions
Compactor explanation
Week-7 Memory pipelining
Concepts related to STA – Basics ET flow
MCP and FP Hierarchical BIST insertion
Reports of ATPG Hands of multi core MBIST insertion
Sequential Depth Assignments
Week-13
Complete Flow of BIST insertion and
validation
Clock Monitoring
ICL network
EDT and OCC insertion on RTL
Gray box generation
Assignments
Week-14
Introduction to ICL and PDL
Scan Wrapper insertion – Hierarchical Flow
Intest and Extest Hands on Lab sessions
Assignments
ATPG Flow with TSDB
Faults merging
WEEK-15
Controlling PLL and CLK Gen’s using ICL and
PDL
Introduction to BISR
Auxiliary Pins
Revision of JTAG/IJTAG and BIST concepts
WEEK-16
Support for Mock interviews
Interactive sessions
Complete Revision of DFT as follows:
DFT Overview
SCAN
COMPRESSION
OCC
JTAG/IJTAG
MBIST/MBISR
ATPG
SIMULATIONS – ATPG and BIST
Handling third party IP’s for DFT
DFT Insertions in both RTL and NETLIST
Total 4 levels of Projects in the entire course
duration. Each Level contains 5-10 Working
Labs.
