ELECTRIC AND ELECTRONIC ENGINEERING

PROGRAM

GROUP ASSIGNMENT REPORT

SEMESTER II 2022/2023

KE18601: LOGIC DESIGN

TITTLE: TWO BITS FULL ADDER

Group Member Matric Number

Marks
Introduction & Objectives
Experiment
Method
Discussion
Conclusion
Total
Objective:
• To Construct A Two-Bits Full Adder

Introduction

Electronic Device such as computers, calculator and other electronic device often needs to
perform an addition as it is the most basic operation that are crucial for electric circuit.
Electronic device that perform an addition of two or more number or more accurately know
as binary numbers is called as adder. Logic circuit use binary number system to operate the
operation .So the adder is known as binary adder.

There two types of adder which is Half Adders and Full Adders. Half Adder Can only add
two 1-bit binary number , so its sum can only be form the range of 0 to 2. To overcome this
problem ,Full Adder was developed since it can add three 1-bit binary numbers that can range
from 0 to 3. Full adder circuit can add three binary digits where two are the input and the
other one is the carry forwarded from the previous addition.

Source: [Link]

Full Adder can be built using two Half Adders circuit and an OR gate. First Half Adder
consist of two 1-bit binary inputs, which are A and B. The outputs are Sum and Carry.
The Sum output will be then be the first input of the second Half Adder while the Carry
output will be the second input to the extra OR gate.

The second input of the second Half Adder becomes the Carry input (Cin) of the Full Adder.
The second Half Adder will provide Sum and Carry outputs. Its Sum output represents the
Sum output (S) of the Full Adder, and its Carry output is the first input of the additional OR
gate. Finally, the OR gate will generate the Carry output (Cout) of the Full Adder.
 Figure 2: Full Adder Circuit
Source: [Link]

Inputs Outputs
A B Cin S(Sum) Cout(Carry)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 1: Truth Table Of Full Adder

K-Map
Karnaugh map is a method for simplifying binary complex Boolean algebraic expressions.

Table 2: K-Map for Full Adder

Sum, S=A⊕B⊕Cin=A′B′Cin+A′BC′in+AB′C′in+ABCin
Carry,C=AB+ACin+BCin
Steps and Method:
1. The truth table was recognized. The full adder's truth table was recognized . It
displays both the outputs (S and Cout) and all possible input combinations (A, B, and
Cin).

2. Based on the truth table, The logic diagram was designed for the full adder. The logic
diagram consists of logic gates such as AND, OR, and XOR.

3. The XOR gates, was used which are in charge of producing the sum (S), is the first
step. The sum of A and B inputs was calculated with an XOR gate. Interface the data
sources An and B to the XOR entryway, and the result of the XOR door is be the total
(S).

4. The AND gates was used which are responsible for generating the carry-out (Cout).
Two AND gates was needed to calculate the [Link] inputs A and B was
connected to one AND gate, and the inputs B and Cin was connected to the other
AND gate. The outputs of these two AND gates are inputs for a third AND gate. The
output of this third AND gate will be the carry-out (Cout).

5. The OR gate was implemented to combine the carry-out (Cout) from the previous step
with the carry-in (Cin). The inputs Cout and Cin Was connected to the OR gate, and
the output of the OR gate will be the final carry-out (Cout).

6. inputs A, B, and Cin was connected to the full adder [Link] output of the XOR
gate was connected to the sum (S) output, and the output of the OR gate was
connected to the carry-out (Cout) output.

7. The Circuit was tested after the full adder circuit was constructed, it was tested by
providing different combinations of inputs (A, B, and Cin) and verifying that the
outputs (S and Cout) match the expected results from the truth table.
Design

Circuit Schematic diagram

Logic Schematic Diagram

A1 A0 B1 B0 Cin S0 S1 COut

1. 0 0 0 0 0 0 0 0
2. 0 0 0 0 1 0 1 0
3. 0 0 0 1 0 0 1 0
4. 0 0 0 1 1 0 0 1
5. 0 0 1 0 0 1 0 0
6. 0 0 1 0 1 1 1 0
7. 0 0 1 1 0 1 0 0
8. 0 0 1 1 1 1 0 1
9. 0 1 0 0 0 1 0 0
10. 0 1 0 0 1 1 1 0
11. 0 1 0 1 0 1 1 0
12. 0 1 0 1 1 1 0 1
13. 0 1 1 0 0 0 0 0
14. 0 1 1 0 1 0 0 1
15. 0 1 1 1 0 0 0 1
16. 0 1 1 1 1 0 1 0
17. 1 0 0 0 0 1 1 0
18. 1 0 0 0 1 1 0 1
19. 1 0 0 1 0 1 0 1
20. 1 0 0 1 1 1 0 1
21. 1 0 1 0 0 0 1 0
22. 1 0 1 0 1 0 0 1
23. 1 0 1 1 0 0 0 1
24. 1 0 1 1 1 0 1 1
25. 1 1 0 0 0 0 1 0
26. 1 1 0 0 1 0 0 1
27. 1 1 0 1 0 0 0 1
28. 1 1 0 1 1 0 1 1
29. 1 1 1 0 0 0 1 0
30. 1 1 1 0 1 1 0 1
31. 1 1 1 1 0 0 0 1
32. 1 1 1 1 1 1 1 1
K-Map For Full Adders Circuit

S0
A1B2 00 01 11 10
A0B0
00 0 1 0 1
01 0 1 0 1
11 1 0 0 0
10 1 0 0 0

S1

A1B2 00 01 11 10
A0B0
00 0 0 1 0
01 1 0 1 0
11 1 1 1 0
10 0 0 0 0

Cout

A1B2 00 01 11 10
A0B0
00 0 0 0 0
01 1 1 1 1
11 0 1 1 1
10 0 1 1 1

Boolean Expression:
S0 = (A0 ⊕ B0) ⊕ Cin
S1= [(A0 ⊕ B0) + (A0 x B0)] ⊕(A1 + B1)
Cout=[ ((A0 ⊕ B0)+ (A0.B0)) x (A1 ⊕ B1)] + (A1 x B1)
Discussion
From this project we can learn that constructing a full adder requires quite a many steps that
needs to be done carefully . First of all, we need to understand the truth table for the adder
because truth table show all possible input combination that we need to know and the outputs.
After then, the required logic gates can be determined based on the logic relationship that we
analyze.

The Logic diagram design then can be made after identify the necessary logic gates and
apparatus to get the desired output. But, the logic gates must be arrange in a logical sequence
to ensure correct signal propagation and computation.

After verifying all the things needed, then we can construct the circuit physically. After the
circuit was done . Testing and verification needs to be done by applying different input
combination (A,B,Cin) and observe whether the output is the same as the desired one. Make
sure to verify the circuit with various of input combination to ensure the circuits functionality.

Last but not least, we need to asses the performance of the circuit in terms of speed and
power consumption. The propagation delay between input changes and the corresponding
output was measured to identify areas for improvement in the full adder circuit.

Conclusion
Constructing a full adder involves comprehending its truth table, designing a logic diagram,
implementing the required logic gates, and verifying the circuit's functionality. This lab report
presented the step-by-step process of constructing a full adder, highlighting the crucial design
considerations and testing procedures. The successful construction of the full adder provides
a solid foundation in digital circuit design and lays the groundwork for more complex
arithmetic circuits in the field of digital electronics.