Digital System Design using VHDL
Course Syllabus (45 Hours)
Course Overview
This course provides comprehensive coverage of digital system design using VHDL (VHSIC Hardware
Description Language). Students will learn to design, simulate, and implement digital systems ranging
from basic logic circuits to complex digital processors.
Total Duration: 45 Hours
Distribution: 5 Units × 9 Hours each
Unit 1: Introduction to Digital Systems and VHDL Fundamentals (9 Hours)
Topics Covered:
Digital System Design Methodology (1.5 hours)
Top-down vs bottom-up design approaches
Hardware description languages overview
Design flow and verification process
Introduction to VHDL (2 hours)
History and evolution of VHDL
VHDL design methodology
Comparison with other HDLs (Verilog, SystemVerilog)
VHDL design hierarchy
VHDL Language Basics (3.5 hours)
VHDL syntax and structure
Entities and architectures
Libraries and packages
Data types and objects
Operators and expressions
Basic VHDL Constructs (2 hours)
Signal assignment statements
Variable assignments
Process statements
Concurrent vs sequential statements
Learning Outcomes:
Understand digital system design principles
Write basic VHDL code structures
Differentiate between concurrent and sequential statements
Unit 2: VHDL Modeling Techniques and Combinational Logic (9 Hours)
Topics Covered:
VHDL Modeling Styles (2 hours)
Behavioral modeling
Dataflow modeling
Structural modeling
Mixed modeling approaches
Combinational Logic Design (3.5 hours)
Logic gates implementation
Boolean function realization
Multiplexers and demultiplexers
Encoders and decoders
Comparators
Advanced Combinational Circuits (2.5 hours)
Arithmetic circuits (adders, subtractors)
ALU design
Code converters
Parity generators and checkers
Simulation and Testing (1 hour)
Writing testbenches
Simulation techniques
Debugging VHDL code
Learning Outcomes:
Design combinational logic circuits using VHDL
Implement different modeling styles
Create and execute testbenches
Unit 3: Sequential Logic and State Machine Design (9 Hours)
Topics Covered:
Sequential Logic Fundamentals (2 hours)
Flip-flops and latches in VHDL
Clock and reset concepts
Synchronous vs asynchronous designs
Edge detection and clock domains
Sequential Circuit Design (3 hours)
Counters (binary, BCD, ring, Johnson)
Shift registers
Sequence generators and detectors
Memory elements
Finite State Machines (FSM) (3.5 hours)
Moore and Mealy machines
State encoding techniques
FSM design methodology
State diagram to VHDL conversion
Advanced Sequential Concepts (0.5 hours)
Hierarchical state machines
FSM optimization techniques
Learning Outcomes:
Design sequential logic circuits
Implement various types of state machines
Apply proper clocking and reset strategies
Unit 4: Advanced VHDL Features and Memory Systems (9 Hours)
Topics Covered:
Advanced VHDL Constructs (3 hours)
Procedures and functions
Packages and libraries
Generic and port maps
Configuration declarations
Memory System Design (3.5 hours)
RAM and ROM modeling
Single-port and dual-port memories
FIFO and LIFO implementations
Memory controllers
Interfacing and Communication (1.5 hours)
Bus protocols and interfaces
Serial communication (UART, SPI)
Handshaking protocols
Design for Testability (1 hour)
Built-in self-test (BIST) basics
Testbench strategies
Learning Outcomes:
Utilize advanced VHDL features for complex designs
Design memory systems and interfaces
Implement testable digital systems
Unit 5: System-Level Design and Implementation (9 Hours)
Topics Covered:
Microprocessor Design (3 hours)
Simple CPU architecture
Instruction set design
Datapath and control unit implementation
Digital Signal Processing (2 hours)
FIR filter implementation
DSP building blocks
Fixed-point arithmetic
FPGA Implementation (3 hours)
FPGA architecture overview
Synthesis considerations
Place and route concepts
Timing constraints
Case Studies and Applications (1 hour)
Real-world design examples
Industry design practices
Design reuse methodologies
Learning Outcomes:
Design complete digital systems
Understand FPGA implementation flow
Apply VHDL to practical applications
Assessment Methods:
Continuous Assessment: 40%
Lab assignments and exercises
Quizzes and short tests
Project milestones
Major Projects: 35%
Mid-term project (combinational/sequential design)
Final project (complete system design)
Final Examination: 25%
Theory and practical problem solving
VHDL code analysis and debugging
Laboratory Requirements:
VHDL simulator (ModelSim, GHDL, or Vivado)
FPGA development board (recommended)
Synthesis tools
Waveform viewers
Prerequisites:
Digital Electronics
Boolean Algebra and Logic Design
Basic Programming Knowledge
Recommended Textbooks:
1. "VHDL: Programming by Example" by Douglas Perry
2. "Digital Design and Computer Architecture" by Harris & Harris
3. "RTL Hardware Design Using VHDL" by Pong Chu
4. "Advanced Digital Design with the Verilog HDL" by Michael Ciletti
Software Tools:
Xilinx Vivado Design Suite
Intel Quartus Prime
ModelSim/QuestaSim
GHDL (Open Source)
This syllabus is designed to provide comprehensive coverage of digital system design using VHDL,
progressing from basic concepts to advanced system-level implementation.
