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Code Shift Registers

The document describes the design and testbench for several digital circuits including SIPO, SISO, and PIPO modules. Each module is defined with its inputs, outputs, and behavior during clock cycles, along with testbench implementations to verify their functionality. The testbenches simulate the modules' operations by toggling signals and observing outputs.

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Raksha RK
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15 views3 pages

Code Shift Registers

The document describes the design and testbench for several digital circuits including SIPO, SISO, and PIPO modules. Each module is defined with its inputs, outputs, and behavior during clock cycles, along with testbench implementations to verify their functionality. The testbenches simulate the modules' operations by toggling signals and observing outputs.

Uploaded by

Raksha RK
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

SIPO #10 si = 1;

Design: #10 si = 0;
module sipo(clk, si, po, #10 si = 1;
reset); #10 si = 1;
input clk, si, reset; #10 si = 0;
output [7:0]po; #10 si = 1;
reg [7:0] temp; #10 si = 0;
#10 si = 1;
always@(posedge clk)begin #20;
if (reset) $finish;
temp <= 8'b0; end
else
temp <= {temp[6:0],si}; endmodule
end
assign po = temp; SISO
endmodule Design:
module siso(clk,clear, si, so,
Testbench: q);
module tb_sipo; input clk,clear,si;
output reg[3:0]q;
reg clk, si, reset; output so;
wire [7:0] po; always@(posedge
clk)begin
sipo uut ( if(clear == 1)
.clk(clk), q <= 4'b0;
.si(si), else begin
.po(po), q <= q>>1;
.reset(reset) q[3] <= si;
); end
end
initial begin assign so = q[0];
clk = 0; endmodule
forever #5 clk = ~clk;
end Testbench:
module tb_siso;
reg clk, clear, si;
initial begin wire [3:0] q;
reset = 1'b1; #11 wire so;
reset = 1'b0;
si = 0; siso uut (
.clk(clk),
.clear(clear), Testbench:
.si(si), module tb_pipo;
.q(q), reg clk;
.so(so) reg [3:0]pi;
); wire [3:0]po;

initial begin pipo uut(clk, pi, po);


clk = 0;
forever #5 clk = ~clk; initial begin
end clk = 0;
forever #5 clk = ~clk;
initial begin end
clear = 1;
si = 0; initial begin
#10; pi = 4'b0000;
clear = 0; #10 pi = 4'b1010;
si = 1; #10; #10 pi = 4'b0101;
si = 0; #10; #10 pi = 4'b1111;
si = 1; #10; #10 pi = 4'b0001;
si = 1; #10 #10 $finish;
clear = 1; #10; end
clear = 0;
si = 0; #10; endmodule
si = 1; #10;
#20; PISO
$finish;
Deisgn:
end
module piso(clk, pi, load,
endmodule
so);
input clk, load;
PIPO input [3:0]pi;
Design: output reg so;
module pipo(clk, pi, po); reg [3:0] temp;
input clk;
input [3:0]pi; always@(posedge clk)begin
output reg [3:0]po; if(load)
always@(posedge clk)begin temp <= pi;
po = pi; else begin
end so <= temp[3];
endmodule
temp <=
{temp[2:0], 1'b0};
end
end
endmodule

Testbench:
module tb_piso;
reg clk, load;
reg [3:0] pi;
wire so;

piso uut (
.clk(clk),
.pi(pi),
.load(load),
.so(so)
);

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
load = 0;
pi = 4'b0000;
#7 pi = 4'b1101;
load = 1;
#10 load = 0;
#40;
pi = 4'b1010;
load = 1;
#10 load = 0;
#40;
#10 $finish;
end
endmodule

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