Cache Memory – Notes
What is Cache Memory?
• Cache is a small, fast memory located close to the CPU.
• It stores frequently accessed data or instructions to speed up processing.
• Main purpose: Reduce the time to access data from main memory (RAM).
Key Concepts
Cache Hit
• When the CPU finds the requested data in the cache.
• Fast and efficient.
• Example: CPU asks for data at address 0x10 and cache already has it → Hit.
Cache Miss
• When the data requested by the CPU is not in the cache.
• Cache must fetch it from main memory → Slower.
• After fetching, cache may store the data for future use.
Reasons for Cache Miss:
1. Compulsory Miss (Very First Read)
a. First time the data is accessed → not in cache.
2. Capacity Miss (Read from Different Address)
a. Too many blocks accessed → cache size not enough.
3. Conflict Miss (Very Far from Previous Location)
a. Multiple data maps to the same cache location → causes replacement.
Write Operations
Write-Through
• Data is written to both cache and main memory at the same time.
• Simple but slower.
• Data in memory is always up to date.
Write-Back
• Data is written only to cache initially.
• Updated in memory later when that cache line is replaced.
• Faster, but memory may be outdated temporarily.
Cache Coherency
• Problem occurs in multi-core systems when multiple cores have their own cache.
• If one core updates data, other cores might have old data.
• Cache coherency ensures all caches reflect the most recent written data.
Coherency Protocols
MOSI Protocol
• Each cache block can be in one of 4 states:
o Modified (M): Block is dirty (changed) and only in this cache.
o Owned (O): Block is dirty but may be shared with others; this cache is
responsible for writing it back.
o Shared (S): Block is clean and shared across multiple caches.
o Invalid (I): Block is not valid anymore.
MOESI Protocol (Extension of MOSI)
• Adds an extra state:
5. Exclusive (E): Block is clean and only present in this cache.
• It helps avoid unnecessary write-backs and bus traffic.
Important Cache States
State Meaning
Unique Clean Data is only in this cache and same as in memory (not modified).
Unique Dirty Data is only in this cache and has been modified (different from memory).
Shared Clean Data is in multiple caches and matches main memory.
Shared Dirty Data is in multiple caches, and at least one has modified it (rare state).
In MOESI, owned = Shared Dirty → one cache "owns" the latest dirty copy.
Summary
Concept Short Note
Cache Hit Data found in cache → Fast.
Cache Miss Data not in cache → Fetch from memory (slow).
Write-Through Update both cache & memory instantly.
Write-Back Update cache now, memory later (on eviction).
Cache Coherency Keeps data consistent across caches in multi-cores.
MOESI/MOSI Protocols that manage cache states.
