TMP75B-Q1

SBOS721B – OCTOBER 2014 – REVISED OCTOBER 2024

TMP75B-Q1 1.8V Digital Temperature Sensor With Two-Wire Interface and Alert
1 Features 3 Description
• Qualified for automotive applications The TMP75B-Q1 is an integrated digital temperature
• AEC-Q100 qualified with the following results: sensor with a 12-bit analog-to-digital converter (ADC)
– Temperature grade 1: –40°C to 125°C that can operate at a 1.8V supply, and is pin and
– HBM ESD classification 2 register compatible with the industry-standard LM75
– CDM ESD classification C4B and TMP75. This device is available in SOIC-8
• Tri-Temp tested option: TMP75BTQDGKRQ1 and VSSOP-8 packages, and requires no external
• Functional Safety-Capable components to sense the temperature. The TMP75B-
– Documentation available to aid functional safety Q1 is capable of reading temperatures with a
system design resolution of 0.0625°C with operating temperature
• Digital output with two-wire serial interface range of –40°C to 125°C. The TMP75BTQDGKRQ1
• Up to eight pin-programmable bus addresses is tri-temperature (–40°C, 25°C, and 125°C) tested in
• Programmable overtemperature ALERT production for improved robustness.
• Shutdown mode for power saving The TMP75B-Q1 features SMBus and two-wire
• One-shot conversion mode interface compatibility, and allows up to eight devices
• Operating temperature range: –40°C to 125°C on the same bus with the SMBus overtemperature
• Operating supply range: 1.4V to 3.6V alert function. The programmable temperature limits
• Quiescent current: and the ALERT pin allow the sensor to operate
– 45μA Active (typical) as a stand-alone thermostat, or an overtemperature
– 0.3μA Shutdown (typical) alarm for power throttling or system shutdown.
• Accuracy: The factory-calibrated temperature accuracy and the
– ±0.5°C (typical) from –20°C to 85°C noise-immune digital interface make the TMP75B-Q1
– ±1°C (typical) from –40°C to 125°C the preferred solution for temperature compensation
• Resolution: 12 bits (0.0625°C) of other sensors and electronic components. The
• Packages: SOIC-8 and VSSOP-8 TMP75B-Q1 is designed for thermal management and
protection of a variety of automotive applications, and
2 Applications is a high-performance alternative to a PCB-mounted
• Autonomous driving module thermistor.
• Media hub & display Package Information
• Head & digital cockpit unit DEVICE NAME PACKAGE (1) PACKAGE SIZE(2)
• Smart telematics & gateway
TMP75BQDRQ1 D (SOIC, 8) 4.9mm × 6mm
• ADAS domain controller & sensor fusion
• Body control module TMP75BQDGKRQ1 DGK (VSSOP, 8) 3mm × 4.9mm
• Onboard charger TMP75BTQDGKRQ1
• Battery system
1.4 V to 3.6 V
(1) For all available packages, see Section 12.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
3

0.01 PF
2
Temperature Error (ƒC)

TMP75B-Q1
1
1 8
SDA VS
0
2 7
Two-Wire SCL A0
±1
Host Controller
3 6 Mean
ALERT A1 ±2
Mean - 61
Mean + 61
4 5 ±3
GND A2
±75 ±50 ±25 0 25 50 75 100 125 150
Temperature (ƒC) C005

Simplified Schematic Temperature Accuracy (Error) vs Ambient

Temperature

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.5 Programming............................................................ 16
2 Applications..................................................................... 1 8 Register Map.................................................................. 17
3 Description.......................................................................1 9 Application and Implementation.................................. 19
4 Device Comparison......................................................... 3 9.1 Application Information............................................. 19
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 20
6 Specifications.................................................................. 4 9.3 Power-Supply Recommendations.............................21
6.1 Absolute Maximum Ratings........................................ 4 9.4 Layout....................................................................... 21
6.2 ESD Ratings............................................................... 4 10 Device and Documentation Support..........................23
6.3 Recommended Operating Conditions.........................4 10.1 Documentation Support.......................................... 23
6.4 Thermal Information....................................................4 10.2 Receiving Notification of Documentation Updates..23
6.5 Electrical Characteristics.............................................5 10.3 Support Resources................................................. 23
6.6 Timing Requirements.................................................. 6 10.4 Trademarks............................................................. 23
6.7 Typical Characteristics................................................ 7 10.5 Electrostatic Discharge Caution..............................23
7 Detailed Description........................................................8 10.6 Glossary..................................................................23
7.1 Overview..................................................................... 8 11 Revision History.......................................................... 23
7.2 Functional Block Diagram........................................... 8 12 Mechanical, Packaging, and Orderable
7.3 Feature Description.....................................................9 Information.................................................................... 23
7.4 Device Functional Modes..........................................15

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4 Device Comparison
Table 4-1. Device Comparison
Device Package Production Test Condition
TMP75BQDRQ1 D (SOIC, 8 pin) Room Temp (25°C)
TMP75BQDGKRQ1 DGK (VSSOP, 8 pin)
TMP75BTQDGKRQ1 DGK (VSSOP, 8 pin) Tri-temp (–40°C, 25°C, and 125°C)

5 Pin Configuration and Functions

SDA 1 8 VS

SCL 2 7 A0

ALERT 3 6 A1

GND 4 5 A2

Figure 5-1. D and DGK Packages 8-Pin SOIC and 8-Pin VSSOP (Top View)

Table 5-1. Pin Functions

PIN
Type(1) DESCRIPTION
NAME NO.
A0 7 I Address select. Connect to GND or VS.
A1 6 I Address select. Connect to GND or VS.
A2 5 I Address select. Connect to GND or VS.
ALERT 3 O Overtemperature alert. Open-drain output; requires a pullup resistor.
GND 4 G Ground
SCL 2 I Serial clock
SDA 1 I/O Serial data. Open-drain output; requires a pullup resistor.
VS 8 I Supply voltage, 1.4V to 3.6V

(1) I = input, O = output, I/O = input or output, and G = ground

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6 Specifications
6.1 Absolute Maximum Ratings
Over free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage 4 V
SDA, SCL, ALERT, A2, A1 –0.3 4 V
VI/O I/O voltage (VS) +
A0 –0.3 V
0.3
ISINK Sink current SDA, ALERT 10 mA
TJ Operating junction temperature –55 150 °C
Tstg Storage temperature range –60 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per AEC Q100-002(1) –2000 2000 V
V(ESD) Electrostatic discharge Charged device model (CDM), per Corner pins (1, 4, 5, and 8) –1000 1000 V
AEC Q100-011 Other pins –1000 1000 V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage 1.4 1.8 3.6 V
Operating free-air temperature, TA -40 125 °C

6.4 Thermal Information

TMP75BQDGK TMP75BTQDG
TMP75BQDRQ1
RQ1 KRQ1
THERMAL METRIC(1) UNIT
D (SOIC) DGK (VSSOP) DGK (VSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 125.4 188.1 188.1
RθJC(top) Junction-to-case (top) thermal resistance 71.5 79.1 79.1
RθJB Junction-to-board thermal resistance 65.8 109.6 109.6
°C/W
ψJT Junction-to-top characterization parameter 21.1 15.3 15.3
ψJB Junction-to-board characterization parameter 65.3 108 108
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

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6.5 Electrical Characteristics

At TA = –40°C to 125°C and VS = 1.4 V to 3.6 V, unless otherwise noted. Typical values at TA = 25°C and VS = 1.8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE SENSOR
Temperature Range -40 125 °C
Temperature resolution 0.0625 °C

TMP75BQDGKRQ1 –20°C to 85°C ±0.5 ±2 °C

Temperature accuracy TMP75BQDRQ1 –40°C to 125°C ±1 ±3 °C
(error)
TMP75BTQDGKRQ1 –40°C to 125°C ±0.5 ±2 °C
DIGITAL INPUT/OUTPUT
VIH High-level input voltage 0.7(VS) VS V
VIL Low-level input voltage –0.3 0.3(VS) V
IIN Input current 0 V< VIN < (VS) + 0.3 V 1 μA
VOL VS ≥ 2 V, IOUT = 3 mA 0 0.4 V
Low-level output voltage
VOL VS < 2 V, IOUT = 3 mA 0 0.2(VS) V
ADC resolution 12 Bits
Conversion time One-shot mode 20 27 35 ms
Conversion modes CR1 = 0, CR0 = 0 (default) 37 Conv/s
CR1 = 0, CR0 = 1 18 Conv/s
CR1 = 1, CR0 = 0 9 Conv/s
CR1 = 1, CR0 = 1 4 Conv/s
Timeout time 38 54 70 ms
POWER SUPPLY
Operating supply range 1.4 3.6 V
Serial bus inactive, CR1 = 0, CR0 = 0 (default) 45 89 μA
Serial bus inactive, CR1 = 0, CR0 = 1 22 48 μA
IQ Quiescent current
Serial bus inactive, CR1 = 1, CR0 = 0 12 30 μA
Serial bus inactive, CR1 = 1, CR0 = 1 6.5 21 μA
Serial bus inactive 0.3 8 μA
ISD Shutdown current Serial bus active, SCL frequency = 400 kHz 10 μA
Serial bus active, SCL frequency = 3.4 MHz 80 μA

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6.6 Timing Requirements

STANDARD FAST-MODE
UNIT
Min Max Min Max
VS ≥ 1.8 V 0.001 0.4 0.001 3 MHz
fSCL SCL operating frequency
VS < 1.8 V 0.001 0.4 0.001 2.5 MHz

Bus-free time between STOP and VS ≥ 1.8 V 1300 160 ns

t(BUF)
START conditions VS < 1.8 V 1300 260 ns
Hold time after repeated START condition.
t(HDSTA) 600 160 ns
After this period, the first clock is generated.
t(SUSTA) Repeated START condition setup time 600 160 ns
t(SUSTO) STOP condition setup time 600 160 ns
VS ≥ 1.8 V 0 900 0 100 ns
t(HDDAT) Data hold time
VS < 1.8 V 0 900 0 140 ns
VS ≥ 1.8 V 100 10 ns
t(SUDAT) Data setup time
VS < 1.8 V 100 20 ns
VS ≥ 1.8 V 1300 190 ns
t(LOW) SCL clock low period
VS < 1.8 V 1300 240 ns
t(HIGH) SCL clock high period 600 60 ns
tR(SDA),
Data rise and fall time 300 80 ns
tF(SDA)
tR(SCL),
Clock rise and fall time 300 40 ns
tF(SCL)
tR Clock and data rise time for SCLK ≤ 100 kHz 1000 ns

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6.7 Typical Characteristics

At TA = 25°C and VS = 1.8V (unless otherwise noted).

100 10
CR = '0h' Vs = 1.4V
90 CR = '1h' 9
Vs = 1.8V
80 CR = '2h' 8
CR = '3h' Vs = 3.6V
70 7
60 6

ISD ( A)
IQ ( A)

50 5
40 4
30 3
20 2
10 1
0 0
±75 ±50 ±25 0 25 50 75 100 125 150 ±75 ±50 ±25 0 25 50 75 100 125 150
Temperature (ƒC) C001 Temperature (ƒC) C002

Figure 6-1. Quiescent Current vs Temperature Figure 6-2. Shutdown Current vs Temperature
30 200
Ta = - Û&
29 175 7D Û&
28 7D Û&
150
Conversion Time (ms)

27
26 125
IQ ( A)

25 100
24 75
23
Vs = 1.4V 50
22
Vs = 1.8V 25
21
Vs = 3.6V
20 0
±75 ±50 ±25 0 25 50 75 100 125 150 10 100 1000 10000
Temperature (ƒC) C003 Bus Frequency (kHz) C004

Figure 6-3. Conversion Time vs Temperature Figure 6-4. Quiescent Current vs Bus Frequency
3

2
Temperature Error (ƒC)

1
Population

±1

Mean
±2
Mean - 61
Mean + 61
±3
0

1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1

±75 ±50 ±25 0 25 50 75 100 125 150

Temperature (ƒC) C005 Temperature Error (ƒC)
Figure 6-5. Temperature Error vs Temperature C006

Figure 6-6. Temperature Error at 25°C

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7 Detailed Description
7.1 Overview
The TMP75B-Q1 is a digital temperature sensor optimal for thermal management and thermal protection
applications. The TMP75B-Q1 is two-wire and SMBus interface compatible, and is specified over a temperature
range of –40°C to 125°C. The TMP75BTQDGKRQ1 is tri-temperature (–40°C, 25°C, and 125°C) tested in
production for improved robustness.
The temperature sensing device for the TMP75B-Q1 is the chip. A bipolar junction transistor (BJT) inside the
chip is used in a band-gap configuration to produce a voltage proportional to the chip temperature. The voltage
is digitized and converted to a 12-bit temperature result in degrees Celsius, with a resolution of 0.0625°C. The
package leads provide the primary thermal path because of the lower thermal resistance of the metal. Thus, the
temperature result is equivalent to the local temperature of the printed circuit board (PCB) where the sensor is
mounted.
7.2 Functional Block Diagram
VS

Device

Voltage Regulator Register Bank Oscillator

SDA
Serial Interface Control Logic
SCL

A0 I NxI ALERT

A1

A2
ADC

Thermal
BJT

GND

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7.3 Feature Description

7.3.1 Digital Temperature Output
The 12-bit digital output from each temperature measurement conversion is stored in the read-only temperature
register. Two bytes must be read to obtain the data; see Figure 8-2. Note that byte 1 is the most significant byte,
followed by byte 2, the least significant byte. The temperature result is left-justified with the 12 most significant
bits used to indicate the temperature. There is no need to read the second byte if resolution below 1°C is not
required. Table 7-1 summarizes the temperature data format. One LSB equals 0.0625°C. Negative numbers are
represented in binary 2's complement format.
Table 7-1. Temperature Data Format
DIGITAL OUTPUT
TEMPERATURE (°C) (1) BINARY HEX
128 0111 1111 1111 7FF
127.9375 0111 1111 1111 7FF
100 0110 0100 0000 640
80 0101 0000 0000 500
75 0100 1011 0000 4B0
50 0011 0010 0000 320
25 0001 1001 0000 190
0.25 0000 0000 0100 004
0 0000 0000 0000 000
–0.25 1111 1111 1100 FFC
–25 1110 0111 0000 E70
–55 1100 1001 0000 C90

(1) The temperature sensor resolution is 0.0625°C/LSB.

Table 7-1 does not supply a full list of all temperatures. Use the following rules to obtain the digital data format
for a given temperature, and so forth.
To convert positive temperatures to a digital data format:
Divide the temperature by the resolution. Then, convert the result to binary code with a 12-bit, left-justified
format, and MSB = 0 to denote a positive sign.
Example: (50°C) / (0.0625°C / LSB) = 800 = 320h = 0011 0010 0000
To convert a positive digital data format to temperature:
Convert the 12-bit, left-justified binary temperature result, with the MSB = 0 to denote a positive sign, to a
decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature.
Example: 0011 0010 0000 = 320h = 800 × (0.0625°C / LSB) = 50°C
To convert negative temperatures to a digital data format:
Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a
12-bit, left-justified format. Then, generate the 2's complement of the result by complementing the binary number
and adding one. Denote a negative number with MSB = 1.
Example: (|–25°C|) / (0.0625°C / LSB) = 400 = 190h = 0001 1001 0000
Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000
To convert a negative digital data format to temperature:
Generate the 2's compliment of the 12-bit, left-justified binary number of the temperature result (with MSB = 1,
denoting negative temperature result) by complementing the binary number and adding one. This represents

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the binary number of the absolute value of the temperature. Convert to decimal number and multiply by the
resolution to get the absolute temperature, then multiply by –1 for the negative sign.
Example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1
Convert to temperature: 0001 1001 0000 = 190h = 400; 400 × (0.0625°C / LSB) = 25°C = (|–25°C|); (|–25°C|) ×
(–1) = –25°C
7.3.2 Temperature Limits and Alert
The temperature limits are stored in the TLOW and THIGH registers (Table 8-4 and Table 8-5) in the same format
as the temperature result, and the values are compared to the temperature result on every conversion. The
outcome of the comparison drives the behavior of the ALERT pin, which can operate as a comparator output or
an interrupt, and is set by the TM bit in the configuration register (Table 8-3).
In comparator mode (TM = 0, default), the ALERT pin becomes active when the temperature is equal to or
exceeds the value in THIGH (fault conditions) for a consecutive number of conversions as set by the FQ bits
of the configuration register. ALERT clears when the temperature falls below TLOW for the same consecutive
number of conversions. The difference between the two limits acts as a hysteresis on the comparator output,
and a fault counter prevents false alerts as a result of environmental noise.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value
in THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of
any register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin
is also cleared if the device is placed in shutdown mode (see the Shutdown Mode section for shutdown mode
description). After the ALERT pin is cleared, this pin becomes active again only when the temperature falls
below TLOW for a consecutive number of fault conditions, and remains active until cleared by a read operation
of any register, or a successful response to the SMBus alert response address. After the ALERT pin is cleared,
the cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH, and so
on. The ALERT pin can also be cleared by resetting the device with the general-call reset command. This action
also clears the state of the internal registers in the device and the fault counter memory, returning the device to
comparator mode (TM = 0).
The active state of the ALERT pin is set by the POL bit in the configuration register. When POL = 0 (default), the
ALERT pin is active low. When POL = 1, the ALERT pin is active high. The operation of the ALERT pin in various
modes is shown in Figure 7-1.

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THIGH
Measured
Temperature

TLOW

Device ALERT PIN

(Comparator Mode)
POL = 0
Device ALERT PIN
(Interrupt Mode)
POL = 0
Device ALERT PIN
(Comparator Mode)
POL = 1
Device ALERT PIN
(Interrupt Mode)
POL = 1

Read Read Read

Time

Figure 7-1. ALERT Pin Modes of Operation

7.3.3 Serial Interface

The TMP75B-Q1 operates as a target device only on the two-wire bus and SMBus. Connections to the bus
are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-
suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP75B-Q1
supports the transmission protocol for both fast (1kHz to 400kHz) and high-speed (1kHz to 3MHz) modes. All
data bytes are transmitted MSB first.
7.3.3.1 Bus Overview
The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets.
The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access,
and generates the start and stop conditions.
To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic
level while SCL is high. All targets on the bus shift in the target address byte; the last bit indicates whether
a read or write operation follows. During the ninth clock pulse, the target being addressed responds to the
controller by generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted
as a start or stop signal.
After all data have been transferred, the controller generates a stop condition indicated by pulling SDA from low
to high, while SCL is high.
7.3.3.2 Serial Bus Address
To communicate with the TMP75B-Q1, the controller must first communicate with target devices using a target
address byte. The target address byte consists of seven address bits, and a direction bit indicating the intent of
executing either a read or write operation. The TMP75B-Q1 features three address pins that allow up to eight
devices to be addressed on a single bus. The TMP75B-Q1 latches the status of the address pins at the start of a
communication. Table 7-2 describes the pin logic levels and the corresponding address values.

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Table 7-2. Address Pin Connections and Target Addresses

DEVICE TWO-WIRE ADDRESS A2 A1 A0
1001000 GND GND GND
1001001 GND GND VS
1001010 GND VS GND
1001011 GND VS VS
1001100 VS GND GND
1001101 VS GND VS
1001110 VS VS GND
1001111 VS VS VS

7.3.3.3 Writing and Reading Operation

Accessing a particular register on the TMP75B-Q1 is accomplished by writing the appropriate value to the
pointer register. The value for the pointer register is the first byte transferred after the target address byte with
the R/W bit low. Every write operation to the TMP75B-Q1 requires a value for the pointer register (see Figure
7-3).
When reading from the TMP75B-Q1, the last value stored in the pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the pointer register. This action is accomplished by issuing a target address byte with
the R/W bit low, followed by the pointer register byte. No additional data are required. The controller can then
generate a start condition and send the target address byte with the R/W bit high to initiate the read command.
See Figure 7-4 for details of this sequence. If repeated reads from the same register are desired, there is no
need to continually send the pointer register bytes because the TMP75B-Q1 stores the pointer register value
until the value is changed by the next write operation.
Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
7.3.3.4 Target-Mode Operations
The TMP75B-Q1 can operate as a target receiver or target transmitter.
7.3.3.4.1 Target Receiver Mode:
The first byte transmitted by the controller is the target address, with the R/W bit low. The TMP75B-Q1 then
acknowledges reception of a valid address. The next byte transmitted by the controller is the pointer register.
The TMP75B-Q1 then acknowledges reception of the pointer register byte. The next byte or bytes are written to
the register addressed by the pointer register. The TMP75B-Q1 acknowledges reception of each data byte. The
controller can terminate data transfer by generating a start or stop condition.
7.3.3.4.2 Target Transmitter Mode:
The first byte transmitted by the controller is the target address, with the R/W bit high. The target acknowledges
reception of a valid target address. The next byte is transmitted by the target and is the most significant byte of
the register indicated by the pointer register. The controller acknowledges reception of the data byte. The next
byte transmitted by the target is the least significant byte. The controller acknowledges reception of the data
byte. The controller can terminate data transfer by generating a not-acknowledge bit on reception of any data
byte, or by generating a start or stop condition.
7.3.3.5 SMBus Alert Function
The TMP75B-Q1 supports the SMBus alert function. When the TMP75B-Q1 operates in interrupt mode (TM = 1),
the ALERT pin can be connected as an SMBus alert signal. When a controller senses that an alert condition is
present on the ALERT line, the controller sends an SMBus alert command (00011001) to the bus. If the ALERT
pin is active, the device acknowledges the SMBus alert command and responds by returning the target address
on the SDA line. The eighth bit (LSB) of the target address byte indicates whether the alert condition is caused
by the temperature exceeding THIGH or falling below TLOW. The LSB is high if the temperature is greater than
THIGH, or low if the temperature is less than TLOW. See Figure 7-5 for details of this sequence.

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If multiple devices on the bus respond to the SMBus alert command, arbitration during the target address portion
of the SMBus alert command determines which device clears the alert status first. If the TMP75B-Q1 wins the
arbitration, the ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP75B-Q1
loses the arbitration, the ALERT pin remains active.
7.3.3.6 General Call
The TMP75B-Q1 responds to a two-wire general call address (0000000) if the eighth bit is 0. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000100, the TMP75B-Q1 latches the status of the address pin, but does not reset. If the second byte is
00000110, the TMP75B-Q1 internal registers are reset to power-up values.
7.3.3.7 High-Speed (Hs) Mode
For the two-wire bus to operate at frequencies above 400kHz, the controller device must issue an SMBus
Hs-mode controller code (00001xxx) as the first byte after a start condition to switch the bus to high-speed
operation. The TMP75B-Q1 does not acknowledge this byte, but does switch the input filters on SDA and SCL
and the output filters on SDA to operate in Hs-mode, allowing transfers at up to 3MHz. After the Hs-mode
controller code has been issued, the controller transmits a two-wire target address to initiate a data-transfer
operation. The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the
stop condition, the TMP75B-Q1 switches the input and output filters back to fast-mode operation.
7.3.3.8 Timeout Function
The TMP75B-Q1 resets the serial interface if SCL or SDA are held low for 54ms (typical) between a start and
stop condition. If the TMP75B-Q1 is pulled low, the device releases the bus and then waits for a start condition.
To avoid activating the timeout function, maintaining a communication speed of at least 1kHz is necessary for the
SCL operating frequency.
7.3.3.9 Two-Wire Timing
The TMP75B-Q1 is two-wire and SMBus compatible. Figure 7-2 to Figure 7-5 describe the various operations on
the TMP75B-Q1. Parameters for Figure 7-2 are defined in Section 6.6. Bus definitions are:

Bus Idle Both SDA and SCL lines remain high.

Start Data A change in the state of the SDA line, from high to low, while the SCL line is high defines a
Transfer start condition. Each data transfer is initiated with a start condition.
Stop Data A change in the state of the SDA line from low to high while the SCL line is high defines a
Transfer stop condition. Each data transfer is terminated with a repeated start or stop condition.
Data Transfer The number of data bytes transferred between a start and a stop condition is not limited,
and is determined by the controller device.
The receiver acknowledges the transfer of data. Using the TMP75B-Q1 for single-byte
updates is also possible. To update only the MS byte, terminate communication by issuing a
start or stop condition on the bus.

Acknowledge Each receiving device, when addressed, must generate an acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge clock
pulse. Setup and hold times must be taken into account. When a controller receives
data, the termination of the data transfer can be signaled by the controller generating a
not-acknowledge (1) on the last byte transmitted by the target.

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7.3.3.10 Two-Wire Timing Diagrams

t(LOW)
tR tF t(HDSTA)

SCL

t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO)

t(HDDAT) t(SUDAT)

SDA
t(BUF)

P S S P

Figure 7-2. Two-Wire Timing Diagram

Controller drives SDA

Target drives SDA

Target Address Register Pointer (N) Data to Register N (MSB) Data to Register N (LSB)

S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 P1 P0 A D15 D14 D13 D12 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P

START R/W STOP

ACK from Target ACK from Target ACK from Target ACK from Target

Note
The value of A7 through A0 are determined by the connections of the corresponding pins. See also
Table 7-2.

Figure 7-3. Two-Wire Timing Diagram for Write Word Format

Controller drives SDA

Target drives SDA

Target Address Register Pointer (N) Target Address

S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 P1 P0 A RS A6 A5 A4 A3 A2 A1 A0 1 A

START R/W START R/W

ACK from Target ACK from Target

Data to Register N (MSB) Data to Register N (LSB)

D15 D14 D13 D12 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 NA P

STOP

ACK from Controller NACK from Controller

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Note
The value of A7 through A0 are determined by the connections of the corresponding pins. See also
Table 7-2.

Figure 7-4. Two-Wire Timing Diagram for Read Word Format

Controller drives SDA

Target drives SDA

ALERT

Target Address from Device

SMBus Alert Func
on

S 0 0 0 1 1 0 0 1 A A6 A5 A4 A3 A2 A1 A0 S NA P

Alert Status STOP

START

ACK from Target NACK from Controller

Note
The value of A7 through A0 are determined by the connections of the corresponding pins. See also
Table 7-2.

Figure 7-5. Timing Diagram for SMBus Alert

7.4 Device Functional Modes

7.4.1 Continuous-Conversion Mode
The default mode of the TMP75B-Q1 is continuous conversion, where the ADC performs continuous
temperature conversions and stores each result to the temperature register, overwriting the result from the
previous conversion. Conversion rate bits CR1 and CR0 in the configuration register configure the TMP75B-Q1
for typical conversion rates of 37Hz, 18Hz, 9Hz, or 4Hz. The TMP75B-Q1 has a typical conversion time of 27ms.
To achieve different conversion rates, the TMP75B-Q1 makes a conversion, and then powers down and waits for
the appropriate delay set by CR1 and CR0. The default rate is 37Hz (no delay between conversions).Table 7-3
shows the settings for CR1 and CR0.
Table 7-3. Conversion Rate Settings
CR1 CR0 CONVERSION RATE (TYP) IQ (TYP)
0 0 37Hz (continuous conversion, default) 45μA
0 1 18Hz 22μA
1 0 9Hz 12μA
1 1 4Hz 6.5μA

After power-up or a general-call reset, the TMP75B-Q1 immediately starts a conversion, as shown in Figure 7-6.
The first result is available after 27ms (typical). The active quiescent current during conversion is 45μA (typical at
25°C). The quiescent current during delay is 1μA (typical at 25°C).

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(1) (1)
Delay Delay

27 ms

27 ms

27 ms

Startup Start of Start of

Conversion Conversion
A. Delay is set by the CR bits in the configuration register.

Figure 7-6. Conversion Start

7.4.2 Shutdown Mode

Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface, and
reduces current consumption to typically less than 0.3μA. Shutdown mode is enabled when the SD bit in the
configuration register is set to 1; the device shuts down after the current conversion is completed. When SD is
equal to 0, the device operates in continuous-conversion mode. When shutdown mode is enabled, the ALERT
pin and fault counter clear in both comparator and interrupt modes; however, this clearing occurs with the rising
edge of the shutdown signal. After shutdown is enabled, reprogramming shutdown does not clear the ALERT pin
and the fault counter until a rising edge is generated on the shutdown signal.
7.4.3 One-Shot Mode
The TMP75B-Q1 features a one-shot temperature measurement mode. When the device is in shutdown mode,
writing a 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state
at the completion of the single conversion. This mode reduces power consumption in the TMP75B-Q1 when
continuous temperature monitoring is not required. When the configuration register is read, the OS bit always
reads zero.
7.5 Programming
Figure 7-7 shows the internal register structure of the TMP75B-Q1. Use the 8-bit pointer register to address a
given data register. The pointer register uses the two LSBs to identify which of the data registers respond to a
read or write command. Figure 8-1 identifies the bits of the pointer register byte.

Pointer
Register

Temperature
Register

SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA

THIGH
Register

Figure 7-7. Internal Register Structure

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8 Register Map
Table 8-1 describes the registers available in the TMP75B-Q1 with the corresponding pointer addresses,
followed by the description of the bits in each register.
Table 8-1. Register Map and Pointer Addresses
P1 P0 REGISTER
0 0 Temperature register (read only, default)
0 1 Configuration register (read/write)
1 0 TLOW register (read/write)
1 1 THIGH register (read/write)

Figure 8-1. Pointer Register (pointer = N/A) [reset = 00h]

7 6 5 4 3 2 1 0
Reserved P1 P0
W-0h W-0h W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Figure 8-2. Temperature Register (pointer = 0h) [reset = 0000h]

15 14 13 12 11 10 9 8
T11 T10 T9 T8 T7 T6 T5 T4
R-0h

7 6 5 4 3 2 1 0
T3 T2 T1 T0 Reserved
R-0h R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-2. Temperature Register Description

Name Description
T11 to T4 The 8 MSBs of the temperature result (resolution of 1°C)
T3 to T0 The 4 LSBs of the temperature result (resolution of 0.0625°C)

Figure 8-3. Configuration Register (pointer = 1h) [reset = 00FFh]

15 14 13 12 11 10 9 8
OS CR FQ POL TM SD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
Reserved
R-FFh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-3. Configuration Register Description

Name Description
OS One-shot mode
In shutdown (SD = 1), write 1 to start a conversion. OS always reads back 0.

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Table 8-3. Configuration Register Description (continued)

Name Description
CR Conversion rate control
CR = 0h: 37Hz conversion rate (typ) (default)
CR = 1h: 18Hz conversion rate (typ)
CR = 2h: 9Hz conversion rate (typ)
CR = 3h: 4Hz conversion rate (typ)
FQ Fault queue to trigger the ALERT pin
FQ = 0h: 1 fault (default)
FQ = 1h: 2 faults
FQ = 2h: 4 faults
FQ = 3h: 6 faults
POL ALERT polarity control
POL = 0: ALERT is active low (default)
POL = 1: ALERT is active high
TM ALERT thermostat mode control
TM = 0: ALERT is in comparator mode (default)
TM = 1: ALERT is in interrupt mode
SD Shutdown control bit
SD = 0: Device is in continuous conversion mode (default)
SD = 1: Device is in shutdown mode

Figure 8-4. TLOW: Temperature Low Limit Register (pointer = 2h) [reset = 4B00h] (1)
15 14 13 12 11 10 9 8
L11 L10 L9 L8 L7 L6 L5 L4
R/W-4Bh

7 6 5 4 3 2 1 0
L3 L2 L1 L0 Reserved
R/W-0h R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) 4B00h = 75°C.

Table 8-4. TLOW Register Description
Name Description
L11 to L4 The 8 MSBs of the temperature low limit (resolution of 1°C)
L3 to L0 The 4 LSBs of the temperature low limit (resolution of 0.0625°C)

Figure 8-5. THIGH: Temperature High Limit Register (pointer = 3h) [reset = 5000h] (1)
15 14 13 12 11 10 9 8
H11 H10 H9 H8 H7 H6 H5 H4
R/W-50h

7 6 5 4 3 2 1 0
H3 H2 H1 H0 Reserved
R/W-0h R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) 5000h = 80°C.

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Table 8-5. THIGH Register Description

Name Description
H11 to H4 The 8 MSBs of the temperature high limit (resolution of 1°C)
H3 to H0 The 4 LSBs of the temperature high limit (resolution of 0.0625°C)

9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The TMP75B-Q1 is used to measure the PCB temperature where the device is mounted. The programmable
address options allow up to eight locations on the board to be monitored on a single serial bus. Connecting the
ALERT pins together and programming the temperature limit registers to desired values allows for a temperature
watchdog operation of all devices, interrupting the host controller only if the temperature exceeds the limits.

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9.2 Typical Application

1.4 V to 3.6 V

0.01 PF

TMP75B-Q1
1 8
SDA VS

Two-Wire 2 7
SCL A0
Host Controller
Connect to VS or
3 6 GND for up to 8
ALERT A1
Address
Combinations
4 5
GND A2

1.4 V to 3.6 V

TMP75B-Q1 0.01 PF
1 8
SDA VS

2 7
SCL A0

Connect to VS or
3 6 GND for up to 8
ALERT A1
Address
Combinations
4 5
GND A2

Additional
Sensor
Locations

Figure 9-1. Temperature Monitoring of Multiple Locations on a PCB

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9.2.1 Design Requirements

The TMP75B-Q1 only requires pullup resistors on SDA and ALERT, although a pullup resistor is typically present
on the SCL as well. A 0.01μF bypass capacitor on the supply is recommended, as shown in Figure 9-1. The
SCL, SDA, and ALERT lines can be pulled up to a supply that is equal to or higher than VS through the pullup
resistors. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either VS or GND.
9.2.2 Detailed Design Procedure
The TMP75B-Q1 must be placed in close proximity to the heat source to be monitored, with a proper layout
for good thermal coupling. This placement verifies that temperature changes are captured within the shortest
possible time interval.
9.2.3 Application Curve
Figure 9-2 shows the step response of the TMP75B-Q1 to a submersion in an oil bath of 100°C from room
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 seconds.
100
95
90
85
80
Temperature (ƒC)

75
70
65
60
55
50
45
40
35
30
25
±1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Time (s) C007

Figure 9-2. Temperature Step Response

9.3 Power-Supply Recommendations

The TMP75B-Q1 operates with power supply in the range of 1.4V to 3.6V. The device is optimized for operation
at 1.8V supply but can measure temperature accurately in the full supply range.
A power-supply bypass capacitor is recommended; place this capacitor as close as possible to the supply and
ground pins of the device. A typical value for this supply bypass capacitor is 0.01μF. Applications with noisy or
high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.
9.4 Layout
9.4.1 Layout Guidelines
Place the temperature sensor as close as possible and run copper planes on the ground or other layers to
provide good thermal coupling to the heat source for fast settling and accurate measurement of the temperature
of the hot spot.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins.
Pull up the open-drain output pins (SDA and ALERT) to a supply voltage rail (VS or higher but up to 3.6V)
through 10kΩ pullup resistors. Smaller values of the resistors can be used to compensate for long bus traces
that can cause an increase in capacitance and slow rise time for the open-drain outputs; the values must not
be less than 1kΩ to avoid self-heating effects due to increased current through the part in the low states of the
outputs.

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9.4.2 Layout Example

Via to Power or Ground Plane

Via to Internal Layer

Pull-Up Resistors
Supply Bypass
Capacitor

Supply Voltage
SDA VS

SCL A0

ALERT A1

GND A2

Ground Plane for

Thermal Coupling
to Heat Source

Serial Bus Traces

Heat Source

Figure 9-3. Layout Example

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
Texas Instruments, TMP75xEVM User's Guide, EVM user's guide
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Revision History

Changes from Revision A (June 2022) to Revision B (October 2024) Page

• Updated the number format for tables, figures, and cross-references throughout the document...................... 1
• Added the TMP75BTQDGKR device information in the specifications section and throughout the document..5

Changes from Revision * (October 2014) to Revision A (June 2022) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Changed all instances of legacy terminology to controller and target where I2C is mentioned..........................1
• Added Functional Safety information to the Features section............................................................................ 1

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TMP75BQDGKRQ1 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T75BQ
TMP75BQDGKRQ1.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T75BQ
TMP75BQDQ1 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 125 T75BQ
TMP75BQDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T75BQ
TMP75BQDRQ1.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T75BQ
TMP75BTQDGKRQ1 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 75BTQ
TMP75BTQDGKRQ1.B Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 75BTQ

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

OTHER QUALIFIED VERSIONS OF TMP75B-Q1 :

• Catalog : TMP75B

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jan-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP75BQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TMP75BQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TMP75BTQDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jan-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP75BQDGKRQ1 VSSOP DGK 8 2500 353.0 353.0 32.0
TMP75BQDRQ1 SOIC D 8 2500 356.0 356.0 35.0
TMP75BTQDGKRQ1 VSSOP DGK 8 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

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 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

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 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

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