Mid Sem. Monsoon2022: VLSI Digital (EC2.
201)
Max. Time: 90 Mins [4:30 to 6:00 PM] Date: 22/09/2022
Note(s): No query is allowed during exam.
Write your assumptions (if any) for each question.
Q 1. [5 Marks] [CO-1]
Consider two NMOS transistors working in saturation with same VGS and VDS
a) If two devices are matched except maximum possible mismatch in their (W/L) ratios
of 3%. What is the maximum resulting mismatch in the drain currents
b) If two devices are matched except maximum possible mismatch in their Vt values of
10mV. What is the maximum possible mismatch in the drain currents. Assume
nominal value of Vt is 0.6V
Q 2. [5 Marks] [CO-1]
A set of I-V characteristics of an nMOS
transistor at room temperature are
shown in below (in Table) for different
biasing conditions. Fig. shows
measurement setup. Using the data,
find the threshold voltage VT0
VGS VDS VSB ID (µA)
4V 4V 0.0V 256
5V 5V 0.0V 441
4V 4V 2.6V 144
5V 5V 2.6V 256
Solution:
MOS Capacitance
Q 3. Answer the following questions [9 Marks] [CO-1]
(a) Draw a MOSFET Capacitance model (DC model) depicting distinct components of
capacitance.
Like this, students may have shown capacitance with MOS symbol, that is also fine.
(b) The capacitances in MOSFET occurs due to _____________
i. Interconnects
ii. Difference in Doping concentration
iii. Difference in dopant materials
iv. All of the mentioned
(c) The parasitic capacitances found in MOSFET are ___________
i. Oxide related capacitances
ii. Inter electrode capacitance
iii. Electrolytic capacitance
iv. All of the mentioned
(d) In Cut-off region (assume MOS is in accumulation), the capacitance Cgs will be equal to _
i. 2CGD0
ii. CGS0.W
iii. CGB
iv. All of the mentioned
(e) In cut-off region (assume MOS is in accumulation), the value of gate to substrate
capacitance is equal to ___________
i. Cox .(W- L)
ii. CGB0.L + Cox W/ L
iii. CGB0.L + Cox* W*L
iv. 0
(f) In linear mode operation, the parasitic capacitances that exists are ___________
i. Nonzero Gate to source capacitance
ii. Nonzero Gate to drain capacitance
iii. Zero gate to substrate capacitance
iv. All of the mentioned
(g) In saturation mode operation, gate to drain capacitance (channel) is zero due to______
i. Gate and drain are interconnected
ii. Channel length is reduced
iii. Inversion layer doesn’t exist
iv. Drain is connected to ground
(h) When MOSFET is operating in saturation region, the gate to source capacitance (channel)
is?
i. 1/2*Cox*W*L
ii. 2/3*Cox*W*L
iii. Cox*W*L
iv. 1/3*Cox*W*L
(i) In the below graph, the regions marked as A, B, C are?
i. A : Saturation, B : Linear, C : Cut-off
ii. A : Cut-off, B : Linear, C : Saturation
iii. A : Linear, B : Saturation, C : Cut-off
iv. None of the mentioned
Hint: Analyse the graph from the gate to source voltage on x axis and regions can be
determined.
Noise Margin
Q 4. [10 Marks] [CO-1, CO-2]
Consider a resistive-load inverter with VDD=5V, transconductance (kn’) = 20 µA/V2, VT0= 0.8 V,
RL= 200 KΩ, and W/L=2. Calculate the critical voltages (VOL, VOH, VIL, VIH) and on the VTC and
find the noise margin of the circuit.
Are your calculated noise margins good? Please comment on the quality of the inverter
design, and how can you improve it? [For this part, you need to look at their answers]
Below is the solution, However, students may have a little different approach. You all should
check properly.
Power dissipation and propagation delays
Q 5. [10 Marks] [CO-2]
Consider a resistive-load inverter design, driving a
similar inverter (as shown in Fig.). Now answer the
following-
(a) What is the net capacitance at node VX.
(b) Let’s say the input (VIN) is abruptly switching
from VDD to 0. What is the state/region of each
MOS (m1 and m2) before and after the switching.
(c) Develop a simple expression for the calculation
of low-to-high propagation delay (τplh).
(d) Discuss the parameters impacting the τplh.
From the developed expression, how can you
improve the operating speed of this resistive-load
inverter? Discuss the trade-off. Also discuss the
assumption considered.
Solution: Answers are below slides, look carefully
Q 6. [6 Marks] [CO-1, CO-2]
How much is the dynamic power dissipated (Pdynamic)
in 2-input resistive-load NAND gate for the following
cases? Develop only equations.
(a) When input ‘B’=1, and input ‘A’ switches with
clock frequency.
(b) When input ‘A’=1, and input ‘B’ switches with
clock frequency.
Solution:
