Sree Vishnu Varthini

@sreevishnuvarthini

ASIC
Design Flow
INTRODUCTION
VLSI (Very Large Scale Integration) is a process used in electronics and semiconductor
industries to create integrated circuits (ICs) by combining thousands to millions of
transistors onto a single chip. This technology enables the development of smaller, faster,
and more efficient devices, such as microprocessors, memory chips, and other complex
digital systems.

Key Concepts in VLSI:

Transistor: The fundamental building block of VLSI circuits, used for amplification and
switching.
Integrated Circuit (IC): A set of electronic circuits integrated into a small chip, often
in the form of a silicon wafer.
Moore’s Law: The observation that the number of transistors on a chip doubles
approximately every two years, leading to increased performance and reduced cost.
ASIC
ASIC (Application-Specific Integrated Circuit) is a type of integrated circuit (IC)
designed for a specific application or task, unlike general-purpose ICs like
microprocessors. ASICs are optimized to perform particular functions with high efficiency,
speed, and low power consumption.

Types of ASICs:
Full-Custom ASIC: Designed from the ground up, with every transistor and
component tailored for the application.
Semi-Custom ASIC: Uses predefined standard cells and blocks (e.g., gate arrays or
structured ASICs) that are customized for a specific application.
Programmable ASIC (e.g., FPGA): Can be reprogrammed to suit different
applications, offering flexibility during the development phase.
ASIC DESIGN FLOW

FRONTEND

DFT INSERTION LOGIC SYNTHESIS

BACKEND
FRONTEND FLOW (LOGICAL DESIGN)
Definition:
The frontend flow focuses on the functional and logical design of the chip. It primarily deals
with what the chip is supposed to do.

Steps:
1.Specification – Define chip architecture and features.
2.RTL Coding – Use Verilog/VHDL to describe the logic.
3.Functional Verification – Test RTL correctness using testbenches.
4.Synthesis – Convert RTL to gate-level netlist (mapped to standard cells).
5.DFT Insertion – Add scan chains and test logic for manufacturing testing.

Tools: Verilog/VHDL, ModelSim, Design Compiler.

Output: Gate-level netlist.
FRONTEND FLOW
SPECIFICATIONS

ARCHITECTURAL DESIGN

RTL CODING

FUNCTIONAL VERIFICATION
Meets Specs? (No) Meets Specs (Yes)

BACKEND
BACKEND FLOW (PHYSICAL DESIGN)
Definition:
The backend flow focuses on the physical implementation of the chip. It deals with how the
logic will be physically laid out on silicon.

Steps:
1.Floorplanning – Define chip area, macro placements, and I/O locations.
2.Placement – Place standard cells efficiently.
3.Clock Tree Synthesis (CTS) – Distribute clock signals with balanced delay.
4.Routing – Physically connect all cells using metal layers.
5.Physical Verification – DRC (design rules), LVS (netlist vs. layout), ERC.

Tools: Innovus, ICC2, Calibre.

Output: GDSII file for fabrication.
BACKEND FLOW
FRONTEND
(NETLIST)
CLOCK TREE SYNTHESIS

FLOORPLANNING
ROUTING

POWERPLANNING
PHYSICAL VERIFICATION
Meets Specs? (No) Meets Specs? (Yes)

PLACEMENT
SIGNOFF & TAPEOUT
ASIC DESIGN FLOW
1.SPECIFICATION
This is the starting point where the functionality and performance of the ASIC are defined.

Goal: Understand what the chip should do. (e.g., Signal Processing, Data Storage)

Key Deliverables:
Functional Requirements: Define the specific tasks the chip will perform.
Performance Metrics: Power consumption, speed, area constraints, etc.
Standards Compliance: Ensure compatibility with industry standards (e.g., PCIe,
USB).

This stage sets a clear roadmap for the design process.

2. ARCHITECTURAL DESIGN
Once the specifications are finalized, a high-level architecture is created.

Goal: Divide the overall functionality into smaller, manageable blocks.

Determine block interconnections and explore various architectural options.
Evaluate performance, feasibility, and resource utilization.

Key Deliverables:
Microarchitecture: Define internal modules and their interaction.
Block Diagram: Represent the design visually with functional blocks.
Data Flow and Control Flow: Specify how data and control signals move between
blocks.
Design Trade-offs: Balance power, performance, and area (PPA).
3. RTL (REGISTER TRANSFER LEVEL) DESIGN
At this stage, the chip's functionality is described using a Hardware Description Language
(HDL) like Verilog or SystemVerilog.

Goal: Create a synthesizable model of the chip.

Key Steps:
Write RTL Code: Describe how data is processed and controlled.
Perform Simulation: Verify functionality against specifications.
Create Testbenches: Simulate scenarios to ensure correct behavior.

Deliverables:
A functional RTL model validated through simulations.
4. FUNCTIONAL VERIFICATION
Functional verification ensures that the RTL design behaves as intended.

Goal: Detect and fix logical bugs.

Confirm the design meets all specified requirements.

Key Techniques:
Simulation-Based Verification: Test the RTL using test cases.
Formal Verification: Prove the correctness of logic mathematically.
Coverage Metrics: Ensure all possible scenarios are tested.

Tools:
UVM (Universal Verification Methodology), SystemVerilog Assertions (SVA).
5. SYNTHESIS
The RTL code is converted into a gate-level netlist.

Goal: Transform HDL into logic gates that can be implemented physically.

Key Steps:
Logic Synthesis: Map RTL to technology-specific standard cells (AND, OR,
Flip-flops, etc.).
Constraint File: Use a timing constraints file (SDC) to meet PPA requirements.
Static Timing Analysis (STA): Verify timing constraints like setup and hold time.

Tools:
Synopsys Design Compiler, Cadence Genus.
6. DESIGN FOR TESTABILITY (DFT)
This step ensures the chip can be tested after manufacturing.

Goal: Ensure the manufactured chip can be tested for defects.

Reduce testing time and cost.

Key Techniques:
Scan Chains: Add extra connections to observe internal signals.
Built-In Self-Test (BIST): Add circuits that test the chip autonomously.
Fault Coverage: Measure how well tests detect potential issues.
Boundary Scan (JTAG): Test interconnects and external components.
Memory BIST (MBIST): Focus on testing embedded memory.
7. FLOORPLANNING
Floorplanning defines chip dimensions, positions blocks, and allocates space for core and
I/O areas based on power, area, and timing.

Goal: Organize the overall chip layout and define the placement of functional blocks.

Key Deliverables:
A floorplan file that specifies the dimensions and relative positions of different modules.
Power grid planning to ensure that all blocks have adequate power delivery.

Considerations:
Block orientation: The arrangement of blocks to minimize wire length.
Clock distribution: Efficient placement of the clock tree to minimize delay.
8. PLACEMENT
Goal: Place the standard cells on the chip to meet performance, power, and area (PPA)
goals.

Key Deliverables:
A placement file specifying the positions of each standard cell.
Timing reports that show if timing constraints are met at this stage.

Considerations:
Wire length: Minimizing the distance between cells reduces delay and power
consumption.
Congestion: Avoid areas with too many cells in close proximity, which can cause
routing issues.
9. CLOCK TREE SYNTHESIS (CTS)
Goal: Distribute the clock signal evenly across the chip while minimizing clock skew,
ensuring timing accuracy, and optimizing power consumption.

Key Deliverables:
A clock tree structure specifying the routing of the clock signal.
Skew and delay reports to ensure that the timing constraints related to the clock are
met.

Considerations:
Clock tree balancing: Distribute the clock evenly across the chip to minimize skew.
Buffer insertion: Add buffers in the clock tree to drive large capacitances and
reduce delay.
10. ROUTING
Goal: Connect all the placed cells using metal layers to form the complete circuit.

Key Deliverables:
A routing file that specifies the metal layers and paths used to connect components.
Design Rule Check (DRC) reports to ensure the routing complies with manufacturing
constraints.

Considerations:
Wire delay: Long wires introduce delays that can impact timing.
Signal integrity: Ensuring that wires are properly shielded to avoid crosstalk or
interference.
Congestion: Avoid overcrowding of wires, which can lead to manufacturing issues.
11. DESIGN RULE CHECK (DRC)
Goal: Ensure that the physical layout adheres to the manufacturing process's design
rules, preventing errors that could affect fabrication and performance.

Key Deliverables:
A DRC report that lists any rule violations.
Corrected layout after fixing violations.

Considerations:
Manufacturing process limits: The layout must be manufacturable with the
technology node (e.g., 7nm, 14nm).
Fixing violations: Small violations are corrected, often by modifying the layout or
adjusting routing paths.
12. LAYOUT VS. SCHEMATIC (LVS)
Goal: Verify that the physical layout matches the intended logical design, ensuring that all
connections and components are correctly implemented.

Key Deliverables:
An LVS report that highlights any mismatches between the layout and the schematic.
A corrected layout after resolving discrepancies.

Considerations:
Net connectivity: Ensuring that every logical connection is correctly implemented in
the layout.
Tool-based comparison: LVS is typically done using automated tools that compare
the schematic and layout files.
13. FINAL SIGN-OFF
Goal: Ensure that the design is fully ready for tape-out. Confirm that the design meets all
the required specifications, including timing, power, area before sending it for fabrication.

Key Deliverables:
Sign-off reports confirming that the design is manufacturable and meets all
requirements.
Tape-out file (GDSII), which is the final file used by the foundry to fabricate the chip.

Considerations:
Final timing analysis: Ensure that no timing violations exist in the final layout.
Verification of all constraints: Make sure all aspects of the design, from power to
performance, are verified.
14. GDSII GENERATION
Goal: Generate the final layout file (GDSII) that describes the physical chip structure for
fabrication.

Key Deliverables:
GDSII file: A file containing the full chip layout, including all the layers and geometries.
Design rule check (DRC): The final design is verified to ensure it complies with
manufacturing constraints before generating the GDSII file.

Considerations:
Manufacturing Constraints: The GDSII file must follow the fabrication process rules.
Layer Representation: Different layers (metal, polysilicon, etc.) are shown separately in
the GDSII file.
 Sree Vishnu Varthini
@sreevishnuvarthini

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