ESMT F59L1G81MB (2M)

Flash 1 Gbit (128M x 8)

3.3V NAND Flash Memory
FEATURES
 Voltage Supply: 3.3V (2.7V~3.6V)  Reliable CMOS Floating Gate Technology
 Organization - ECC Requirement: - 4bit/528Byte
- Memory Cell Array: (128M + 4M) x 8bit - Endurance: 100K Program/Erase cycles
- Data Register: (2K + 64) x 8bit - Data Retention: 10 years
 Automatic Program and Erase  Command Register Operation
- Page Program: (2K + 64) Byte
 Automatic Page 0 Read at Power-Up Option
- Block Erase: (128K + 4K) Byte
- Boot from NAND support
 Page Read Operation
- Page Size: (2K + 64) Byte - Automatic Memory Download
- Random Read: 25us (Max.)  NOP: 4 cycles
- Serial Access: 25ns (Min.) (3.3V)  Cache Program Operation for High Performance Program
 Memory Cell: 1bit/Memory Cell  Cache Read Operation
 Fast Write Cycle Time  Copy-Back Operation
- Program time: 300us - typical  EDO mode
- Block Erase time: 4ms - typical  OTP Operation
 Command/Address/Data Multiplexed I/O Port  Bad-Block-Protect
 Hardware Data Protection  Operating temperature
- Program/Erase Lockout During Power Transitions
- Commercial: 0°C to +70°C

ORDERING INFORMATION
Product ID Speed Package Comments
F59L1G81MB -25TG2M 25 ns 48 pin TSOPI Pb-free
F59L1G81MB-25BUG2M 25 ns 48 ball BGA Pb-free
F59L1G81MB -25BG2M 25 ns 63 ball BGA Pb-free
F59L1G81MB -25BCG2M 25 ns 67 ball BGA Pb-free

GENERAL DESCRIPTION
The device is a 128Mx8bit with spare 4Mx8bit capacity. The Byte. The I/O pins serve as the ports for address and command
device is offered in 3.3V Vcc Power Supply. Its NAND cell inputs as well as data input/output. The copy back function
provides the most cost-effective solution for the solid state mass allows the optimization of defective blocks management: when a
storage market. The memory is divided into blocks that can be page program operation fails the data can be directly
erased independently so it is possible to preserve valid data programmed in another page inside the same array section
while old data is erased. without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
The device contains 1024 blocks, composed by 64 pages register while the data register is copied into the Flash array.
consisting in two NAND structures of 32 series connected Flash This pipelined program operation improves the program
cells. A program operation allows to write the 2,112-Byte page in throughput when long files are written inside the memory. A
typical 400us and an erase operation can be performed in typical cache read feature is also implemented. This feature allows to
3ms on a 128K-Byte for X8 device block. dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
Data in the page mode can be read out at 25ns cycle time per feature: Automatic Read at Power Up.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 1/51
ESMT F59L1G81MB (2M)
PIN CONFIGURATION (TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)

BALL CONFIGURATION (TOP VIEW)

(BGA 48 BALL, 6.5mm X 5mm Body, 0.8 Ball Pitch)
1 2 3 4 5 6

A WP ALE VSS CE WE R/B

B NC RE CLE NC NC NC

C NC NC NC NC NC NC

D NC NC NC NC NC NC

E NC NC LOCK NC NC NC

F NC I/O0 NC NC NC VCC

G NC I/O1 NC VCC I/O5 I/O7

H VSS I/O2 I/O3 I/O4 I/O6 VSS

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 2/51
ESMT F59L1G81MB (2M)

BALL CONFIGURATION (TOP VIEW)

(BGA 63 BALL, 9mm X 11mm Body, 0.8 Ball Pitch)

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 3/51
ESMT F59L1G81MB (2M)
BALL CONFIGURATION (TOP VIEW)
(BGA 67 Ball, 6.5mmx8mmx1.0mm Body, 0.8mm Ball Pitch)

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 4/51
ESMT F59L1G81MB (2M)
Pin Description
Symbol Pin Name Functions
The I/O pins are used to input command, address and data, and to output data
I/O0~I/O7 Data Inputs / Outputs during read operations. The I/O pins float to high-z when the chip is deselected
or when the outputs are disabled.
The CLE input controls the activating path for commands sent to the internal
Command Latch command registers. Commands are latched into the command register through
CLE
Enable
the I/O ports on the rising edge of the WE signal with CLE high.
The ALE input controls the activating path for addresses sent to the internal
ALE Address Latch Enable address registers. Addresses are latched into the address register through the
I/O ports on the rising edge of WE with ALE high.

The CE input is the device selection control. When the device is in the Busy

Chip Enable state, CE high is ignored, and the device does not return to standby mode in
CE
program or erase operation. Regarding CE control during read operation,
refer to ’Page read’ section of Device operation.
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled.
LOCK LOCK To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it
unconnected (internal pull-down).

The RE input is the serial data-out control, and when it is active low, it drives
RE Read Enable the data onto the I/O bus. Data is valid tREA after the falling edge of RE which
also increments the internal column address counter by one.

The WE input controls writes to the I/O ports. Commands, address and data
WE Write Enable
are latched on the rising edge of the WE pulse.
The WP pin provides inadvertent write/erase protection during power
WP Write Protect transitions. The internal high voltage generator is reset when the WP pin is
active low.
The R/ B output indicates the status of the device operation. When low, it
indicates that a program, erase or random read operation is in progress and
R /B Ready / Busy Output returns to high state upon completion. It is an open drain output and does not
float to high-z condition when the chip is deselected or when outputs are
disabled.
VCC Power VCC is the power supply for device.
VSS Ground
NC No Connection Lead is not internally connected.
Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave V CC or VSS disconnected.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 5/51
ESMT F59L1G81MB (2M)
BLOCK DIAGRAM

ARRAY ORGANIZATION

Array Address
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Address
1st cycle A0 A1 A2 A3 A4 A5 A6 A7 Column Address
2nd cycle A8 A9 A10 A11 L* L* L* L* Column Address
3rd cycle A12 A13 A14 A15 A16 A17 A18 A19 Row Address
4th cycle A20 A21 A22 A23 A24 A25 A26 A27 Row Address

Note:
1. Column Address: Starting Address of the Register.
2. *L must be set to “Low”.
3. The device ignores any additional input of address cycles than required.
4. A12~A17 are for Page Address, A18~A27 are for Block Address

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 6/51
ESMT F59L1G81MB (2M)
Product Introduction
The device is a 1Gbit memory organized as 128K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column
address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The program and read operations are executed on a page basis,
while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It
indicates that the bit-by-bit erase operation is prohibited on the device.

The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address Latch
Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory.

Command Set
Acceptable Command
Function 1st Cycle 2nd Cycle
during Busy
Read 00h 30h
Read for Copy Back 00h 35h
Read ID 90h -
Reset FFh - O
BLOCK UNLOCK LOW / HIGH 23h 24h
BLOCK LOCK 2Ah
BLOCK LOCK-TIGHT 2Ch
BLOCK LOCK READ STATUS 7Ah O
Page Program 80h 10h
Copy-Back Program 85h 10h
Block Erase 60h D0h
(1)
Random Data Input 85h -
(1)
Random Data Output 05h E0h
Read Status 70h - O
Cache Program 80h 15h
Cache Read 31h -
Read Start For Last Page 3Fh -
Cache Read

Note: Random Data Input / Output can be executed in a page.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 7/51
ESMT F59L1G81MB (2M)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
VCC -0.6 to +4.6
Voltage on any pin relative to VSS VIN -0.6 to +4.6 V
VI/O -0.6 to VCC + 0.3 (< 4.6)
Temperature Under Bias TBIAS -40 to +125 ℃
Storage Temperature TSTG -65 to +150 ℃
Short Circuit Current IOS 5 mA
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.
3. Maximum Voltage may overshoot to VCC +2.0V during transition and for less than 20 ns during transitions.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, TA = 0 to 70℃)
Parameter Symbol Min. Typ. Max. Unit
Supply Voltage VCC 2.7 3.3 3.6 V
Supply Voltage VSS 0 0 0 V

DC AND OPERATION CHARACTERISTICS

(Recommended operating conditions otherwise noted)
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Page Read with
ICC1 tRC=25ns, CE =VIL, IOUT=0mA - 15 30
Operating Serial Access
Program ICC2 - - 15 30 mA
Current
Erase ICC3 - - 15 30
Stand-by Current (TTL) ISB1 CE =VIH, WP =0V/VCC - - 1 mA
Stand-by Current (CMOS) ISB2 CE = VCC -0.2, WP =0V/ VCC - 10 50 uA
Input Leakage Current ILI VIN=0 to VCC (max) - - ±10 uA
Output Leakage Current ILO VOUT=0 to VCC (max) - - ±10 uA
Input High Voltage VIH - 0.8 x VCC - VCC +0.3 V
Input Low Voltage, All inputs VIL - -0.3 - 0.2 x VCC V
Output High Voltage Level VOH IOH=-400uA 2.4 - - V
Output Low Voltage Level VOL IOL=2.1mA - - 0.4 V
Output Low Current (R/ B ) IOL (R / B ) VOL=0.4V 8 10 - mA
Note:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
2. Typical value are measured at VCC =3.3V, TA=25℃. And not 100% tested.

VALID BLOCK
Symbol Min. Typ. Max. Unit
NVB 1004 - 1024 Block
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The
number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain
one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad
blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to
be a valid block up to 1K program/erase cycles with 4bit/528Byte ECC.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 8/51
ESMT F59L1G81MB (2M)
AC TEST CONDITION
(TA=0 to 70℃, VCC=2.7V~3.6V)
Parameter Condition
Input Pulse Levels 0V to VCC
Input Rise and Fall Times 5 ns
Input and Output Timing Levels VCC /2
Output Load* 1 TTL Gate and CL=50pF

Note: Refer to Ready/ Busy , R/ B output’s Busy to Ready time is decided by the pull-up resistor (Rp) tied to the R/ B pin.

CAPACITANCE
(TA=25℃, VCC=3.3V, f=1.0MHz)
Item Symbol Test Condition Min. Max. Unit
Input / Output Capacitance CI/O VIL = 0V - 8 pF
Input Capacitance CIN VIN = 0V - 8 pF
Note: Capacitance is periodically sampled and not 100% tested.

MODE SELECTION
CLE ALE CE WE RE WP Mode
H L L H X Command Input
Read Mode
L H L H X Address Input (4 clock)
H L L H H Command Input
Write Mode
L H L H H Address Input (4 clock)
L L L H H Data Input
L L L H X Data Output
X X X X H X During Read (Busy)
X X X X X H During Program (Busy)
X X X X X H During Erase (Busy)
(1)
X X X X X L Write Protect
(2)
X X H X X 0V/VCC Stand-by
Note:
1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for stand-by.

Program / Erase Characteristics

(TA=0 to 70℃, VCC=2.7V~3.6V)
Parameter Symbol Min. Typ. Max. Unit
Average Program Time tPROG - 300 750 us
Dummy Busy Time for Cache Program tCBSY - 3 750 us
Last Page Program Time tLPROG - - 900 us
Number of Partial Program Cycles in the
NOP - - 4 Cycle
Same Page
Block Erase Time tBERS - 4 10 ms
Busy Time for Program / Erase on
tLBSY - - 3 us
Locked Blocks
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V V CC and 25℃
temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program time variation from page to page is
possible.
3. tLPROG= tPROG(last page)+ tPROG(last-1 page)- Command load time(last page)-Address load time(last page)- Data load time(last
page).

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 9/51
ESMT F59L1G81MB (2M)
AC Timing Characteristics for Command / Address / Data Input
Parameter Symbol Min. Max. Unit
(1)
CLE Setup Time tCLS 12 - ns
CLE Hold Time tCLH 5 - ns
(1)
CE Setup Time tCS 20 - ns

CE Hold Time tCH 5 - ns

WE Pulse Width tWP 12 - ns

(1)
ALE Setup Time tALS 12 - ns
ALE Hold Time tALH 5 - ns
(1)
Data Setup Time tDS 12 - ns
Data Hold Time tDH 5 - ns
Write Cycle Time tWC 25 - ns
WE High Hold Time tWH 10 - ns
(2)
Address to Data Loading Time tADL 100 - ns
Note:
1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 10/51
ESMT F59L1G81MB (2M)
AC Characteristics for Operation
Parameter Symbol Min. Max. Unit
Data Transfer from Cell to Register tR - 25 us
ALE to RE Delay tAR 10 - ns

CLE to RE Delay tCLR 10 - ns

Ready to RE Low tRR 20 - ns

RE Pulse Width tRP 12 - ns

WE High to Busy tWB - 100 ns

WP Low to WE Low (disable mode)

tWW 100 ns
WP High to WE Low (enable mode)
Read Cycle Time tRC 25 - ns
RE Access Time tREA - 20 ns

CE Access Time tCEA - 25 ns

RE High to Output Hi-Z tRHZ - 100 ns

CE High to Output Hi-Z tCHZ - 30 ns

CE High to ALE or CLE Don’t Care tCSD 0 - ns

RE High to Output Hold tRHOH 15 - ns

RE Low to Output Hold tRLOH 5 - ns

CE High to Output Hold tCOH 15 - ns

RE High Hold Time tREH 10 - ns

Output Hi-Z to RE Low tIR 0 - ns

RE High to WE Low tRHW 100 - ns

WE High to RE Low tWHR 60 - ns

Read - 5 us
Device Resetting Program - 10 us
tRST
Time during ... Erase - 500 us
(1)
Ready - 5 us
Cache Busy in Read Cache (following
tDCBSYR - 30 us
31h and 3Fh)
Note:
1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 11/51
ESMT F59L1G81MB (2M)
NAND Flash Technical Notes
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The
information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the
same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not
affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The
system design must be able to mask out the initial invalid block(s) via address mapping.

The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with
4bit/528Byte ECC.

Identifying Initial Invalid Block(s) and Block Replacement Management

All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the 1st byte column address in the spare area.

Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information
and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop
with Flash memory usage.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 12/51
ESMT F59L1G81MB (2M)

Algorithm for Bad Block Scanning

Check “FFh” at the 1st Byte column address

in the spare area of the 1st and 2nd page in
the block.

For (i=0; i<Num_of_LUs; i++)

{
For (j=0; j<Blocks_Per_LU; j++)
{
Defect_Block_Found=False;

Read_Page(lu=i, block=j, page=0);

If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;

Read_Page(lu=i, block=j, page=1);

If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;

If (Defect_Block_Found) Mark_Block_as_Defective(lu=i, block=j);

}

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 13/51
ESMT F59L1G81MB (2M)
Error in Write or Read Operation
Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.
The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and
reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To
improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by
ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks.

Failure Mode Detection and Countermeasure sequence

Erase Failure Read Status after Erase → Block Replacement
Write
Program Failure Read Status after Program → Block Replacement
Read Up to 4 bit Failure Verify ECC → ECC Correction

Note: Error Correcting Code → RS Code or BCH Code etc.

Example: 4bit correction / 528Byte

Program Flow Chart

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 14/51
ESMT F59L1G81MB (2M)
Erase Flow Chart

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 15/51
ESMT F59L1G81MB (2M)
Read Flow Chart

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 16/51
ESMT F59L1G81MB (2M)
Block Replacement

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page of the block to MSB (Most
Significant Bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.

Page 63 (64) Page 63 (64)

: :

Page 31 (32) Page 31 (1)

: :

Page 2 (3) Page 2 (3)

Page 1 (2) Page 1 (32)
Page 0 (1) Page 0 (2)

Data register Data register

From the LSB page to MSB page Ex.) Random page program (Prohibition)

DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64)

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 17/51
ESMT F59L1G81MB (2M)
System Interface Using CE don’t-care

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio
applications that use slow cycle time on the order of μ-seconds, de-activating CE during the data-loading and serial access would
provide significant savings in power consumption.

Program/Read Operation with “ CE not-care”

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 18/51
ESMT F59L1G81MB (2M)
Address Information
I/O DATA ADDRESS
I/Ox Data In / Out Col. Add1 Col. Add2 Row Add1 Row Add2
I/O0 ~ I/O7 2,112 Byte A0 ~ A7 A8 ~ A11 A12 ~ A19 A20 ~ A27

Command Latch Cycle

Address Latch Cycle

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 19/51
ESMT F59L1G81MB (2M)
Input Data Latch Cycle

Serial access Cycle after Read (CLE = L, ALE = L, WE = H)

Note:
1. Dout transition is measured at ±200mV from steady state voltage at I/O with load.
2. tRHOH starts to be valid when frequency is lower than 33MHz.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 20/51
ESMT F59L1G81MB (2M)
Serial access Cycle after Read (EDO Type CLE = L, ALE = L, WE = H)

Note:
1. Transition is measured at +/-200mV from steady state voltage with load.
This parameter is sample and not 100% tested. (t CHZ, tRHZ)
2. tRLOH is valid when frequency is higher than 33MHZ.
tRHOH starts to be valid when frequency is lower than 33MHZ.

Status Read Cycle

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 21/51
ESMT F59L1G81MB (2M)
Read Operation (Read One Page)

Read Operation (Intercepted by CE )

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 22/51
ESMT F59L1G81MB (2M)
Random Data Output In a Page

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 23/51
ESMT F59L1G81MB (2M)
Page Program Operation

Page Program Operation with Random Data Input

Note: tADL is the time from WE rising edge of final address cycle to the WE rising edge of first data cycle.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 24/51
ESMT F59L1G81MB (2M)
Copy-Back Operation with Random Data Input

Cache Program Operation

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 25/51
ESMT F59L1G81MB (2M)
Cache Read Operation

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 26/51
ESMT F59L1G81MB (2M)
Block Erase Operation

Read ID Operation
00h Address

20h Address

ID Definition Table
ID Access command = 90h
rd th th
Maker Code Device Code 3 Cycle 4 Cycle 5 Cycle
C8h D1h 80h 95h 40h

Description
st
1 Byte Maker Code
nd
2 Byte Device Code
rd
3 Byte Internal Chip Number, Cell Type, etc
th
4 Byte Page Size, Block Size, etc
th
5 Byte Plane Number, Plane Size

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 27/51
ESMT F59L1G81MB (2M)
3rd ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1 0 0
2 0 1
Internal Chip Number
4 1 0
8 1 1
2 Level Cell 0 0
4 Level Cell 0 1
Cell Type
8 Level Cell 1 0
16 Level Cell 1 1
1 0 0
Number of
2 0 1
Simultaneously
4 1 0
Programmed Pages
8 1 1
Interleave Program Not Support 0
Between Multiple Chips Support 1
Not Support 0
Cache Program
Support 1

4th ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1KB 0 0
Page Size 2KB 0 1
(w/o redundant area) 4KB 1 0
8KB 1 1
64KB 0 0
Block Size 128KB 0 1
(w/o redundant area) 256KB 1 0
512KB 1 1
Redundant Area Size 8 0
(Byte/512Byte) 16 1
x8 0
Organization
x16 1
45ns 0 0
Reserved 0 1
Serial Access Time
25ns 1 0
Reserved 1 1

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 28/51
ESMT F59L1G81MB (2M)
5th ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
4bit/528B 0 0
2bit/528B 0 1
ECC Level
1bit/528B 1 0
Reserved 1 1
1 0 0
2 0 1
Plane Number
4 1 0
8 1 1
64Mb 0 0 0
128Mb 0 0 1
256Mb 0 1 0
Plane Size 512Mb 0 1 1
(w/o redundant area) 1Gb 1 0 0
2Gb 1 0 1
4Gb 1 1 0
8Gb 1 1 1
Reserved Reserved 0

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 29/51
ESMT F59L1G81MB (2M)
DEVICE OPERATION
Page Read
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h command, four-cycle
address, and 30h command. After initial power up, the 00h command can be skipped because it has been latched in the command
register. The 2,112Byte of data on a page are transferred to cache registers via data registers within 25us (t R). Host controller can
detect the completion of this data transfer by checking the R/ B output. Once data in the selected page have been loaded into cache
registers, each Byte can be read out in 25ns cycle time by continuously pulsing RE . The repetitive high-to-low transitions of RE
clock signal make the device output data starting from the designated column address to the last column address.

The device can output data at a random column address instead of sequential column address by using the Random Data Output
command. Random Data Output command can be executed multiple times in a page.

After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.

A page read sequence is illustrated in Figure below, where column address, page address are placed in between commands 00h and
30h. After tR read time, the R/ B de-asserts to ready state. Read Status command (70h) can be issued right after 30h. Host controller
can toggle RE to access data starting with the designated column address and their successive bytes.

Read Operation

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 30/51
ESMT F59L1G81MB (2M)
Random Data Output In a Page

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 31/51
ESMT F59L1G81MB (2M)
Page Program
The device is programmed based on the unit of a page. Addressing of page program operations within a block should be in sequential
order. A complete page program cycle consists of a serial data input cycle in which up to 2,112byte of data can be loaded into data
register via cache register, followed by a programming period during which the loaded data are programmed into the designated
memory cells.

The serial data input cycle begins with the Serial Data Input command (80h), followed by a four-cycle address input and then serial
data loading. The bytes not to be programmed on the page do not need to be loaded. The column address for the next data can be
changed to the address follows Random Data Input command (85h). Random Data Input command may be repeated multiple times in
a page. The Page Program Confirm command (10h) starts the programming process. Writing 10h alone without entering data will not
initiate the programming process. The internal write engine automatically executes the corresponding algorithm and controls timing for
programming and verification, thereby freeing the host controller for other tasks. Once the program process starts, the host controller
can detect the completion of a program cycle by monitoring the R/ B output or reading the Status bit (I/O6) using the Read Status
command. Only Read Status and Reset commands are valid during programming. When the Page Program operation is completed,
the host controller can check the Status bit (I/O0) to see if the Page Program operation is successfully done. The command register
remains the Read Status mode unless another valid command is written to it.

A page program sequence is illustrated in Figure below, where column address, page address, and data input are placed in between
80h and 10h. After tPROG program time, the R/ B de-asserts to ready state. Read Status command (70h) can be issued right after 10h.

Program & Read Status Operation

Random Data Input In a page

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 32/51
ESMT F59L1G81MB (2M)
Cache Program
Cache Program is an extension of Page Program, which is executed with 2,112 byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.

After writing the first set of data up to 2,112 bytes into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache
registers to data registers, the device remains in Busy state for a short period of time (t CBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail status of only the
previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5)
for internal Ready/Busy may be polled to identity the completion of internal programming. If the system monitors the progress of
programming only with R/ B , the last page of the target programming sequence must be programmed with actual Page Program
command (10h).

Cache Program (available only within a block)

Note:
1. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after
completion of the previous cycle, which can be expressed as the following formula.
2. tLPROG = Program time for the last page + Program time for the (last-1)th page – (Program command cycle time + Last page data
loading time)

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 33/51
ESMT F59L1G81MB (2M)
Copy-Back Program
Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is
no bit error detected in the stored data. The benefit is particularly obvious when a portion of a block is updated and the rest of the block
needs to be copied to a newly assigned empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of
Copy-Back Program with Destination address. A Read for Copy-Back operation with “35h” command and the Source address moves
the whole 2,112byte data into the internal buffer. The host controller can detect bit errors by sequentially reading the data output.
Copy-Back Program is initiated by issuing Page-Copy Data-Input command (85h) with Destination address. If data modification is
necessary to correct bit errors and to avoid error propagation, data can be reloaded after the Destination address. Data modification
can be repeated multiple times as shown in Figure below. Actual programming operation begins when Program Confirm command
(10h) is issued. Once the program process starts, the Read Status command (70h) may be entered to read the status register. The
host controller can detect the completion of a program cycle by monitoring the R/ B output, or the Status bit (I/O6) of the Status
Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The command register remains Read
Status mode until another valid command is written to it.

Page Copy-Back Program Operation

Page Copy-Back Program Operation with Random Data Input

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 34/51
ESMT F59L1G81MB (2M)
Block Erase
The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a two-cycle row address, in which only
Plane address and Block address are valid while Page address is ignored. The Erase Confirm command (D0h) following the row
address starts the internal erasing process. The two-step command sequence is designed to prevent memory content from being
inadvertently changed by external noise.

At the rising edge of WE after the Erase Confirm command input, the internal control logic handles erase and erase-verify. When the
erase operation is completed, the host controller can check Status bit (I/O0) to see if the erase operation is successfully done. Figure
below illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in between
commands 60h and D0h. After tBERS erase time, the R/ B de-asserts to ready state. Read Status command (70h) can be issued right
after D0h to check the execution status of erase operation.

Block Erase Operation

One-Time Programmable (OTP) Operations

This device flash device offers one-time programmable memory area. Thirty full pages of OTP data are available on the device, and the
entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands.
The OTP area leaves the factory in an unwritten state. The OTP area cannot be erased, whether it is protected or not. Protecting the
OTP area prevents further programming of that area.
The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation mode, issue the Set Feature
(EFh-90h-01h) command. When the device is in OTP operation mode, subsequent Read and/or Page Program are applied to the OTP
area. When you want to come back to normal operation, you need to use EFh-90h-00h for OTP mode release. Otherwise,
device will stay in OTP mode.
To program an OTP page, issue the Serial Data Input (80h) command followed by address cycles. The number of address cycles
depends on the memory density; 4-byte address input is needed for 512Mb or 1Gb product, while 5-byte address input is needed for
2Gb or 4Gb product. The first two address cycles are column address that must be set as 00h. For the third cycle, select a page in the
range of 00h through 1Dh. The fourth and fifth cycle is fixed at 00h. Next, up to 2,112 bytes of data can be loaded into data register.
The bytes other than those to be programmed do not need to be loaded. Random Data Input (85h) command in this device is
prohibited. The Page Program confirm (10h) command initiates the programming process. The internal control logic automatically
executes the programming algorithm, timing and verification. Please note that no partial-page program is allowed in the OTP area. In
addition, the OTP pages must be programmed in the ascending order. A programmed OTP page will be automatically protected.
Similarly, to read data from an OTP page, set the device to OTP operation mode and then issue the Read (00h-30h) command. The
first two address cycles are column address that must be set as 00h and Random Data Output (05h-E0h) command is prohibited as
well.
All pages in the OTP area will be protected simultaneously by issuing the Set Feature (EFh-90h-03h) command to set the device to
OTP protection mode. After the OTP area is protected, no page in the area is programmable and the whole area cannot be
unprotected.
The Read Status (70h) command is the only valid command for reading status in OTP operation mode.

OTP Modes and Commands Table

Set feature Command
1 2
Read EFh-90h -01h 00h-30h
OTP Operation mode
Page Program EFh-90h-01h 80h-10h
OTP Protection mode Program Protect EFh-90h-03h 80h-10h
OTP Release mode Leave OTP mode EFh-90h-00h
NOTE:
1. 90h is OTP status register address.
2. 00h, 01h, and 03h are OTP status register data values.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 35/51
ESMT F59L1G81MB (2M)
OTP Area Details Table
Description Value
Number of OTP pages 30
OTP page address 00h – 1Bh
Number of partial page programs for each page in the OTP area 1
NOTE:
1. OTP page address 1Ch and 1Dh are also able to access, however, they both are read only for test mark.

Read Status
A status register on the device is used to check whether program or erase operation is completed and whether the operation is
completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the status register to
I/O pins on the falling edge of CE or RE , whichever occurs last. These two commands allow the system to poll the progress of each
device in multiple memory connections even when R/ B pins are common-wired. RE or CE does not need to toggle for status
change.

The command register remains in Read Status mode unless other commands are issued to it. Therefore, if the status register is read
during a random read cycle, a read command (00h) is needed to start read cycles.

Status Register Definition for 70h Command

I/O Page Program Block Erase Cache Program Read Cache Read Definition
I/O0 Pass / Fail Pass / Fail NA NA NA Pass: ”0” Fail: ”1”
I/O1 NA NA NA NA NA Don’t cared
NA
I/O2 NA NA NA NA Don’t cared
(Pass / Fail, OTP)
I/O3 NA NA NA NA NA Don’t cared
I/O4 NA NA NA NA NA Don’t cared
True True Busy: ”0”
I/O5 NA NA NA
Ready / Busy Ready / Busy Ready: ”1”
Busy: ”0”
I/O6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy
Ready: ”1”
Protected: ”0”
I/O7 Write Protect Write Protect Write Protect Write Protect Write Protect
Not Protected: ”1”

Note:
1. I/Os defined NA are recommended to be masked out when Read Status is being executed.
2. N: current page, N-1: previous page.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 36/51
ESMT F59L1G81MB (2M)
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h.
Four read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th and 5th cycle ID respectively. The
command register remains in Read ID mode until further commands are issued to it.

Read ID Operation

ID Definition Table
ID Access command = 90h
ID Definition Table (00h)
rd th th
Maker Code Device Code 3 Cycle 4 Cycle 5 Cycle
C8h D1h 80h 95h 40h

ID Definition Table (20h)

st nd rd th
1 Cycle 2 Cycle 3 Cycle 4 Cycle
4Fh 4Eh 46h 49h

Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the
Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/ B pin changes to low for tRST after the Reset command is written. Refer to Figure below.

Device Status
After Power-up After Reset
Operation mode 00h Command is latched Waiting for next command

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 37/51
ESMT F59L1G81MB (2M)
Cache Read
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always
issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are
transferred from data registers to cache registers in a short time period of t DCBSYR, and then data of the next page (page N+1) is
transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and
achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used
to complete data transfer from memory cells to data registers.

Read Operation with Cache Read

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 38/51
ESMT F59L1G81MB (2M)
READY/ BUSY
The device has a R/ B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/ B pin is normally high but transition to low after program or erase command is written to the command
register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/ B outputs to be Or-tied. Because pull-up resistor value is related to tr (R/ B )
and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart. Its value can be
determined by the following guidance.

RP vs tRHOH vs CL

where IL is the sum of the input currents of all devices tied to the R/ B pin.
RP (max) is determined by maximum permissible limit of tr

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 39/51
ESMT F59L1G81MB (2M)
Data Protection & Power-up sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.

The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the
initialization the device R/ B signal indicates the Busy state as shown in the figure below. In this time period, the acceptable
commands are 70h.

The WP signal is useful for protecting against data corruption at power on/off.

AC Waveforms for Power Transition

Write Protect Operation

Enable WP during erase and program busy is prohibited. The erase and program operations are enabled and disable as follows.

Enable Programming:

Note: WP keeps “High” until programming finish.

Disable Programming:

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 40/51
ESMT F59L1G81MB (2M)
Enable Eraseing:

Note: WP keeps “High” until erasing finish.

Disable Erasing:

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 41/51
ESMT F59L1G81MB (2M)
BLOCK LOCK Operation

The block lock feature protects either the entire device ranges of blocks from being programmed and erased. Using the block lock
feature is preferable to using WP to prevent PRORAM and ERASE operations. Contact to ESMT for using this feature.

Read Parameter Page Operation

Read Parameter Page (ECh) command is used to read the ONFI parameter page programmed into the target. This command is
accepted by the target only when the die(s) on the target is idle. Writing ECh to the command register puts the target in read parameter
page mode. The target stays in this mode until another valid command is issued.
When ECh command is followed by one 00h address cycle, the target goes busy for tR. If the Read Status (70h) command is used to
monitor for command completion, the Read mode (00h) command must be used to re-enable data output mode.
A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. Random Data Output
(05h-E0h) can be used to change the location of data output.

Read Parameter Page Operation

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 42/51
ESMT F59L1G81MB (2M)
Byte Description Value
0-3 Parameter page signature ("O", "N", "F", "I") 4Fh, 4Eh, 46h, 49h
4-5 Revision number 02h, 00h
6-7 Features supported 10h, 00h
8-9 Optional commands supported 33h, 00h
10-31 Reserved All 00h
50h, 4Fh, 57h, 45h, 52h, 43h, 48h, 49h, 50h,
32-43 Device manufacturer
20h, 20h, 20h
50h, 53h, 55h, 31h, 47h, 41h, 33h, 30h, 44h,
44-63 Device model 54h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h

64 Manufacturer ID C8h
65-66 Date code 00h, 00h
67-79 Reserved All 00h
80-83 Number of data bytes per page 00h, 08h, 00h, 00h
84-85 Number of spare bytes per page 40h, 00h
86-89 Number of data bytes per partial page 00h, 02h, 00h, 00h
90-91 Number of spare bytes per partial page 10h, 00h
92-95 Number of pages per block 40h, 00h, 00h, 00h
96-99 Number of blocks per unit 00h, 04h, 00h, 00h
100 Number of logical units 01h
101 Number of address cycles 22h
102 Number of bits per cell 01h
103-104 Number of maximum bad blocks per unit 14h, 00h
105-106 Block endurance 01h, 05h
107 Guaranteed valid blocks at beginning of target 01h
108-109 Block endurance of guaranteed valid blocks 00h, 00h
110 Number of partial programs per page 04h
111 Partial programming attributes 00h
112 Number of bits ECC 04h
113 Number of Interleaved address bits 00h
114 Interleaved operation attributes 00h
115-127 Reserved All 00h
128 I/O pin capacitance 08h
129-130 Timing mode support 1Fh, 00h
131-132 Program cache timing mode support 1Fh, 00h
133-134 tPROG (max) EEh, 02h
135-136 tBERS (max) 10h, 27h
137-138 tR (max) 19h, 00h
139-140 tCCS (min) 64h, 00h

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 43/51
ESMT F59L1G81MB (2M)
141-163 Reserved All 00h
164-165 Vendor-specific revision number 01h, 00h
Two-Plane Page Read support
166 Bit[7:1]: Reserved (0) 00h
Bit 0: 0= Doesn’t support Two Plane Page Read
Read cache support
167 Bit[7:1]: Reserved (0) 00h
Bit 0: 0= Doesn’t support ONFI-specific read cache
Read Unique ID support
168 Bit[7:1]: Reserved (0) 00h
Bit 0: 0= Doesn’t support ONFI-specific Read Unique ID
Programmable output impedance support
169 Bit[7:1]: Reserved (0) 00h
Bit 0: 0= Doesn’t support programmable output impedance support
Number of programmable output impedance support
settings
170 00h
Bit[7:3]: Reserved (0)
Bit[2:0]: Number of programmable IO output impedance settings
171 Reserved 00h
Programmable R / B pull-down strength support
172 Bit[7:1]: Reserved (0) 00h
Bit 0: 0= Doesn’t support programmable R / B pull-down strength
173 Reserved 00h
Number of programmable R / B pull-down strength support
174 Bit[7:3]: Reserved (0) 00h
Bit[2:0]: Number of programmable R / B pull-down strength settings
OTP mode support
Bit[7:2]: Reserved (0)
175 01h
Bit 1: 0= Doesn’t support Get/Set Feature command set
Bit 0: 1= support OTP mode
OTP page start
176 00h
Bit[7:0] = Page where OTP page space begins
OTP Data Protect address
177 00h
Bit[7:0] = Page address to use when issuing OTP Data Protect command
Number of OTP pages
178 Bit[15:5]: Reserved (0) 1Ch
Bit[4:0] = Number of OTP pages
179 OTP Feature Address 90h
180-253 Reserved All 00h
254-255 Integrity CRC Set at test
256-511 Values of bytes 0-255 Values of bytes 0-255
512-767 Values of bytes 0-255 Values of bytes 0-255
768+ Additional redundant parameter pages

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 44/51
ESMT F59L1G81MB (2M)
Read Unique ID Operation

Read Unique ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the
target only when the die(s) on the target is idle. Writing EDh to the command register puts the target in read unique ID mode. The target
stays in this mode until another valid command is issued.
When EDh command is followed by one 00h address cycle, the target goes busy for tR. If the Read Status (70h) command is used to
monitor for command completion, the Read mode (00h) command must be used to re-enable data output mode. After tR completes,
the host enables data output mode to read the unique ID.
Sixteen copies of the unique ID data are store in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique ID
data, and the second 16 bytes are the complement of the first 16 bytes of FFh, then that copy of the unique ID data is correct. In the
event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. Random
Data Output (05h-E0h) can be used to change the location of data output.

Read Unique ID Operation

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 45/51
ESMT F59L1G81MB (2M)
PACKING DIMENSION

48-LEAD TSOP(I) ( 12x20 mm )

Dimension in mm Dimension in inch Dimension in mm Dimension in inch

Symbol Symbol
Min Norm Max Min Norm Max Min Norm Max Min Norm Max
A ------- ------- 1.20 ------- ------- 0.047 D 20.00 BSC 0.787 BSC
A1 0.05 ------- 0.15 0.006 ------- 0.002 D1 18.40 BSC 0.724 BSC
A2 0.95 1.00 1.05 0.037 0.039 0.041 E 12.00 BSC 0.472 BSC
b 0.17 0.22 0.27 0.007 0.009 0.011 e 0.50 BSC 0.020 BSC
b1 0.17 0.20 0.23 0.007 0.008 0.009 L 0.50 0.60 0.70 0.020 0.024 0.028
O O O O
c 0.10 ------- 0.21 0.004 ------- 0.008 θ 0 ------- 8 0 ------- 8
c1 0.10 ------- 0.16 0.004 ------- 0.006

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 46/51
ESMT F59L1G81MB (2M)
PACKING DIMENSIONS

48-BALL Flash ( 6.5x5 mm )

Pin#1
Index side

A2
E

A
A1
Seating plane

"A"

D1
e

ob
E1

Detail "B"

"B"

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max
A － － 0.80 － － 0.031
A1 0.22 0.27 0.32 0.009 0.011 0.013
A2 － 0.48 － － 0.019 －
Φb 0.30 0.35 0.40 0.012 0.014 0.016
D 4.90 5.00 5.10 0.193 0.197 0.201
E 6.40 6.50 6.60 0.252 0.256 0.260
D1 4.00 BSC 0.157 BSC
E1 5.60 BSC 0.220 BSC
e 0.80 BSC 0.031 BSC
Controlling dimension : Millimeter.
(Revision date : Apr 10 2018)

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 47/51
ESMT F59L1G81MB (2M)
PACKING DIMENSIONS
63-BALL 1G NAND Flash ( 9x11 mm )
E

Pin #1

A2
A

A1
Seating plane
C ccc C

Detail A

Detail A

e e

Solder ball
e
e

b
D1

Detail B

Pin #1
Index

Detail B E1

Dimension in mm Dimension in inch

Symbol
Min Norm Max Min Norm Max
A － － 1.00 － － 0.039
A1 0.25 － 0.35 0.010 － 0.014
A2 0.60 BSC 0.024 BSC
Φb 0.40 － 0.50 0.016 － 0.020
D 10.90 11.00 11.10 0.429 0.433 0.437
E 8.90 9.00 9.10 0.350 0.354 0.358
D1 8.80 BSC 0.346 BSC
E1 7.20 BSC 0.283 BSC
e 0.8 BSC 0.031 BSC
ccc － － 0.10 － － 0.004
Controlling dimension : Millimeter.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 48/51
ESMT F59L1G81MB (2M)
PACKING DIMENSIONS

67-BALL Flash ( 6.5x8 mm )

Pin# 1
index

A2
A
E
Seating plane

A1
Detail "A"

"A"

D1
e
e

Φb
E1

Pin# 1
index Detail "B"

"B"

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max
A － － 1.00 － － 0.039
A1 0.22 0.27 0.32 0.009 0.011 0.013
A2 0.61 0.66 0.71 0.024 0.026 0.028
Φb 0.30 0.35 0.40 0.012 0.014 0.016
D 6.40 6.50 6.60 0.252 0.256 0.260
E 7.90 8.00 8.10 0.311 0.315 0.319
D1 5.60 BSC 0.220 BSC
E1 7.20 BSC 0.283 BSC
e 0.80 BSC 0.031 BSC
Controlling dimension : Millimeter.
(Revision date : Jun 29 2014)

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 49/51
ESMT F59L1G81MB (2M)
Revision History
Revision Date Description

0.1 2017.07.26 Original

0.2 2017.08.08 Modify BLOCK LOCK Operation description
1. Delete Preliminary
1.0 2018.08.17
2. Correct typo
1.1 2018.11.27 Add 48 ball BGA packing (6.5x5mm)
1.2 2019.05.08 Modify the value of parameter page table
1.3 2021.12.24 Add the operating temperature to features list

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 50/51
ESMT F59L1G81MB (2M)

Important Notice
All rights reserved.

No part of this document may be reproduced or duplicated in any form or

by any means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at

the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.

The information contained herein is presented only as a guide or

examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.

Any semiconductor devices may have inherently a certain rate of failure.

To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.

ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.

Elite Semiconductor Microelectronics Technology Inc. Publication Date: Dec. 2021

Revision: 1.3 51/51