AP7176B

3A ULTRA LOW DROPOUT LINEAR REGULATOR WITH ENABLE

Description Pin Assignments

The AP7176B is a 3.0A ultra low-dropout (LDO) linear regulator that
features an enable input and a power-good output.

The enable input and power-good output allow users to configure

power management solutions that can meet the sequencing
requirements of FPGAs, DSPs, and other applications with different
start-up and power-down requirements.
NEW PRODUCT

The AP7176B features two supply inputs, for power conversion

supply and control. With the separation of the control and the power
input very low dropout voltages can be reached and power dissipation
is reduced.

A precision reference and feedback control deliver 1.5% accuracy

over load, line, and operating temperature ranges.

The AP7176B is available in SO-8EP, MSOP-8EP and U-DFN3030-

10 package with an exposed PAD to reduce the junction to case
resistance and extend the temperature range it can be used in.

(Top View)
Features
1 10
• VIN Range: 1.2V to 3.65V VCNTL 3.0V to 5.5V VOUT VCNTL
2 9
• Adjustable Output Voltage VOUT VIN
• Continuous Output Current IOUT = 3A 3 8
VOUT GND VIN
• Fast Transient Response 4 7
FB VIN
• Power on reset monitoring on VCNTL and VIN
5 6
• Internal Soft-Start PG 11 EN
• Stable with Low ESR MLCC Capacitors
U-DFN3030-10
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. “Green” Device (Note 3)

Applications
• Notebook
• PC
• Netbook
• Wireless Communication
• Server
• Motherboard
• Dongle
• Front Side Bus VTT (1.2V/3.3A)

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.

AP7176B 1 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Typical Applications Circuit

NEW PRODUCT

Figure 1 Typical Application Circuit

Pin Descriptions
Pin Pin Number
Function
Name SO-8EP MSOP-8EP U-DFN3030-10
Power Good.Output open drain to indicate the status of VOUT via monitoring the FB pin.
PG 1 1 5 This pin is pulled low when the voltage is outside the limits, during thermal shutdown and
if either VCNTL or VIN go below their thresholds.
Enable Pin. Driving this pin low will disable the part. When left floating an internal current
EN 2 2 6
source will pull this pin high and enable it.
Power Input Pin for current supply. Connect a decoupling capacitor (≥10µF) as close as
VIN 3 3 7,8,9
possible to the pin for noise filtering
BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor (≥1µF)
VCNTL 4 4 10
as close as possible to the pin for noise filtering.
NC 5 5 No Connection
VOUT 6 6 1,2,3 Power output pin
FB 7 7 4 Feedback to set the output voltage via an external resistor divider between VOUT and GND
GND 8 8 11 Ground
PAD EP EP EP Exposed pad connected to GND for good thermal conductivity

Functional Block Diagram

AP7176B 2 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.)

Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 to +4.0 V
VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 to +7.0 V
VOUT VOUT to GND Voltage -0.3 to VIN +0.3 V
PG to GND Voltage -0.3 to +7.0 V
EN, FB to GND Voltage -0.3 to VCNTL +0.3 V
Power Dissipation (SO-8EP) 1.7
PD Power Dissipation (MSOP-8EP) 1.5 W
NEW PRODUCT

Power Dissipation (U-DFN3030-10) 1.9

TJ Maximum Junction Temperature 150 °C
TSTG Storage Temperature -65 to +150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Note: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may
be affected by exposure to absolute maximum rating conditions for extended periods of time.

Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.)

Symbol Parameter Test Condition Range Unit
VCNTL VCNTL Supply Voltage 3.0 to 5.5 V
VIN VIN Supply Voltage 1.2 to 3.65 V
VOUT VOUT Output Voltage (when VCNTL - VOUT >1.9V) 0.8 to VIN – VDROP V
IOUT VOUT Output Current 0 to 3 A
IOUT = 3A at 25% nominal VOUT 8 to 1100
COUT VOUT Output Capacitance IOUT = 2A at 25% nominal VOUT 8 to 1700 µF
IOUT = 1A at 25% nominal VOUT 8 to 2400
ESRCOUT ESR of VOUT Output Capacitor 0 to 200 mΩ
TA Ambient Temperature -40 to +85 °C
TJ Junction Temperature -40 to +125 °C

Electrical Characteristics (Specifications apply over VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40°C to +85°C, typical values
@TA = +25°C, unless otherwise specified.)

AP7176B
Symbol Parameter Conditions Unit
Min Typ Max
SUPPLY CURRENT
IVCNTL VCNTL Supply Current EN = VCNTL, IOUT = 0A — 1.0 1.5 mA
ISD VCNTL Supply Current at Shutdown EN = GND — 15 30 µA
VIN Supply Current at Shutdown EN = GND, VIN = 3.65V — — 1 µA
POWER-ON-RESET (POR)
Rising VCNTL POR Threshold 2.50 2.70 2.95 V
VCNTL POR Hysteresis — 0.4 — V
Rising VIN POR Threshold 0.8 0.9 1.0 V
VIN POR Hysteresis — 0.5 — V

AP7176B 3 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Electrical Characteristics (cont.) (Specifications apply over VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40°C to +85°C, typical
values @TA = +25°C, unless otherwise specified.)

AP7176B
Symbol Parameter Conditions Unit
Min Typ Max
OUTPUT VOLTAGE
Reference Voltage FB=VOUT — 0.8 — V
VCNTL = 3.0 ~ 5.5V, IOUT = 0~3A,
Output Voltage Accuracy -1.5 — +1.5 %
TJ = -40 to +125°C
VREF Load Regulation IOUT =0A to 3A — 0.06 0.25 %
Line Regulation IOUT =10mA, VCNTL = 3.0 to 5.5V -0.15 — +0.15 %/V
NEW PRODUCT

VOUT Pull-low Resistance VCNTL = 3.3V, VEN = 0V, VOUT <0.8V — 10 — Ω

FB Input Current VFB = 0.8V -100 — +100 nA
DROPOUT VOLTAGE
TJ = 25°C — 0.33 0.38
VOUT = 2.5V
TJ = -40°C to +125°C — 0.53
VIN-to-VOUT Dropout Voltage VCNTL = 5.0V, TJ = +25°C — 0.31 0.36
VDROP VOUT = 1.8V V
(Note 5) IOUT = 3A TJ = -40°C to +125°C — 0.50
TJ = +25°C — 0.30 0.35
VOUT = 1.2V
TJ = -40°C to +125°C — — 0.48
TJ = +25°C, VOUT = 80% VNOMINAL 4.5 5.7 6.7 A
ILIM Current-Limit Level
TJ = -40°C to +125°C 4.2 — — A
PROTECTIONS
ISHORT Short Current-Limit Level VFB < 0.2V — 1.1 — A
TSD Thermal Shutdown Temperature TJ rising — 170 — °C
Thermal Shutdown Hysteresis — 50 — °C
ENABLE AND SOFT-START
EN Logic High Threshold Voltage VEN rising 0.5 0.8 1.1 V
EN Hysteresis — 0.1 — V
EN Pull-High Current EN = GND — 5 — µA
TSS Soft-Start Interval 0.3 0.6 1.2 ms
Turn On Delay From being enabled to VOUT rising 10% 200 350 500 µs
POWER-GOOD AND DELAY
VTHPG Rising PG Threshold Voltage VFB rising 90 92 95 %
PG Threshold Hysteresis — 8 — %
PG Pull-low Voltage PG sinks 5mA — 0.25 0.4 V
PG Debounce Interval VFB < falling PG voltage threshold — 10 — µs
PG Delay Time From VFB = VTHPG to rising edge of the VPG 1 2 4 ms
THERMAL CHARACTERISTIC
SO-8EP (Note 6) — 70 — °C/W
Thermal Resistance Junction-to-
θJA MSOP-8EP (Note 7) — 80 — °C/W
Ambient
U-DFN3030-10 (Note 6) — 60 — °C/W
Thermal Resistance Junction-to- SO-8EP (Note 6) — 30 — °C/W
θJC
Ambient MSOP-8EP (Note 7) — 30 — °C/W
U-DFN3030-10 (Note 6) — 20 — °C/W
Notes: 5. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops 2% below its nominal value.
6. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and thermal vias to bottom layer ground
plane.
7. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper,with minimum recommended pad layout.

AP7176B 4 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Typical Characteristics
NEW PRODUCT

AP7176B 5 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Typical Characteristics (cont.)

NEW PRODUCT

AP7176B 6 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Typical Characteristics (cont.)

NEW PRODUCT

AP7176B 7 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Operating Waveforms (Test Conditions VIN = 1.8V, VCNTL = 5V, VOUT 1.2V, TA = +25°C unless otherwise specified.)
Power On Power Off

VCNTL

VCNTL

VIN VIN

VOUT
VOUT
NEW PRODUCT

VPG VPG

COUT =10µF, CIN =10µF, RL = 0.4Ω COUT = 10µF, CIN =10µF, RL = 0.4Ω
CH1: VCNTL, 5V/Div, DC CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC CH2: VIN, 1V/Div, DC
CH3: VOUT, 1V/Div, DC CH3: VOUT, 1V/Div, DC
CH4: VPG, 5V/Div, DC CH4: VPG, 5V/Div, DC
TIME: 2ms/Div TIME: 2ms/Div

Load Transient Response Over Current Protection

VOUT
VOUT

IOUT
IOUT

IOUT = 10mA to 3A to10mA (rise / fall time = 1µs) COUT = 10µF, CIN = 10µF, IOUT = 2A to 5.6A
COUT = 10µF, CIN = 10µF CH1: VOUT, 0.5V/Div, DC
CH2: VOUT, 50mV/Div, AC CH4: IOUT, 2A/Div, DC
CH4: IOUT, 1A/Div, DC TIME: 0.2ms/Div
TIME: 50µs/Div

Shutdown Enable

VEN VEN

VOUT
VOUT

VPG VPG

IOUT
IOUT

COUT = 10µF, CIN = 10µF, RL = 0.4Ω COUT = 10µF, CIN = 10µF, RL = 0.4Ω
CH1: VEN, 5V/Div, DC CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC CH2: VOUT, 1V/Div, DC
CH3: VPG, 5V/Div, DC CH3: VPG, 5V/Div, DC
CH4: IOUT, 2A/Div, DC CH4: IOUT, 2A/Div, DC
TIME: 4µs/Div TIME: 1ms/Div

AP7176B 8 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Application Information
Power Good and Delay
AP7176B monitors the feedback voltage VFB on the FB pin. An internal delay timer is started after the PG voltage threshold (VTHPG) on the FB pin
is reached. At the end of the delay time an internal NMOS of the PG is turned off to indicate that the power at the output is good (PG). This
monitoring function is continued during operation and if VFB falls 8% (typ) below VTHPG, the NMOS of the PG is turned on after a delay time of
typical 10µs to avoid oscillating of the PG signal.

Power On Reset
AP7176B monitors both supply voltages, VCNTL and VIN to ensure operation as intended. A Soft-Start process is initiated after both voltages
exceed their POR threshold during power on. During operation the POR component continues to monitor the supply voltage and pulls the PG low
NEW PRODUCT

to indicate an out of regulation supply. This function will engage without regard to the status of the output.

Soft-Start
AP7176B incorporates an internal Soft-Start function. The output voltage rise is controlled to limit the current surge during start-up. The typical
Soft-Start time is 0.6ms

Current-Limit Protection
AP7176B monitors the current flow through the NMOS and limits the maximum current to avoid damage to the load and AP7176B during
overload conditions.

Short Circuit Current-Limit Protection

AP7176B incorporates a current limit function to reduce the maximum current to 1.1A (typ) when the voltage at FB falls below 0.2V (typ) during
an overload or short circuit situation.

During start-up period, this function is disabled to ensure successful heavy load start-up.

Enable Control
If the enable pin (EN) is left open, an internal current source of ~5µA pulls the pin up and enables the AP7176B. This will reduce the bill of
material saving an external pull up resistor. Driving the enable pin low disables the device. Driving the pin high subsequently initiates a new Soft-
Start cycle.

Output Voltage Regulation

Output Voltage is set by resistor divider from VOUT via FB pin to GND. Internally VFB is compared to a 0.8V temperature compensated reference
voltage and the NMOS pass element regulates the output voltage while delivering current from VIN to VOUT.

Setting the Output Voltage

A resistor divider connected to FB pin programs the output voltage.
⎛ R1 ⎞
V OUT = VREF ∗ ⎜1 + ⎟V
⎝ R2 ⎠
R1 is connected from VOUT to FB with Kelvin sensing connection. R2 is connected from FB to GND. To improve load transient response and
stability, a bypass capacitor can be connected in parallel with R1. (optional in typical application circuit)

Power Sequencing
AP7176B requires no specific sequencing between VIN and VCNTL. However, care should be taken to avoid forcing VOUT for prolonged times
without the presence of VIN. Conduction through internal parasitic diode (from VOUT to VIN) could damage AP7176B.

Thermal Shutdown
The PCB layout and power requirements for AP7176B under normal operation condition should allow enough cooling to restrict the junction
temperature to +125°C. The packages for AP7176B have an exposed PAD to support this. These packages provide better connection to the
PCB and thermal performance. Refer to the layout considerations.

If AP7176B junction temperature reaches +170°C a thermal protection block disables the NMOS pass element and lets the part cool down. After
its junction temperature drops by 50°C (typ), a new Soft-Start cycle will be initiated. A new thermal protection will start, if the load or ambient
conditions continue to raise the junction temperature to +170°C. This cycle will repeat until normal operation temperature is maintained again.

AP7176B 9 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B

Application Information (cont.)

Output Capacitor
An output capacitor (COUT) is needed to improve transient response and maintain stability. The ESR (equivalent series resistance) and
capacitance drives the selection. Care needs to be taken to cover the entire operating temperature range.

The output capacitor can be an Ultra-Low-ESR ceramic chip capacitor or a low ESR bulk capacitor like a solid tantalum, POSCap or aluminum
electrolytic capacitor.

COUT is used to improve the output stability and reduces the changes of the output voltage during load transitions. The slew rate of the current
sensed via the FB pin in AP7176B is reduced. If the application has large load variations, it is recommended to utilize low-ESR bulk capacitors.
NEW PRODUCT

It is recommended to place ceramic capacitors as close as possible to the load and the ground pin and care should be taken to reduce the
impedance in the layout.

Input Capacitor
To prevent the input voltage from dropping during load steps it is recommended to utilize an input capacitor (CIN). As with the output capacitor
the following are acceptable, Ultra-Low-ESR ceramic chip capacitor or low ESR bulk capacitor like a solid tantalum, POSCap or aluminum
electrolytic capacitor. Typically it is recommended to utilize an capacitance of at least 10µF to avoid output voltage drop due to reduced input
voltage. The value can be lower if VIN changes are not critical for the application.

Layout Consideration
For good ground loop and stability, the input and output capacitors should be located close to the input, output, and ground pins of the device.
No other application circuit is connected within the loop. Avoid using vias within ground loop. If vias must be used, multiple vias should be used
to reduce via inductance.

The regulator ground pin should be connected to the external circuit ground to reduce voltage drop caused by trace impedance. Ground plane is
generally used to reduce trace impedance.

Wide trace should be used for large current paths from VIN to VOUT, and load circuit.

Place the R1, R2, and C1 (optional) near the LDO as close as possible to avoid noise coupling.

R2 is placed close to device ground. Connect the ground of the R2 to the GND pin by using a dedicated trace.

Connect the pin of the R1 directly to the load for Kelvin sensing.

No high current should flow through the ground trace of feedback loop and affect reference voltage stability.

For the packages with exposed pads, heat sinking is accomplished using the heat spreading capability of the PCB and its copper traces.
Suitable PCB area on the top layer and thermal vias (0.3mm drill size with 1mm spacing, 4 to 8 vias at least) to the VIN power plane can help to
reduce device temperature greatly.

Reference Layout Plots:

Top Layer Bottom Layer

GND C1

1 R2
PG
R1
EN
GND
Vin Vout
FB

Vcntl
Cin Ccntl Cout Vcntl

GND

AP7176B 10 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B
Ordering Information
NEW PRODUCT

Package 13” Tape and Reel

Part Number Packaging
Code Quantity Part Number Suffix
AP7176BSP-13 SP SO-8EP 2500/Tape & Reel -13
AP7176BMP-13 MP MSOP-8EP 2500/Tape & Reel -13
AP7176BFN-7 FN U-DFN3030-10 3000/Tape & Reel -7

Marking Information
(1) SO-8EP

(2) MSOP-8EP

(3) U-DFN3030-10

( Top View )
XX : Identification Code
XX Y : Year : 0~9
YWX W : Week : A~Z : 1~26 week;
a~z : 27~52 week; z represents
52 and 53 week
X : A~Z : Green
Part No. Package Identification Code
AP7176B U-DFN3030-10 A7

AP7176B 11 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B
Package Outline Dimensions (All dimensions in mm.)
Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for latest version.
(1) SO-8EP

Exposed Pad
8 5
SO-8EP (SOP-8L-EP)
E1
Dim Min Max Typ
H A 1.40 1.50 1.45
A1 0.00 0.13 -
1 4
F b 0.30 0.50 0.40
C 0.15 0.25 0.20
NEW PRODUCT

D 4.85 4.95 4.90

b
Bottom View
E 3.80 3.90 3.85
E0 3.85 3.95 3.90
E E1 5.90 6.10 6.00
9° (All sides) N
45° e - - 1.27
7°
Q F 2.75 3.35 3.05
A 4° ± 3° C H 2.11 2.71 2.41
Gauge Plane
Seating Plane L 0.62 0.82 0.72
e E0 N - - 0.35
A1
D L
Q 0.60 0.70 0.65
All Dimensions in mm
(2) MSOP-8EP

D
MSOP-8EP
Dim Min Max Typ
A - 1.10 -
4X A1 0.05 0.15 0.10
10
D1 ° A2 0.75 0.95 0.86
0.25

x A3 0.29 0.49 0.39

E E2 b 0.22 0.38 0.30
Gauge Plane
Seating Plane c 0.08 0.23 0.15
y D 2.90 3.10 3.00
a

4X D1 1.60 2.00 1.80

10 L
° E 4.70 5.10 4.90
1
e 8Xb E1 2.90 3.10 3.00
E3 Detail C E2 1.30 1.70 1.50
A1 A3 E3 2.85 3.05 2.95
c
A A2 e - - 0.65
L 0.40 0.80 0.60
D E1 a 0° 8° 4°
x - - 0.750
See Detail C
y - - 0.750
All Dimensions in mm

AP7176B 12 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B
Package Outline Dimensions (cont.) (All dimensions in mm.)
Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for latest version.
(3) U-DFN3030-10
A3
A
U-DFN3030-10
SEATING PLANE
A1 Dim Min Max Typ
A 0.57 0.63 0.60
D A1 0 0.05 0.02
Pin#1 ID
D2 A3 ⎯ ⎯ 0.15
b 0.20 0.30 0.25
D 2.90 3.10 3.00
D2 2.30 2.50 2.40
NEW PRODUCT

e ⎯ ⎯ 0.50
E E2 E 2.90 3.10 3.00
E2 1.50 1.70 1.60
L 0.25 0.55 0.40
z ⎯ ⎯ 0.375
All Dimensions in mm
L
b
z e

Suggested Pad Layout

Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.
(1) SO8-EP
X2

Value
Dimensions
(in mm)
C 1.270
X 0.802
Y1
Y2 X1 3.502
X1 X2 4.612
Y 1.505
Y1 2.613
Y
Y2 6.500

C X

(2) MSOP-8EP
X C

Y Value
G Dimensions
(in mm)
C 0.650
G 0.450
X 0.450
Y2 Y1 X1 2.000
X1 Y 1.350
Y1 1.700
Y2 5.300

AP7176B 13 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.

 AP7176B
Suggested Pad Layout
Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.

(3) U-DFN3030-10
Y C

X1
G
Dimensions Value (in mm)
Z 2.60
X G 0.15
X 1.80
X1 0.60
NEW PRODUCT

G Y 0.30
C 0.50

IMPORTANT NOTICE

DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume
all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated
website, harmless against all damages.

Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.

Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings
noted herein may also be covered by one or more United States, international or foreign trademarks.

This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.

LIFE SUPPORT

Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:

A. Life support devices or systems are devices or systems which:

1. are intended to implant into the body, or

2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.

B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.

Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.

Copyright © 2014, Diodes Incorporated

www.diodes.com

AP7176B 14 of 14 April 2014

Document number: DS35818 Rev.3 - 2 www.diodes.com © Diodes Incorporated

Downloaded from Arrow.com.