// Full Adder Module: Computes sum and carry for single-bit addition
module fulladder (a, b, cin, sum, carry);
input a, b, cin; // Inputs: Two bits (a, b) and carry-in (cin)
output sum, carry; // Outputs: Sum and carry-out
assign sum = a ^ b ^ cin; // XOR operation for sum calculation
assign carry = (a & b) | (b & cin) | (cin & a); // Carry logic using AND and OR
endmodule
// 4-bit Parallel Adder Module: Adds two 4-bit numbers with carry-in
module parellel (a, b, cin, sum, carry);
input [3:0] a, b; // 4-bit input operands
input cin; // Carry-in
output [3:0] sum; // 4-bit sum output
output carry; // Carry-out
wire [3:1] w; // Internal wires to carry intermediate carries
fulladder fa0(a[0], b[0], cin, sum[0], w[1]); // LSB addition
fulladder fa1(a[1], b[1], w[1], sum[1], w[2]); // Next bit addition
fulladder fa2(a[2], b[2], w[2], sum[2], w[3]); // Next bit addition
fulladder fa3(a[3], .b[3], w[3], sum[3], carry); // MSB addition, final carry-out
endmodule
// Testbench for 4-bit Parallel Adder
module parallel_tb;
reg [3:0] a, b; // 4-bit registers for inputs
reg cin; // Single-bit register for carry-in
wire [3:0] sum; // 4-bit wire for sum output
wire carry; // Wire for carry-out
// Instantiate the parallel adder module
parallel uut (a, b, cin, sum, carry);
initial begin
// First test case
a = 4'b0111; b = 4'b0100; cin = 1'b0;
#10; // Wait 10 time units
// Second test case
a = 4'b1011; b = 4'b0110; cin = 1'b1;
#10; // Wait 10 time units
// End simulation after some time
$finish;
End
initial begin
$monitor($time, " a=%b b=%b cin=%b => sum=%b carry=%b", a, b, cin, sum, carry);
end
endmodule
BOOTH ALGORITHM
// Module definition for Booth's Multiplier
module BoothMul(clk, rst, start, X, Y, valid, Z);
// Input declarations
input clk; // Clock signal
input rst; // Reset signal (active low)
input start; // Start signal to initiate multiplication
input signed [3:0] X, Y; // 4-bit signed inputs (multiplicand and multiplier)
// Output declarations
output signed [7:0] Z; // 8-bit signed output (product)
output valid; // Output signal indicating valid result
// Internal register declarations
reg signed [7:0] Z, next_Z, Z_temp; // Registers to hold the product and intermediate values
reg next_state, pres_state; // Registers for current and next state in FSM
reg [1:0] temp, next_temp; // Registers to hold the concatenated bits of X
reg [1:0] count, next_count; // Counter registers to track the number of iterations
reg valid, next_valid; // Registers for valid signal
// State encoding
parameter IDLE = 1'b0; // IDLE state
parameter START = 1'b1; // START state
// Sequential logic: State and register update on clock edge or reset
always @ (posedge clk or negedge rst) begin
if (!rst) begin
// Asynchronous reset: Initialize all registers to default values
Z <= 8'd0;
valid <= 1'b0;
pres_state <= IDLE;
temp <= 2'd0;
count <= 2'd0;
end else begin
// Update registers with next state values
Z <= next_Z;
valid <= next_valid;
pres_state <= next_state;
temp <= next_temp;
count <= next_count;
end
end
// Combinational logic: Next state and output logic
always @ (*) begin
case (pres_state)
IDLE: begin
// Default assignments for IDLE state
next_count = 2'b0;
next_valid = 1'b0;
if (start) begin
// On start signal, initialize for multiplication
next_state = START;
next_temp = {X[0], 1'b0}; // Concatenate LSB of X with 0
next_Z = {4'd0, X}; // Initialize Z with X in lower 4 bits
} else begin
// Remain in IDLE state
next_state = IDLE;
next_temp = 2'd0;
next_Z = 8'd0;
end
end
START: begin
// Booth's algorithm operation based on temp value
case (temp)
2'b10: Z_temp = {Z[7:4] - Y, Z[3:0]}; // Subtract Y from upper 4 bits of Z
2'b01: Z_temp = {Z[7:4] + Y, Z[3:0]}; // Add Y to upper 4 bits of Z
default: Z_temp = Z; // No operation
endcase
// Prepare for next iteration
next_temp = {X[count + 1], X[count]}; // Update temp with next bits of X
next_count = count + 1'b1; // Increment count
next_Z = Z_temp >>> 1; // Arithmetic right shift of Z_temp
// Check if all bits have been processed
next_valid = (&count) ? 1'b1 : 1'b0; // Set valid signal if count is all ones
next_state = (&count) ? IDLE : START; // Return to IDLE if done, else continue
end
endcase
end
endmodule
