LTC4357

Positive High Voltage

Ideal Diode Controller
Features Description
n Reduces Power Dissipation by Replacing a Power The LTC®4357 is a positive high voltage ideal diode control-
Schottky Diode with an N-Channel MOSFET ler that drives an external N-channel MOSFET to replace a
n 0.5µs Turn-Off Time Limits Peak Fault Current Schottky diode. When used in diode-OR and high current
n Wide Operating Voltage Range: 9V to 80V diode applications, the LTC4357 reduces power consump-
n Smooth Switchover without Oscillation tion, heat dissipation, voltage loss and PC board area.
n No Reverse DC Current The LTC4357 easily ORs power sources to increase total
n Available in 6-Lead (2mm × 3mm) DFN and system reliability. In diode-OR applications, the LTC4357
8-Lead MSOP Packages controls the forward voltage drop across the MOSFET to
ensure smooth current transfer from one path to the other
Applications without oscillation. If the power source fails or is shorted,
a fast turn-off minimizes reverse current transients.
n N + 1 Redundant Power Supplies
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
n High Availability Systems Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
n AdvancedTCA Systems property of their respective owners.

n Telecom Infrastructure
n Automotive Systems

Typical Application
48V, 10A Diode-OR Power Dissipation vs Load Current
6
VINA FDB3632
48V 5
DIODE (MBR10100)
POWER DISSIPATION (W)

IN GATE OUT 4

LTC4357 VDD VOUT TO LOAD 3 POWER

SAVED
GND 2

1
VINB FDB3632
FET (FDB3632)
48V
0
0 2 4 6 8 10
IN GATE OUT CURRENT (A)
4357 TA01b

LTC4357 VDD

GND
4357 TA01

*SEE FIGURES 2 AND 3 FOR ADDITIONAL OPTIONAL COMPONENTS

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LTC4357
Absolute Maximum Ratings (Notes 1, 2)

Supply Voltages Operating Ambient Temperature Range

IN............................................................. –1V to 100V LTC4357C................................................. 0°C to 70°C
OUT, VDD............................................... –0.3V to 100V LTC4357I.............................................. –40°C to 85°C
Output Voltage LTC4357H........................................... –40°C to 125°C
GATE (Note 3)......................... VIN – 0.2V to VIN + 10V LTC4357MP........................................ –55°C to 125°C
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package....................................................... 300°C

pin Configuration
TOP VIEW

TOP VIEW
OUT 1 6 VDD
IN 1 8 OUT
7
IN 2 GND 5 NC NC 2 7 VDD
NC 3 6 NC
GATE 3 4 GND GATE 4 5 GND
MS8 PACKAGE
DCB PACKAGE 8-LEAD PLASTIC MSOP
6-LEAD (2mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 163°C/W
TJMAX = 125°C, θJA = 90°C/W
EXPOSED PAD (PIN 7) PCB GND CONNECTION OPTIONAL

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4357CMS8#PBF LTC4357CMS8#TRPBF LTCXD 8-Lead Plastic MSOP 0°C to 70°C
LTC4357IMS8#PBF LTC4357IMS8#TRPBF LTCXD 8-Lead Plastic MSOP –40°C to 85°C
LTC4357HMS8#PBF LTC4357HMS8#TRPBF LTCXD 8-Lead Plastic MSOP –40°C to 125°C
LTC4357MPMS8#PBF LTC4357MPMS8#TRPBF LTFWZ 8-Lead Plastic MSOP –55°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4357MPMS8 LTC4357MPMS8#TR LTFWZ 8-Lead Plastic MSOP –55°C to 125°C

LEAD FREE FINISH

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4357CDCB#TRMPBF LTC4357CDCB#TRPBF LCXF 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC4357IDCB#TRMPBF LTC4357IDCB#TRPBF LCXF 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC4357HDCB#TRMPBF LTC4357HDCB#TRPBF LCXF 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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 LTC4357
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VOUT = VDD, VDD = 9V to 80V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Operating Supply Range l 9 80 V
IDD Supply Current l 0.5 1.25 mA
IIN IN Pin Current VIN = VOUT ±1V l 150 350 500 µA
IOUT OUT Pin Current VIN = VOUT ±1V l 80 210 µA
DVGATE External N-Channel Gate Drive VDD, VOUT = 20V to 80V l 10 12 15 V
(VGATE – VIN) VDD, VOUT = 9V to 20V l 4.5 6 15 V
IGATE(UP) External N-Channel Gate Pull-Up Current VGATE = VIN, VIN – VOUT = 0.1V l –14 –20 –26 µA
IGATE(DOWN) External N-Channel Gate Pull-Down VGATE = VIN + 5V l 1 2 A
Current in Fault Condition
–
tOFF Gate Turn-Off Time VIN – VOUT = 55mV |––1V, l 300 500 ns
VGATE – VIN < 1V, CGATE = 0pF
DVSD Source-Drain Regulation Voltage VGATE – VIN = 2.5V l 10 25 55 mV
(VIN – VOUT)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 2: All currents into pins are positive, all voltages are referenced to
may cause permanent damage to the device. Exposure to any Absolute GND unless otherwise specified.
Maximum Rating condition for extended periods may affect device Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
reliability and lifetime. IN or 100V above GND. Driving this pin to voltages beyond this clamp may
damage the device.

Typical Performance Characteristics

VDD Current (IDD vs VDD) IN Current (IIN vs VIN) OUT Current (IOUT vs VOUT)
800 400 180
VDD = VOUT = VIN ± 1V VDD = VOUT = VIN + 1V

150
VDD = VOUT = VIN – 1V
600 300 VDD = VOUT = VIN + 1V
120
IOUT (µA)
IDD (µA)

IIN (µA)

400 200 90

60
200 100 VDD = VOUT = VIN – 1V
30

0 0 0
0 20 40 60 80 0 20 40 60 80 0 20 40 60 80
VDD (V) VIN (V) VOUT (V)
4357 G01 4357 G02 4357 G03

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LTC4357
Typical Performance Characteristics
GATE Current vs Forward Drop DVGATE vs GATE Current
(IGATE vs DVSD) (DVGATE vs IGATE) OUT Current (IOUT vs VIN)
25 15 125
$VGATE = 2.5V VOUT = 12V, VIN = VDD

VIN > 18V

100

0 10
VIN = 12V 75

$VGATE (V)
IGATE (µA)

IOUT (µA)
VIN = 9V 50
–25 5

25

–50 0 0
–50 0 50 100 150 0 5 10 15 20 25 0 2 4 6 8 10 12 14
VSD (mV) IGATE (µA) VIN (V)
4357 G06
4357 G04 4357 G05

FET Turn-Off Time FET Turn-Off Time

vs GATE Capacitance vs Initial Overdrive
500 400
VGATE < VIN + 1V VIN = 48V
$VSD = 55mV –1V $VSD = VINITIAL –1V
400
300

300
tOFF (ns)

tPD (ns)

200
200

100
100

0 0
0 20 40 60 80 0 0.2 0.4 0.6 0.8 1.0
CGATE (nF) VINITIAL (V)
4357 G07 4357 G08

FET Turn-Off Time

vs Final Overdrive FET Load Current vs DVSD
2000 10
VIN = 48V VIN = 48V WITH FET (FDB3632)
$VSD = 55mV VFINAL
8
1500
LOAD CURRENT (A)

6
tPD (ns)

1000
4

500
2

0 0
–1 –0.8 –0.6 –0.4 –0.2 0 0 25 50 75
VFINAL (V) ∆VSD (mV)
4357 G10
4357 G09

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 LTC4357
Pin Functions
Exposed Pad: Exposed pad may be left open or connected is used to control the source-drain voltage across the
to GND. MOSFET. The GATE fast pull-down current is returned
through the IN pin. Connect this pin as close as possible
GATE: Gate Drive Output. The GATE pin pulls high, enhanc-
to the MOSFET source.
ing the N-channel MOSFET when the load current creates
more than 25mV of voltage drop across the MOSFET. NC: No Connection. Not internally connected.
When the load current is small, the gate is actively driven OUT: Drain Voltage Sense. OUT is the cathode of the ideal
to maintain 25mV across the MOSFET. If reverse current diode and the common output when multiple LTC4357s
develops more than –25mV of voltage drop across the are configured as an ideal diode-OR. It connects to the
MOSFET, a fast pull-down circuit quickly connects the drain of the N-channel MOSFET. The voltage sensed at
GATE pin to the IN pin, turning off the MOSFET. this pin is used to control the source-drain voltage across
GND: Device Ground. the MOSFET.
IN: Input Voltage and GATE Fast Pull-Down Return. IN is VDD: Positive Supply Input. The LTC4357 is powered from
the anode of the ideal diode and connects to the source the VDD pin. Connect this pin to OUT either directly or
of the N-channel MOSFET. The voltage sensed at this pin through an RC hold-up circuit.

block diagram

IN GATE OUT
17V

CHARGE PUMP

VDD

FPD GATE
COMP AMP
+ –
– +
IN

25mV + + 25mV
– –

GND

4357 BD

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LTC4357
Operation
High availability systems often employ parallel-connected voltage is detected at the IN and OUT pins, and the
power supplies or battery feeds to achieve redundancy LTC4357 drives the GATE pin to servo the forward drop
and enhance system reliability. ORing diodes have been to 25mV. If the load current causes more than 25mV of
a popular means of connecting these supplies at the point voltage drop when the MOSFET gate is driven fully on,
of load. The disadvantage of this approach is the forward the forward voltage is equal to RDS(ON) • ILOAD.
voltage drop and resulting efficiency loss. This drop reduces If the load current is reduced causing the forward drop
the available supply voltage and dissipates significant to fall below 25mV, the MOSFET gate is driven lower by
power. Using an N-channel MOSFET to replace a Schottky a weak pull-down in an attempt to maintain the drop at
diode reduces the power dissipation and eliminates the 25mV. If the load current reverses and the voltage across
need for costly heat sinks or large thermal layouts in high IN to OUT is more negative than –25mV the LTC4357
power applications. responds by pulling the MOSFET gate low with a strong
The LTC4357 controls an external N-channel MOSFET to pull-down.
form an ideal diode. The voltage across the source and In the event of a power supply failure, such as if the output
drain is monitored by the IN and OUT pins, and the GATE of a fully loaded supply is suddenly shorted to ground,
pin drives the MOSFET to control its operation. In effect reverse current temporarily flows through the MOSFET that
the MOSFET source and drain serve as the anode and is on. This current is sourced from any load capacitance
cathode of an ideal diode. and from the other supplies. The LTC4357 quickly responds
At power-up, the load current initially flows through the to this condition turning off the MOSFET in about 500ns,
body diode of the MOSFET. The resulting high forward thus minimizing the disturbance to the output bus.

Applications Information
MOSFET Selection ORing Two-Supply Outputs
The LTC4357 drives an N-channel MOSFET to conduct Where LTC4357s are used to combine the outputs of two
the load current. The important features of the MOSFET power supplies, the supply with the highest output voltage
are on-resistance, RDS(ON), the maximum drain-source sources most or all of the load current. If this supply’s
voltage, VDSS, and the gate threshold voltage. output is quickly shorted to ground while delivering load
current, the flow of current temporarily reverses and
Gate drive is compatible with 4.5V logic-level MOSFETs
flows backwards through the LTC4357’s MOSFET. When
in low voltage applications (VDD = 9V to 20V). At higher
the reverse current produces a voltage drop across the
voltages (VDD = 20V to 80V) standard 10V threshold MOS-
MOSFET of more than –25mV, the LTC4357’s fast pull-down
FETs may be used. An internal clamp limits the gate drive
activates and quickly turns off the MOSFET.
to 15V between the GATE and IN pins. An external Zener
clamp may be added between GATE and IN for MOSFETs If the other, initially lower, supply was not delivering load
with a VGS(MAX) of less than 15V. current at the time of the fault, the output falls until the
body diode of its ORing MOSFET conducts. Meanwhile,
The maximum allowable drain-source voltage, BVDSS,
the LTC4357 charges its MOSFET gate with 20µA until the
must be higher than the power supply voltage. If an input
forward drop is reduced to 25mV. If instead this supply was
is connected to GND, the full supply voltage will appear
delivering load current at the time of the fault, its associ-
across the MOSFET.
ated ORing MOSFET was already driven at least partially
on, and the LTC4357 will simply drive the MOSFET gate
harder in an effort to maintain a drop of 25mV.
4357fd


 LTC4357
Applications Information
Load Sharing Input Short-Circuit Faults
The application in Figure 1 combines the outputs of multiple, The dynamic behavior of an active, ideal diode entering
redundant supplies using a simple technique known as reverse bias is most accurately characterized by a delay
droop sharing. Load current is first taken from the highest followed by a period of reverse recovery. During the delay
output, with the low outputs contributing as the output phase some reverse current is built up, limited by parasitic
voltage falls under increased loading. The 25mV regulation resistances and inductances. During the reverse recovery
technique ensures smooth load sharing between outputs phase, energy stored in the parasitic inductances is trans-
without oscillation. The degree of sharing is a function of ferred to other elements in the circuit. Current slew rates
RDS(ON), the output impedance of the supplies and their during reverse recovery may reach 100A/µs or higher.
initial output voltages. High slew rates coupled with parasitic inductances in se-
ries with the input and output paths may cause potentially
M1
FDB3632 destructive transients to appear at the IN and OUT pins
VINA 48V BUS
48V of the LTC4357 during reverse recovery. A zero imped-
PSA ance short-circuit directly across the input of the circuit
RTNA
IN GATE OUT
is especially troublesome because it permits the highest
LTC4357 VDD possible reverse current to build up during the delay phase.
When the MOSFET finally commutates the reverse current
GND
the LTC4357 IN pin experiences a negative voltage spike,
while the OUT pin spikes in the positive direction.
M2

VINB
FDB3632 To prevent damage to the LTC4357 under conditions of
48V input short-circuit, protect the IN pin and OUT pin as
PSB shown in Figure 2. The IN pin is protected by clamping
IN GATE OUT
RTNB to the GND pin in the negative direction. Protect the OUT
LTC4357 VDD pin with a clamp, such as with a TVS or TransZorb, or with
GND
a local bypass capacitor of at least 10µF. In low voltage
applications the MOSFET's drain-source breakdown may
be sufficient to protect the OUT pin, provided BVDSS +
M3
FDB3632
VIN < 100V.
VINC
48V Parasitic inductance between the load bypass and the
PSC LTC4357 allows a zero impedance input short to collapse
IN GATE OUT
RTNC the voltage at the VDD pin, which increases the total turn-off
LTC4357 VDD time (tOFF). For applications up to 30V, bypass the VDD pin
GND
with 39µF; above 30V use at least 100µF. If VDD is powered
4357 F01 from the output side, one capacitor serves to guard against
VDD collapse and also protect OUT from voltage spikes.
Figure 1. Droop Sharing Redundant Supplies
If the OUT pin is protected by a diode clamp or if VDD is
powered from the input side, decouple the VDD pin with a
separate 100Ω, 100nF filter (see Figure 3). In applications
above 10A increase the filter capacitor to 1µF.

4357fd


LTC4357
Applications Information
INPUT PARASITIC REVERSE RECOVERY CURRENT OUTPUT PARASITIC
INDUCTANCE INDUCTANCE
VIN
+ – M1 + – VOUT

DIN IN GATE OUT

INPUT OR DCLAMP
SBR1U- COUT
SHORT SMAT70A CLOAD
150SA LTC4357 VDD 10µF

GND
4357 F02

Figure 2. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pin.
The Polarity of Step Recovery Spikes is Shown Across Parasitic Inductances

OUTPUT PARASITIC
M1 INDUCTANCE
VIN VOUT

R1
IN GATE OUT 100Ω
INPUT
SHORT OR COUT CLOAD
LTC4357 VDD

C1
GND 100nF
4357 F03

Figure 3. Protecting Against Collapse of VDD During Reverse Recovery

Design Example M1
VIN1 Si4874DY VOUT
The following design example demonstrates the calcula- 12V TO LOAD
tions involved for selecting components in a 12V system R1
with 10A maximum load current (see Figure 4). IN GATE OUT 100Ω

First, calculate the RDS(ON) of the MOSFET to achieve the de- LTC4357 VDD
sired forward drop at full load. Assuming VDROP = 0.1V, C1
GND 0.1µF
VDROP 0.1V
RDS(ON) ≤ =
I LOAD 10A M2
VIN2 Si4874DY
RDS(ON) ≤ 10mΩ 12V

The Si4874DY offers a good solution, in an S8 package IN GATE OUT

R1
100Ω
with RDS(ON) = 10mΩ(max) and BVDSS of 30V.
LTC4357 VDD
The maximum power dissipation in the MOSFET is: C1
GND 0.1µF
P = ILOAD2 • RDS(ON) = (10A)2 • 10mW = 1W 4357 F04

With less than 39µF of local bypass, the recommended RC

values of 100W and 0.1µF were used in Figure 4. Figure 4. 12V, 10A Diode-OR
Since BVDSS + VIN is much less than 100V, output clamp-
ing is unnecessary.
4357fd


 LTC4357
Applications Information
Layout Considerations For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
Connect the IN and OUT pins as close as possible to the
guidelines to determine if this is an issue. To increase the
MOSFET’s source and drain pins. Keep the traces to the
pin spacing between high voltage and ground pins, leave
MOSFET wide and short to minimize resistive losses. See
the exposed pad connection open. Use no-clean solder
Figure 5.
to minimize PCB contamination.

1 S D 8 1 S D 8
VIN VOUT VIN VOUT
2 S D 7 2 S D 7
MOSFET
3 S D 6 3 S D 6
4 G D 5 4 G D 5

IN
IN OUT
GATE OUT

1
3
LTC4357
GATE

7
4357 F05

6
Figure 5. Layout Considerations

4357fd


LTC4357
Typical Applications
Solar Panel Charging a Battery
M1
FDB3632

R1
100Ω IN GATE OUT
100W 14V +
SOLAR SHUNT 12V LOAD
PANEL REGULATOR VDD LTC4357 BATTERY

C1
0.1µF GND

4357 TA02

–12V Reverse Input Protection –48V Reverse Input Protection

M1 M1
Si4874DY VOUT VIN FDB3632 VOUT
VIN
12V 48V 48V
12V
10A 10A
CLOAD CLOAD

IN GATE OUT IN GATE OUT

LTC4357 VDD LTC4357 VDD

DCLAMP
GND GND SMAT70A
D1 4357 TA03
D1
MMBD1205 MMBD1205 4357 TA04

Low Current Shutdown

M1
VIN FDS3672
48V VOUT
5A
10M DCLAMP
SMAT70A
R1
100Ω IN GATE OUT

VDD
LTC4357
C1
0.1µF GND
4357 TA05

G1
ON OFF BSS123

4357fd

10
 LTC4357
Package Description
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)

2.00 p0.10 R = 0.115 0.40 p 0.10

(2 SIDES) TYP
R = 0.05 4 6
0.70 p0.05 TYP

1.65 p0.05 3.00 p0.10 1.65 p 0.10

3.55 p0.05
(2 SIDES) (2 SIDES) (2 SIDES)
2.15 p0.05
PACKAGE PIN 1 BAR PIN 1 NOTCH
OUTLINE TOP MARK R0.20 OR 0.25
(SEE NOTE 6) s 45o CHAMFER
(DCB6) DFN 0405
3 1
0.25 p 0.05 0.25 p 0.05
0.50 BSC 0.200 REF 0.75 p0.05 0.50 BSC
1.35 p0.05 1.35 p0.10
(2 SIDES) (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

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11
LTC4357
Package Description
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)

3.00 p 0.102
(.118 p .004) 0.52
(NOTE 3) 8 7 6 5 (.0205)
REF

3.00 p 0.102
0.889 p 0.127 4.90 p 0.152
DETAIL “A” (.118 p .004)
(.035 p .005) 0.254 (.193 p .006)
(NOTE 4)
(.010)
0o – 6o TYP
GAUGE PLANE
5.23 1 2 3 4
(.206) 3.20 – 3.45
(.126 – .136) 0.53 p 0.152
MIN 1.10 0.86
(.021 p .006)
(.043) (.034)
DETAIL “A” MAX REF
0.18
0.42 p 0.038 0.65
(.007)
(.0165 p .0015) (.0256)
TYP BSC SEATING
PLANE 0.22 – 0.38
RECOMMENDED SOLDER PAD LAYOUT 0.1016 p 0.0508
(.009 – .015) (.004 p .002)
NOTE: TYP 0.65 MSOP (MS8) 0307 REV F
1. DIMENSIONS IN MILLIMETER/(INCH) (.0256)
2. DRAWING NOT TO SCALE BSC
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4357fd

12
 LTC4357
Revision History (Revision history begins at Rev D)

REV DATE DESCRIPTION PAGE NUMBER

D 09/10 Revised θJA value for MS8 package in Pin Configuration section and added MP-grade to Order Information section 2
Added two new plots and revised remaining curves in Typical Performance Characteristics section 3, 4
Updated Electrical Characteristics section 4
Revised Figure 2 and Figure 4 in Applications Information section 8

4357fd

13
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4357
Typical Application
Plug-In Card Input Diode for Supply Hold-Up
BACKPLANE PLUG-IN CARD
CONNECTORS CONNECTOR 1
FDB3632 Hot Swap
48V VOUT1
CONTROLLER

IN GATE OUT
+
LTC4357 VDD CHOLDUP

GND SMAT70A

GND
FDB3632 Hot Swap
VOUT2
CONTROLLER

IN GATE OUT

+
LTC4357 VDD CHOLDUP

GND SMAT70A

GND

PLUG-IN CARD 4357 TA06

GND CONNECTOR 2

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4357fd

14 Linear Technology Corporation

LT 0910 REV D • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com  LINEAR TECHNOLOGY CORPORATION 2007