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MODULE – IV
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
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Introduction
Circuit Design for latches and Flip-flops.
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Introduction
• What is sequential circuit ? Purpose of sequential circuit.
Examples for sequential circuits.
Static circuits refer to gates that have no clock input, such as
complementary CMOS, pseudo-nMOS, or pass transistor logic.
Dynamic circuits refer to gates that have a clock input, especially
domino logic.
A sequencing element with static storage employs some sort of
feedback to retain its output value indefinitely. An element with
dynamic storage generally maintains its value as charge on a
capacitor that will leak away if not refreshed for a long period of time.
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Circuit Design of Latches and Flip-flops
• Conventional CMOS latches are built using pass
transistors or tristate buffers to pass the data while the latch is
transparent and feedback to hold the data while the latch is
opaque.
• Many latches accept reset and/or enable inputs. It is also possible
to build logic functions into the latches to reduce the sequencing
overhead.
• The True Single Phase Clocking (TSPC) technique uses a single
clock with no inversions to simplify clock distribution. The
Klass Semidynamic Flip-Flop (SDFF) is a fast flip-flop using a
domino-style input stage. Differential flip-flops are good for
certain applications.
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S.No FLIP FLOP LATCH
1 Flip-flop is a bistable device i.e it Latch is also a bistable device
has two stable states that are whose states are also represented
represented as 0 and 1. as 0 and 1.
2 It checks the inputs but changes the It checks the inputs continuously
output only at times defined by the and responds to the changes in
clock signal or any other control inputs immediately
signal
3 It is a edge triggered device. It is a level triggered device.
4 Gates like NOR, NOT, AND, NAND These are also made up of gates.
are building blocks of flip flops.
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S.No FLIP FLOP LATCH
5 They are classified into There is no such classification in
asynchronous or synchronous latches.
flipflops.
6 It forms the building blocks of many These can be used for the
sequential circuits like counters designing of sequential circuits but
are not generally preferred.
7 a, Flip-flop always have a clock Latches doesn’t have a clock signal
signal
8 Flip-flop can be build from Latches Latches can be build from gates.
9 Ex: D Flip-flop, JK Flip-flop Ex: SR Latch, D Latch
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Dynamic Logic Circuits
• Introduction
• Basic Principles of Pass Transistor Circuits.
• Synchronous Dynamic Circuit Techniques.
• Dynamic CMOS Circuit Techniques.
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GLOBAL ACADEMY OF TECHNOLOGY
What are the disadvantages of Static logic circuits?
A typical static logic gate generates its output corresponding to the applied
input voltages after a certain time delay, and it can preserve its output
level (or state) as long as the power supply is provided.
This approach, however, may require a large number of transistors to
implement a function, and may cause a considerable time delay.
In high-density, high-performance digital implementations where
reduction of circuit delay and silicon area is a major objective, dynamic
logic circuits offer several significant advantages over static logic circuits.
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Merits of dynamic logic Implementation :
• The capability of temporarily storing a state, i.e., a voltage level, at
a capacitive node allows us to implement very simple sequential
circuits with memory functions.
• Also, the use of common clock signals throughout the system enables
us to synchronize the operations of various circuit blocks. As a
result, dynamic circuit techniques lend themselves well to
synchronous logic design.
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GLOBAL ACADEMY OF TECHNOLOGY
• Dynamic logic implementation of complex functions generally
requires a smaller silicon area than does the static logic
implementation.
• The power consumption which increases with the parasitic
capacitances, the dynamic circuit implementation in a smaller
area will, in many cases, consume less power than the static
counterpart, despite its use of clock signals.
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Dynamic D-latch
• We will see that the parasitic input capacitance C. of the primary inverter stage
plays an important role in the dynamic operation of this circuit. The input pass
transistor is being driven by the external periodic clock signal, as follows:
• When the clock is high (CK = 1), the pass transistor turns on. The capacitor C, is either
charged up, or charged down through the pass transistor MP, depending on the input
(D) voltage level. The output (Q) assumes the same logic level as the input.
• When the clock is low (CK = 0), the pass transistor MP turns off, and the capacitor C
is isolated from the input D. Since there is no current path from the intermediate node
X to either VDD or ground, the amount of charge stored in C. during the previous cycle
determines the output voltage level Q.
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GLOBAL ACADEMY OF TECHNOLOGY
Basic principles of Pass Transistor Circuits
• Basic building block for nMOS dynamic logic, which consists of
an nMOS pass transistor driving the gate of another nMOS
transistor
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GLOBAL ACADEMY OF TECHNOLOGY
Basic principles of Pass Transistor Circuits
• Logic 1 transfer : Assume that the soft node
voltage is equal to 0 initially, i.e., Vx(t = 0) = 0
V. A logic " 1" level is applied to the input
terminal, which corresponds to Vin = VOH = VDD.
Now, the clock signal at the gate of the pass
transistor goes from 0 to VDD at t = 0. It can be
seen that the pass transistor MP starts to
conduct as soon as the clock signal becomes
active and that MP will operate in saturation
throughout this cycle since VDS = VGS.
Consequently, VD > VGS – VT
Equivalent circuit for the logic " 1 " transfer
event
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GLOBAL ACADEMY OF TECHNOLOGY
Basic principles of Pass Transistor Circuits
Variation of V as a function of time during logic "I" transfer
Node voltages in a pass-transistor chain during the logic " 1 " transfer
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Basic principles of Pass Transistor Circuits
Node voltages during the logic " 1 " transfer, when each pass transistor is driving
another pass transistor.
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Basic principles of Pass Transistor Circuits
Logic 0 transfer:
Assume that the soft-node voltage V is equal to a logic " 1 " level
initially, i.e., Vx(t = 0) = Vm = (VDD- VTn). A logic "0" level is
applied to the input terminal, which corresponds to Vin = 0 V. Now,
V
the clock signal at the gate of the pass transistor goes from 0 to DD
at t = 0. The pass transistor MP starts to conduct as soon as the clock
signal becomes active, and the direction of drain current flow
through MP will be opposite to that during the charge-up (logic " 1
" transfer) event. The intermediate node X will now correspond to
the drain terminal of MP and that the input node will correspond to
its source terminal. With VGS = VDD and VDS = Vmax, it can be seen
that the pass transistor operates in the linear region throughout this
cycle, since VDS < VGS - VTn.
Equivalent circuit for the logic "0" transfer event.
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GLOBAL ACADEMY OF TECHNOLOGY
Basic principles of Pass Transistor Circuits
Variation of V as a function of time during logic “0" transfer
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Charge leakage
• Dynamic Logic Circuits during the active clock phase and that now both
the input voltage Vn and the clock are equal to 0 V. The charge stored
in Cx will gradually leak away, primarily due to the leakage currents
associated with the pass transistor.
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GLOBAL ACADEMY OF TECHNOLOGY
Equivalent circuit for analyzing charge leakage process
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Synchronous dynamic circuit techniques
• Multi-stage pass transistor logic driven by two non overlapping clocks
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Consider the generalized view of a multi-stage synchronous circuit shown
in Figure.
The circuit consists of cascaded combinational logic stages, which are
interconnected through nMOS pass transistors. All inputs of each
combinational logic block are driven by a single clock signal.
Individual input capacitances are not shown in this figure for simplicity,
but the operation of the circuit obviously depends on temporary charge
storage in the parasitic input capacitances.
To drive the pass transistors in this system, two nonoverlapping clock
signals, Ф1 and Ф2, are used. The nonoverlapping property of the two clock
signals guarantees that at any given time point, only one of the two clock
signals can be active, as illustrated in Figure.
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Nonoverlapping clock signals used for two-phase synchronous
operation.
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GLOBAL ACADEMY OF TECHNOLOGY
When clock Ф1, is active, the input levels of Stage 1 (and also of Stage 3)
are applied through the pass transistors, while the input capacitances of
Stage 2 retain their previously set logic levels.
During the next phase, when clock Ф2 is active, the input levels of Stage 2
will be applied through the pass transistors, while the input capacitances of
Stage 1 and Stage 3 retain their logic levels.
This allows us to incorporate the simple dynamic memory function at each
stage input, and at the same time, to facilitate synchronous operation by
controlling the signal flow in the circuit using the two periodic clock
signals.
This signal timing scheme is also called two-phase clocking and is one of
the most widely used timing strategies.
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GLOBAL ACADEMY OF TECHNOLOGY
By introducing the two-phase clocking scheme, we have not made any
specific assumptions about the internal structure of the combinational logic
stages.
It will be seen that depletion-load nMOS, enhancement-load nMOS, or
CMOS logic circuits can be used for implementing the combinational logic.
The Figure shows a depletion-load dynamic shift register circuit, in which
the input data are inverted once and transferred or shifted into the next
stage during each clock phase.
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Three stages of a depletion-load nMOS dynamic shift register
circuit driven with two-phase clocking.
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Operation of Shift register
• During the active phase of Ф1 the input voltage level V is transferred into
the input capacitance Cin1.
• Thus, the valid output voltage level of the first stage is determined as the
inverse of the current input during this cycle.
• When Ф2 becomes active during the next phase, the output voltage
level of the first stage is transferred into the second stage input
capacitance Cin2, and the valid output voltage level of the second stage is
determined.
• During the active Ф2 phase, the first-stage input capacitance continues
to retain its previous level via charge storage.
• When Ф1 becomes active again, the original data bit written into the
register during the previous cycle is transferred into the third stage, and the
first stage can now accept the next data bit.
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Depletion-load nMOS implementation of synchronous complex
logic.
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Enhancement-load dynamic shift register (ratioed logic).
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Ratioed logic is a type of digital logic circuit design where the pull-up
device in a CMOS gate is replaced with a simple resistive or other load
device, rather than the usual complementary PMOS pull-up network.
This approach reduces the number of transistors used in a gate, but it
comes with trade-offs like reduced noise margins and increased static
power dissipation.
The name "ratioed" stems from the fact that the voltage swing and gate
functionality are influenced by the ratio of transistor sizes, especially in
pseudo-NMOS logic.
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
A dynamic shift register implemented with a technique named“ratioed
dynamic logic”.
Ф1and Ф2 are non-overlapping clocks.
When Ф1 is high, Cin1 charges to Vdd – Vt if Vin is high or to GND if Vin is
low.
When Ф1 drops and Ф2 comes up, the input data is trapped on Cin1 and
yields a logic output on Cout1 which is transferred to Cin2.
When Ф2 drops and Ф1 comes up again, the logic output on Cout1 is
trapped on Cin2, which yields a logic output on Cout2, which is
transferred to Cin3, etc.
To avoid losing too much voltage on the logic high level, Coutn >> Cinn+1 is
desired.
Each inverter must be ratioed to achieve a desired VOL (e.g. when Ф2 is
high on 1st inv).
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General circuit structure of ratioed synchronous
dynamic logic
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Enhancement-load dynamic shift register (ratioless logic).
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A Dynamic shift register is a “ratioless dynamic logic” circuit.
When Ф2 is high transferring data to stage 2, Ф1 has already
turned off the stage 1 load transistor, allowing a VOL = 0 to be
obtained.
Without a ratio condition between load and driver transistors
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General circuit structure of ratioless synchronous dynamic
logic
22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
CMOS Transmission Gate Logic
• Basic two-phase synchronous logic circuit principle, in which
individual logic blocks are cascaded via clock-controlled switches,
can easily be adopted to CMOS structures.
• Static CMOS gates are used for implementing the logic blocks, and
CMOS transmission gates are used for transferring the output levels
of one stage to the inputs of the next stage.
• Each transmission gate is actually controlled by the clock signal
and its complement. As a result, two-phase clocking in CMOS
transmission gate logic requires a total of four clock signals are
generated and routed throughout the circuit.
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GLOBAL ACADEMY OF TECHNOLOGY
CMOS Transmission Gate Logic
• The operation of CMOS dynamic logic relies on
charge storage in the parasitic input capacitances during
the inactive clock cycles.
• To illustrate the basic operation principles, the
fundamental building block of a dynamic CMOS
transmission gate shift register is shown in figure
9.24.
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GLOBAL ACADEMY OF TECHNOLOGY
To illustrate the basic operation principles, the fundamental building block
of a dynamic CMOS transmission gate shift register is shown in Figure. It
consists of a CMOS inverter, which is driven by a CMOS transmission gate.
During the active clock phase (CK =1), the input voltage Vin is transferred
onto the parasitic input capacitance C, via the transmission gate. Note
that the low on-resistance of the CMOS transmission gate usually
results in a smaller transfer time compared to those for nMOS-only
switches.
Also, there is no threshold voltage drop across the CMOS transmission
gate. When the clock signal becomes inactive, the CMOS transmission gate
turns off and the voltage level across Cx, can be preserved until the next
cycle.
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GLOBAL ACADEMY OF TECHNOLOGY
Figure 9.25 shows a single-phase CMOS shift register, which is built by
cascading identical units as in Fig. 9.24 and by driving each stage
alternately with the clock signal and its complement.
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GLOBAL ACADEMY OF TECHNOLOGY
Ideally, the transmission gates of the odd-numbered stages would
conduct during the active clock phase (when CK = 1), while the
transmission gates of the even-numbered stages are off, so that the
cascaded inverter stages in the chain are alternately isolated.
This would ensure that inputs are permitted in alternating half cycles.
In practice, however, the clock signal and its complement do not
constitute a truly nonoverlapping signal pair, since the clock voltage
waveform has finite rise and fall times. Also, the clock skew between CK
and CK may be unavoidable because one of the signals is generated by
inverting the other.
Therefore, true two-phase clocking with two nonoverlapping clock
signals (Ф1 and Ф2) and their complements is usually preferred over
single-phase clocking in dynamic CMOS transmission gate logic.
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Dynamic CMOS logic (Precharge-Evaluate Logic)
Dynamic CMOS circuit technique which allows us to significantly
reduce the number of transistors used to implement any logic
function.
The circuit operation is based on first precharging the output node
capacitance and subsequently, evaluating the output level according
to the applied inputs.
Both of these operations are scheduled by a single clock
signal, which drives one nMOS and one pMOS transistor in each
dynamic stage.
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GLOBAL ACADEMY OF TECHNOLOGY
Dynamic CMOS logic (Pre-charge-Evaluate Logic)
• Dynamic CMOS logic gate implementing a
complex Boolean function.
Fig. 9.26
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When the clock signal is low (precharge phase), the pMOS precharge
transistor MP is conducting, while the complementary nMOS transistor Me is
off. The parasitic output capacitance of the circuit is charged up through the
conducting pMOS transistor to a logic-high level of VOID = VDD. The input
voltages are also applied during this phase, but they have no influence yet
upon the output level since Me is turned off.
When the clock signal becomes high (evaluate phase), the precharge transistor Mp
turns off and Me turns on. The output node voltage may now remain at the logic-
high level or drop to a logic low, depending on the input voltage levels. If the input
signals create a conducting path between the output node and the ground, the
output capacitance will discharge toward VOL = 0 V.
The final discharged output level depends on the time span of the evaluation
phase. Otherwise, Vout remains at VDD.
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Disadvantage of same clock signal
Dynamic CMOS logic stages driven by the same clock signal cannot
be cascaded directly. This severe limitation seems to undermine all
the other advantages of dynamic CMOS logic, such as low power
dissipation, large noise margins, and low transistor count.
Alternative clocking schemes and circuit structures must be
developed to overcome this problem. In fact, the search for viable
circuit alternatives has spawned a large array of high-performance
dynamic CMOS circuit Techniques.
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GLOBAL ACADEMY OF TECHNOLOGY
High Performance Dynamic CMOS Circuits
The circuits presented here are variants of the basic dynamic CMOS logic gate
structure. We will see that they are designed to take full advantage of the
obvious benefits of dynamic operation and at the same time, to allow
unrestricted cascading of multiple stages. The ultimate goal is to achieve
reliable, high-speed, compact circuits using the least complicated clocking
scheme possible.
Domino CMOS Logic
Consider the generalized circuit diagram of a domino CMOS logic gate shown in
Fig. 9.28. A dynamic CMOS logic stage, such as the one shown in Fig. 9.26, is
cascaded with a static CMOS inverter stage. The addition of the inverter allows
us to operate a number of such structures in cascade, as explained in the
following.
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Domino CMOS logic gate: Fig. 9.28
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Figure 9.29. Cascaded domino CMOS logic gates
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During the precharge phase (when CK = 0), the output node of the
dynamic CMOS stage is precharged to a high logic level, and the
output of the CMOS inverter (buffer) becomes low.
When the clock signal rises at the beginning of the evaluation phase,
there are two possibilities: The output node of the dynamic CMOS
stage is either discharged to a low level through the nMOS circuitry
(1 to 0 transition), or it remains high.
Consequently, the inverter output voltage can also make at most one
transition during the evaluation phase, from 0 to 1. Regardless of the
input voltages applied to the dynamic CMOS stage, it is not possible
for the buffer output to make a 1 to 0 transition during the
evaluation phase.
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GLOBAL ACADEMY OF TECHNOLOGY
Remember that the problem in cascading conventional dynamic CMOS
stages occurs when one or more inputs of a stage make a 1 to 0 transition
during the evaluation phase.
On the other hand, if we build a system by cascading domino CMOS logic
gates as shown in Fig. 9.29, all input transistors in subsequent logic blocks
will be turned off during the precharge phase, since all buffer outputs are
equal to 0.
During the evaluation phase, each buffer output can make at most one
transition (from 0 to 1), and thus each input of all subsequent logic stages
can also make at most one (0 to 1) transition.
In a cascade structure consisting of several such stages, the evaluation of each
stage ripples the next stage evaluation, similar to a chain of dominos falling one
after the other. The structure is hence called domino CMOS logic.
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NORA CMOS Logic (NP-Domino Logic)
In domino CMOS logic gates, all logic operations are performed by the
nMOS transistors acting as pull-down networks, while the role of pMOS
transistors is limited to precharging the dynamic nodes.
As an alternative and a complement to nMOS-based domino CMOS
logic, we can construct dynamic logic stages using pMOS transistors as
well
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22EEE63C VLSI DESIGN Dr.KHR Department of EEE
GLOBAL ACADEMY OF TECHNOLOGY
Note that the precharge-and-evaluate timing of nMOS logic stages is
accomplished by the clock signal Ф, whereas the pMOS logic stages are
controlled by the inverted clock signal, Ф.
The operation of the NORA CMOS circuit is as follows:
When the clock signal is low, the output nodes of nMOS logic blocks are
precharged to VDD through the pMOS precharge transistors, whereas the
output nodes of pMOS logic blocks are pre-discharged to 0 V through the
nMOS discharge transistors, driven by Ф .
When the clock signal makes a low-to-high transition (note that the
inverted clock signal Ф makes a high-to-low transition simultaneously), all
cascaded nMOS and pMOS logic stages evaluate one after the other, much
like the domino CMOS examined earlier.
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