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Digital Electronic Circuits

Assignment- Week 2
TYPE OF QUESTION: MCQ/MSQ
Number of questions: 15 Total mark: 15 X 1 = 15
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QUESTION: 1
Consider the following truth tables for addition (‘+’), multiplication (‘x’) and division(‘/’)
operation,

A B A+B A B AxB A B A/B

0 0 0 0 0 0 0 0 0

0 1 1 0 1 0
0 1 0

1 0 1 1 0 X
1 0 0
(Don’t care)
1 1 1 1 1 1
1 1 1

Find the Boolean logic (using k-map minimization) for the expression:
F = (A+(BxC))/D

a) F = AB+BC
b) F = A+B+C
c) F = AB+C
d) F = A+BC
Correct Answer: d)
Detailed Solution:
Truth table for F = (A+(BxC))/D is,
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A B C D BxC A+(BxC) (A+(BxC))/D

0 0 0 0 0 0 0

0 0 0 1 0 0 0

0 0 1 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 0 1 0 0 0

0 1 1 0 1 1 X

0 1 1 1 1 1 1

1 0 0 0 0 1 X

1 0 0 1 0 1 1

1 0 1 0 0 1 X

1 0 1 1 0 1 1

1 1 0 0 0 1 X

1 1 0 1 0 1 1

1 1 1 0 1 1 X

1 1 1 1 1 1 1

K-map minimization of min-terms devised from Truth table.

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C’D’ C’D CD CD’

A’B’

A’B 1 X

AB X 1 1 X

AB’ X 1 1 X

Hence, final answer is, F = A + BC.

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QUESTION 2:
If A = A0A1 and B = B0B1 are 2–bit binary numbers. The Boolean function Y(A0, A1, B0, B1) that
satisfies the condition “If A ≥ B, then Y = 1”, in its minimized form is________.

a) Y = B0B1 +A0A1+A1B0’+A0B0’+A0B1’
b) Y = A0A1+B0’+A0B1’
c) Y = B0’B1’ +A0A1+A1B0’+A0B0’+A0B1’
d) Y = A0A1+B0’+A0’B1’

Correct Answer: c)
Detailed Solution:
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QUESTION 3:
A logic circuit implements a Boolean logic given by,
F = X’Y+XY’Z’.
After implementation of the circuit, it is found that input combination X=Z=1 can never occur.
Taking this into account, a simplified expression for F(X, Y, Z) is?
a) X⨁Y
b) X.Y
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c) (X⨁Y)’
d) X+Y
Correct Answer: a
Detailed Solution:

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QUESTION 4:
Using K-map assign variables to the inputs a, b, c and d of the AND-XOR circuit in the given
figure such that the output F(W,X,Y,Z) = Σm(2, 3, 4, 5). (Note: Output gate is a 2-input XOR
gate).
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a. a = W ;b = X ;c = Y ;d = Z
b. a = Z ;b = Y ;c = X ;d = W
c. a = X’ ;b = W ;c = X’ ;d = Z
d. a = Y ;b = W’ ;c = W’ ;d = X
Correct Answer: d
Detailed Question:
The K-map for the given expression is drawn below:

Y’Z’ Y’Z YZ YZ’

W’X’ 1 1

W’X 1 1

WX

WX’

Hence, the given expression is, F = W’XY’ + W’X’Y. _____eq. (1)

Let the inputs to the circuit be, a, b, c and d.
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This implies, F = ab ⨁ cd.

F = abc’ + abd’ + a’cd + b’cd. _____eq.(2)
As eq(1) and (2) are same and eq(2) has two min-terms which is possible when two AND inputs
have one input in common. Hence, setting b = c in eq(2), which gives,
F = acc’ + acd’ + a’cd + c’cd = acd’ + a’cd _______eq.(3)
Comparing eq (1) and eq (3), we get,
a = Y; c = W’; d = X
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QUESTION 5:
Suppose you have a controller with two buttons (A and B). The controller also has two input
probes (X and Y). Depending upon how the controlling buttons are set ON or OFF, the following
basic operations take place with the inputs X and Y. Let the output of the circuit be Z.

A B Operation (Output Z)

0 0 X NOR Y

0 1 X XOR Y

1 0 X NAND Y

1 1 X XNOR Y

The equivalent logic expression of output Z(A,B,X,Y) is:

a. Z = A’X’Y’ + AB’X’ + AB’Y’ + AX’Y’
b. Z = A’BXY’ + A’BX’Y + ABXY+ B’X’Y’ + AX’Y’ + AB’Y’ + AB’X’
c. Z = A’BXY’ + A’BX’Y + ABXY + A’B’X’Y’+ AX’Y’ + AB’Y’ + AB’X’
d. Z = A’BXY’ + A’BX’Y + ABXY + AB’XY’ + AX’Y’ + A’X’Y’ + AB’X’
Correct Solution: b
Detailed Solution:
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The truth table for the given logic functions is:

A B Operation X Y Z

0 0 NOR 0 0 1

0 0 NOR 0 1 0

0 0 NOR 1 0 0

0 0 NOR 1 1 0

0 1 XOR 0 0 0

0 1 XOR 0 1 1

0 1 XOR 1 0 1

0 1 XOR 1 1 0

1 0 NAND 0 0 1

1 0 NAND 0 1 1

1 0 NAND 1 0 1

1 0 NAND 1 1 0

1 1 XNOR 0 0 1

1 1 XNOR 0 1 0

1 1 XNOR 1 0 0

1 1 XNOR 1 1 1

K-map formulation of the given problem statement is:

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X’Y’ X’Y XY XY’

A’B’ 1

A’B 1 1

AB 1 1

AB’ 1 1 1

Z =A’BX’Y + ABXY + A’BXY’ + B’X’Y’ + AX’Y’ + AB’Y’ + AB’X’.

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QUESTION 6:
In the given below figure, the output Y is Y = A+B+C’+D. For the given output, the gates G1 and
G2 must be,

a. NAND gate and NOR gate

b. AND gate and NAND gate
c. NAND gate and OR gate
d. AND gate and NOR gate
Correct Answer: b
Detailed Solution:
Y = A + B +C’+D = ((A+B+C’+D)’)’ = ((A+B)’. (C’+D)’)’ = ((A’. B’). (C. D’))’
Hence, we need an AND gate for G1 (to obtain (A’. B’)) and NAND gate in G2 (to obtain
complete ((A’. B’). (C. D’)’)).
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QUESTION 7:
In a digital circuit, N numbers of XNOR gates are connected to each other as shown below. The
output of the circuit will be _______(0 or 1) when N is odd and with the restriction that input
combination can contain odd number of 1’s.

Correct Answer: 0 (Logic LOW)

Detailed Solution:
Given N is odd, hence consider N=3, i.e.,

The output of the given circuit is equivalent to Y = A0 ⊙A1 ⊙A2⊙A3.

Hence, when the no. of 1s in the inputs are odd, the output would be 0. This would be true for
any odd value of N following the given configuration of the circuit.
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QUESTION 8:
The output of the given circuit diagram is:

a. Output = A’B + B’C + ABC’

b. Output = AB’ + B’C + ABC’
c. Output = A’B + B’C + ABC
d. Output = AB’ + BC’ + ABC’

Correct Answer: d
Detailed Solution:

ABC’

BC’

AB’

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QUESTION 9:
Fill in the blank:
With 5 logic variables there are _________ total number of possible logic functions.
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Correct Answer: 4294967296

Detailed Solution:
With n variables, there are 2^(2n) possible logic functions.
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QUESTION 10:
Determine the output waveform of the circuit at Y. No inputs are given initially. Also, the logic
remains 0 everywhere in the initial state of the circuit (t = 0). The input is kept and maintained
at logic 0 indefinitely, i.e., for t > 0. Consider delay through every gate to be 2ms.

a.

b.

c.

d.

Correct Answer: d

Detailed Solution:

The circuit in figure acts as an oscillator. As potential everywhere is 0 initially, output of both
gates becomes 1 after 2ms.

C
B
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A B C D (Y)

0 0 0 0

0 1 1 1

0 0 0 0

0 1 1 1

0 0 0 0

Hence, the output Y switches between 0 and 1 continuously.

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QUESTION 11:
Find the dual of the following expression using Shannon’s expansion theorem:
F(A, B, C,...,N) = C’.F(A,B,0,D ..., N) + C.F(A,B,1,D ..., N)

a. [C’ + F(A,B,1,D..., N)].[C + F(A,B,0,D ..., N)]

b. [C’ + F(A,B, 0,D ..., N)].[C + F(A,B, 0,D ..., N)]
c. [C’ + F(A,B,0, D, ..., N)].[C + F(A,B,1, D, ..., N)]
d. [C’ + F(A,B,1, D, ..., N)].[C + F(A,B,1, D, ..., N)]

Correct Answer: a

Detailed Solution:
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(Refer Boolean Function to Truth Table and Implementation Issues, lecture 8, slide no. 6 NPTEL
online certification courses)

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QUESTION 12:
Match the following Boolean expressions: (Representation of NAND: ↑, NOR :↓)

1. Absorption i)(A.B).C = A.(B.C)

2. Adsorption ii) A.B + A.B’ = A

3. Consensus iii) A + A’.B = A + B

4. Uniting iv) A↓(B↑C) = (A’↑B)↓(A’↑C)

5. Associative v)A.B + A’.B + B.C = A.B + A’.B

6. Distributive vi) (A↓B)’↓C = A↓(B↓C)’

7. Pseudo associative vii) A.(B + C) = A.B + A.C

8. Pseudo distributive viii) A + A.B = A

a. 1→viii ;2→iii;3→v ;4→ii ;5→i ;6→vii ;7→vi ;8→iv;

b. 1→viii ;2→iii ;3→v ;4→ii ;5→i ;6→vii ;7→iv ;8→vi;

c. 1→iii;2→viii ;3→ii ;4→v ;5→i ;6→vii ;7→vi ;8→iv;

d. 1→iii ;2→ii ;3→v ;4→viii ;5→vii ;6→i ;7→iv;8→vi;

Correct Answer: a

Detailed Solution:

Refer Lecture 07: Fundamentals of Boolean Algebra of NPTEL online certification course

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QUESTION 13:
Which gate among the following is generally preferred by computer hardware manufacturers?
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a. AND
b. OR
c. NAND
d. XOR

Correct Answer: c
Detailed Solution:
NAND and NOR are universal gates, i.e., any logic gate operation can be performed by using
NAND or NOR gates. Hence, they are generally preferred in computer hardware.
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QUESTION 14:
Find the self-dual function among the given options:
a. F (A, B, C) = Σ m (0, 2, 5)
b. F (A, B, C) = Σ m (0, 3, 5, 6)
c. F (A, B, C) = Σ m (2, 3, 5, 7)
d. F (A, B, C) = Σ m (1, 6, 7)
Correct Answer: b
Detailed Solution:
F (A, B, C) = Σ m (0, 3, 5, 6)

B’C’ B’C BC BC’

A’ 1 1

A 1 1

F = A’B’C’ + A’BC + AB’C + ABC’ = No mutually exclusive terms and no. min-terms are equal to
number of max-terms.

QUESTION 15:
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Correct Answer: b
Detailed Solution:

𝐹 (𝐴, 𝐵, 𝐶, 𝐷) = ∏ 𝑀 (0,1,2, 5, 6,8,10,13,14)

The k-map simplification would be,

Therefore, the correct answer is Y = (A+B+C) (B+D) (B’+C+D’) (C’+D)

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