CS 429 – Discussion 12
Week 0xC
Quiz – same rules as usual
Announcements
● Checkpoint 2 Due Tonight 11:59 PM
○ You can only use 1 slip day because of this extension (i.e. final due date is unchanged)
○ Make sure to download the repaired reference files from Ed and replace the files in your
repository.
● Checkpoint 3 Due Next Thursday
PSA Office Hours Etiquette
● The queues get long, especially near the checkpoint, as you all have
seen
● To make sure everyone has a fair chance, make sure you…
○ Write both you and your partnerʼs name in one line (even if your partner isnʼt there)
○ Write a 13 word description of your issue
○ Do NOT write your name multiple times at once (we will erase you, and if it continues we
may institute temporary OH bans – it is unfair to other students)
○ Do NOT write a question unless & until you actually have one. You shouldnʼt be on the
queue “in caseˮ you have a question
■ Weʼll remove from the queue if you donʼt have a question/need help when we get
to you
○ There needs to be some attempt at debugging prior to asking us a code question. It
takes up to 1520 minutes for us per person when you do not do this
Quiz 0x8 Review
Overview of Stages
PIPE- vs PIPE
PIPE- is not fully correct– and it’s evident in some of the test cases from week one
of SE lab.
We have to handle hazards to achieve a correct pipeline.
PIPE is our fully-functional, IaaT-semantic-compliant pipeline.
Pipelining and Hazards (Lecture Slides 11.1)
>
-
-
y
=
Dependencies
● Data Dependence
○ An instruction is dependent on the data that is being used or altered by a previous instruction
■ True dependency (read after write) - only one relevant for sequential CS429 code
=
■ Anti-dependency (write after read)
■ Output dependency (write after write) 3
● Control Dependence
○ Whether or not an instruction runs is dependent on the result of a previous instruction
■ (conditional jumps)
■ Branch mispredictions
How to Defeat Hazards
● Not all dependencies are hazards, but they have the potential to be
● Methods: Dealing with Data Dependencies
>
- ○ Stalling - Gives more time to previous instruction to complete before the next instruction with
data dependence or ret uses data
■ Inserts nops bubble
-
■ Ret instruction requires a single bubble at the fetch stage
-
>
- ○ Forwarding - Sends data from a previous instruction at later stage to the next instruction at a
previous stage
■ Preferable to stalling for data hazards because no cycle loss
● Execute or writeback output sent through a wire to the decode
Squashing
>
-
truding inses into
->
hops
forward
-
FDX M w
write in
1x3 Q O
rouch
used load,
for not
from and stores
stalling
-
used for load and store
label +
FD + nu
Il rot
>
- ret
label L
.
>
- b label I
> 13
-
O
-
-
>
-
=> &
subs
· >
-
0 - z= 1 -00--
=> >
not taken
-
-
>
-
>
bubble
-
F
bub
>
-
PC+F
=>
>
-
Misprediction Let
& hazard at the same time :
subs XO XO XO
B . NE
,
LI
, weat at
mispredichm
.
- RET B NE
.
RET B NE
.
XT B NE .
What does this mean for SE lab?
In week two of SE lab, we make the leap (more of a hop in my opinion) from PIPE-
to PIPE. This means correctly handling all pipeline hazards as they come up.
What does this mean for you?
You’ll have to…
&
- implement hazard_control.c >
-
stalling bubbling
if there's hazards
-
checking
implement forwarding.c
- as a part of this, add a call to forward_reg() in decode_instr()
-
implement funchon called forward-reg
data
dep checks
Make sure have a default case of all false for stalling
you
and
bubbling
(
=
-
-
f-bubble
-
Stall
f -
exception handling
error in decode
Stall decode (fetch
error in write back
Stall W m, t D, F
j ,
Review: Debugging
Tools & Debugging tips for SE Lab
- Verbose output from lab executables
- test-se, se, and the references all have the -v option for more details
w - SE’s v2 is VERY useful, compare your outputs to the reference
- Think “Does this change affect global state, and if it does should it?” Not all pipeline
-2
values are used by every instruction
flag - Use a text-based difference checker to make differences easier to spot
- Redirect output to a text file to avoid terminal limits for longer outputs
- For example, test-se v2
- GDB -
-
Really handy with the v2 flag, just keep in mind 2 things:
enter
- To break on a specific stage until you reach your desired cycle, make sure to stop when
net
the cycle right before has printed.
-
skip - proc.c calls your stages in reverse (by design).
a
Cycle C30
Terminal
swen
IEnte for
decode-insert
Cgdb)
agdess
in
cycle 7
Conceptual questions about SE Lab?
&A
Wurval-> final value to
update dot
register
Apro-
ADRP XO ,
L
ADRP XO
,
L &
- -
Work How
-
1) call select PC to current PC
get
2) to instr bits & addr current PC
I mem
get
3) Use itable [] to
get opcode (in upper 11 birote)
4) Fix (e g SUBS- LMD)
instr aliases for
opcode
.
.
>
5) call
predict PC +update F-PC &
sea-sec
6)If
you have ADRP instr-update houp-ral
edt
,O
ADD XO
↓ ↓
vala val -
imm
UBFM <Xd) ,
< Xn >, mr , imons
-
d
LSL imms + 1 =
immrt-
LSR
UBFM <XdD ,
<Xn) , immr
, 3
R
UBFM <XdD ,
[Xu7 ,
< shift) , 13
shift ame =
immr
ISL
UBFM <Xd) ,
<Xn >, <
-shift mod 642 , 63-shifts
↑
, rums
imms =
63-shift
<
shift) = 63-imms
a val-imm
