8086 Assembly Language Programming and Instruction Sets

CHAPTER THREE

8086 ASSEMBLY LANGUAGE PROGRAMMING AND INSTRUCTION SETS

The 8086 instruction set includes almost all the instruction sets of 8085 plus newly
added ones. The 8086 has approximately 117 different instructions with different 300
OPCODES. The 8086 instruction set contains no operand, single operand, and two
operand instructions. Except for the string operation which involves array operations, the
8086 instruction do not permit memory to memory operations.

3.1 8086 Addressing Modes

In the previous chapter, we have seen how the 8086 can generate the 20-bit physical
address with the help of the CS and IP. The addressing modes will explain and make
clear the ways that an 8086 can access data. The ways in which the processor can access
data is called ADDRESSING MODES. Addressing modes can broadly be grouped as:
• Data addressing modes
• Program memory addressing modes
• Stack memory addressing modes

3.1.1 Data Addressing Mode

The data addressing mode can further be divided into:

3.1.1.1 Immediate Register & Data Addressing Mode

1. Register Addressing Mode
This addressing mode specifies the source and destination operand. Most of the
time the sources and destinations are both contained in the registers of 8086.
Some examples of register addressing modes are:
MOV BX, CX
MOV CL, BL
Example MOV AL, BL. This instruction is a type of register addressing mode. The
data direction flow is from right to the left, which means values of the BL register
will be copied from the BL register to the AL register. The register from which a
data is copied from is called Source register while the one to be copied to is the
Destination register.

2. Immediate Addressing Mode

In this type of addressing an already provided 8 or 16-bit of data can be specified
as part of the instruction.
MOV AL, 20H in this instruction the data 20 in hexadecimal will be copied to the
destination register AL (in the lower bytes)
MOV AX, 2A12H is also an example of immediate addressing mode.

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Addressing Modes for Accessing data in memory

The Execution Unit has a direct access of the registers and the immediate data. However,
the execution unit cannot access the memory unless aided by the Bus Interface Unit
(BIU). Especially the segment registers of the BIU are used whenever the EU attempts to
read or write memory. Whenever the EU needs to access the memory, it sends out offset
values to the BIU. This offset is also known by the name Effective Address (EA). It is
important to note that the EA is the displacement of the desired memory segment from
the base segment. Like discussed before, the BIU generates the 20-bit physical address
after shifting the contents of the segment registers four bits and adding the EA to the
shifted value. The way the EU provides the EA to the BIU can be different, there are six
ways
a. Direct Addressing Mode d. Indexed Addressing Mode
b. Register Indirect Addressing Mode e. Based Indexed Addressing Mode
c. Based Addressing Mode f. String Addressing Mode

a. Direct Addressing Mode

In this mode the 16-bit effective address is taken directly from the displacement field
of the instruction. The displacement (unsigned 16-bit or sign extended 8-bit number)
is stored in the location following the instruction opcode. The value is given in a
square bracket.

Figure 1 Direct Addressing Mode

Question what does the instruction MOV CL, [2467H] means?

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b. Register Indirect Addressing Mode

Unlike the direct the EA in Register Indirect Addressing mode is specified in either a
point or an index register. The register can be the base register BX or base pointer BP
and index register can either be the Source Index (SI) register or Destination Index (DI)
register. The 20-bit physical address is computed using DS and EA.

Figure 2 Register Indirect Addressing Mode

MOV [DI], BX ; the instruction copies the 16-bit content of BX into a memory
location ; offset by the value of EA specified in DI from the current
contents in DS. ; Now, if [DS] =7205H, [DI] =0030H, and [BX] =8765H,
then after MOV ; [DI], BX content of BX (8765H) is copied to memory
locations 72080H ; and 72081H.

Explain MOV DL, [BP]

c. Base Addressing [Base-Plus-Index-Addressing]

This is similar to the register indirect addressing mode for it indirectly addresses
memory data. This addressing uses one base register [BP or BX], and one index
register [DI or SI] to indirectly address memory. The base register often holds the
beginning location of a memory array, while the index register holds the relative
position of an element in the array. Whenever BP addresses memory data, the
contents of stack segment, BP and index registers are used to generate physical
address

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Figure 3 Base addressing mode for data addressing

Locating Array Data Using Base-Plus-Index Addressing

The main use of the bas-plus-index addressing mode is to address elements in a
memory array. Suppose that the array is located in the data segment beginning from
memory location ARRAY. To access a particular element within the array we have to
load the BX register (base) with the beginning address of the array, and the DI register
(index) with the element number to be accessed.

Figure 4 Base addressing used for single dimensional array manipulation

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d. Register Relative Addressing Mode

This addressing mode is similar to the base-plus-index addressing mode. Here the
data in the segment memory are addressed by adding the displacement to the content
of a base or index register (BP, BX DI or SI). The displacement which could be 8-bit
number or 16-bit number is added to the register in the [ ].
• The displacement can be subtracted from the register: MOV AL, [DI-2]
• Displacement can be an offset address appended to the front of the [ ]. MOV
AL, OFF_ADD [DI+4]

Example: MOV AL, LAST [SI+2]; This instruction copies the content of the 20-bit
address computed from the displacement LAST, SI+2 and DS into AL.

Figure 5 Register relative addressing upon accessing normal data

Addressing Array Data with Register Relative

The following example shows how to address data element within the array with register
relative addressing.

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Figure 6 Array data addressing with Register Relative addressing mode

e. Base Relative Plus Index Addressing

The base relative plus Index addressing is similar to the base plus index addressing
mode, but it adds a displacement, besides using a base register and an index register
to generate a physical address of the memory. This addressing mode is suitable to
address data within two dimensional arrays.

Addressing data with Base Relative-Plus-Index

Figure 7 Data accessing using base relative plus index addressing

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Addressing Arrays with Base Relative-Plus-Index:

This addressing mode is usually used to address two dimensional arrays. Two
dimensional arrays are usually used to store records. To access data element from a
particular record we use base register to hold the beginning address of the array of
records, index register to point to a particular record in the array of records and
displacement to point particular element in the record.

Figure 8 Two dimensional array accessing using base relative plus index addressing

f. String Addressing Mode

This mode uses index registers. The string instruction automatically assumes SI to
point to the first byte or word of the source operand and DI to point to the first byte or
word of the destination operand. The content of SI and DI are automatically
incremented (by clearing the DF to 0 by CLD instruction) or decremented (by setting
DF to 1 by the STD instruction) to point to the next byte or word. The segment
register for the source is DS and for destination is ES.
Example
MOVS BYTE ;if [DF]=0, [DS]=3000H, [SI]=0600H, [ES]=5000H,
;[DI]=0400H, [30600]=38H, and [50400H]=45H, then
;after execution of the MOVS BYTE, [50400H]=38H,
;[SI]=0601H, and [DI]=0401H

Addressing Modes for Accessing I/O Ports (I/O Modes)

Standard I/O devices use port addressing modes. For memory mapped I/O, memory
addressing modes are used. There are two types of port addressing modes. These are
• Direct Port addressing
• Indirect Port addressing

In direct port addressing mode, the port number is an 8-bit immediate number operand.
This allows fixed access to ports numbered from 0-255.

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Example:
OUT 05H, AL ; sends the contents of AL to 8-bit port 05

IN AX, 80H ; copies 16-bit contents of port 80H

In indirect port addressing mode, the port number is taken from DX allowing 64K 8-bit
ports or 32K 16-bit ports.

Example:
IN AL, DX ; if [DX] =7890H, then this command copies 8-bit content of
; port 7890H into AL.

IN AX, DX ; Copies the 8-bit contents of ports 7890H and 7891H in to AH

; and AL respectively

Note that the 16 and 8-bit I/O transfer must take place through AX and AL respectively.

3.1.2 Program Memory Addressing Mode

Like data needs special addressing modes to identify type of various data, so does
program. Program memory addressing modes are those instructions which are used to
control the flow and execution of program. Instructions like JMP (Jump) and CALL use
special addressing modes. Program addressing modes are typically three types. These are
a. Direct Program Addressing Mode
b. Indirect Program Addressing Mode
c. Relative Program Addressing Mode

a. Direct Program Memory Addressing Mode

This type of addressing mode directly specifies the location of memory where the
program should next be transferred to. The immediate 16-bit effective address
memory location is given in the instruction along with opcode. To see how this works,
let us take the following example

Figure 9 Inter Segmental Jump Instruction

In our previous discussion of the data addressing modes, we always used the DS register
to hold the 16-bit current memory location. Similarly, here in program memory
addressing, we use the CS register to hold this same value of the next instruction to be
executed. However, in case of direct intersegment jump the address could be any memory
segment. What this instruction does is it loads the CS with the immediate 16-bit address.
For that matter, this type of jump is also called far jump.
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Like JMP instruction, CALL instruction also uses direct program addressing with
intersegment or far CALL instruction. Usually in both instructions, (JMP and CALL) the
name of the memory address, called a label is specified in the instruction instead of
address.

b. Indirect Program Memory Addressing Mode

The 8086 provides several forms of indirect program memory addressing modes for the
JUMP and CALL instructions. In this addressing mode it is possible to use any 16-bit
registers (AX, BX, CX, DX, SP, BP, DI, or SI). Any relative register ([BP], [BX], [DI], or
[SI]); and any relative register with displacement to specify the jump address. This is
illustrated as follows
Instruction Operation
Jumps to memory location addressed by BX within current
JMP BX code segment.
IPBX
Jumps to memory location addressed by the contents of
the data segment memory location addressed by BX within
JMP NEAR PTR the current code segment
[BX] IP  ([BX+1], [BX])
High Low
Byte Byte
Jumps to memory location addressed by the contents of
data segment memory location addressed by DI plus 2
JJMP NEAR PTR within the current code segment.
[DI+2] IP  ([DI+3], [DI+2])
High Low
Byte Byte
Jumps to memory location addressed by the contents of
data segment memory location addressed by ARRAY plus
JMP ARRAY[BX] BX with the current code segment.
IP  ([ARRAY+BX+1], [ARRAY+BX])
High Byte Low Byte

c. Relative Program Memory Addressing Mode

In this addressing mode, the term relative is restricted to instruction pointer (IP). For
instance, if a JMP instruction skips the next 3 bytes of memory, the address in relation
to the instruction pointer is a 3 that adds to the instruction pointer. This generates the
address of the next program instruction as shown below.

In JMP instruction, opcode takes one byte and displacement may take one or two bytes.
When displacement is one byte (8-bit), it is called short jump. When displacement is two
bytes (16-bit), it is called near jump. In both (short and near) cases only contents of IP
register are modified; contents of CS register are not modified. Such jumps are called
intrasegment jumps because jumps are within the current code segment.

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Opcod
e
20000H EB
JMP [03]
20001H 05
20002H --
20003H -- Offset
20004H --
20005H
20006H

The relative JMP and CALL instructions can have either an 8-bit or 16-bit signed
displacement that allows a forward memory reference or a reverse memory reference.

3.1.3 Stack Memory Addressing Mode

The stack portion is a read/write memory set aside by the user for the purpose of storing
information temporarily. When the information is written on the stack the instruction
PUSH is used and when reading the instruction POP is used. The stack operates on the
principle of First In Last Out (FILO) or Last In First Out (LIFO). The stack is incremented
by the help of a special memory pointer called stack pointer. During PUSH and POP
operation, stack pointer register gives the address of the memory where the information
is to be stored or to be read. The stack pointer is automatically manipulated to point to
the top of the stack. Top of a stack is a place in the stack where the current pointer is
pointing to.

Figure 10 Stack and Stack Pointer

PUSH Operations

This instruction decrements stack pointer by two and copies a word from the source to
the location where the stack points. The source must be a 16-bit (a word). The source

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can be a general purpose register, a segment register or memory. The way PUSH behaves
has been demonstrated in the following figure (PUSH AX, PUSH CX).

Figure 11 Stack behavior when PUSH operates

POP Operation

The POP instruction copies a word from the stack location pointed by the stack pointer to
the destination. The destination can be a general purpose register, a segment register, or
a memory location. After the word is copied to the specified location, the stack pointer is
automatically incremented by 2. The next figure shows the map of the stack after and
before the execution of POP DX and POP BX.

Figure 12 Stack behavior when POP operates

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CALL Operation
The call instruction is used to transfer execution to a subprogram or procedure. There
are two basic types of CALL instructions, the near and far CALL. In the near CALL, the
next procedure resides in the same memory segment as the CALL instruction. When the
8086 executes a near call, the stack pointer is decremented by two and then copies the
offset the next instruction after the CALL on the stack segment.

A far CALL is a call to a procedure which is in a different segment from that which
contains the CALL instruction. When the 8086 executes the far CALL it decrements the
stack pointer by two and copies the content of the CS register to the stack. It then
decrements the stack pointer by two again and copies the offset of the instruction after
CALL to the stack. Finally, it loads CS with the segment base of the code which contains
the procedure and IP with the offset of the instruction of the procedure in that segment.

RET Operation

You may have a question how a program will return back to its previous instruction after
finishing a procedure block after the instruction CALL in the calling program. The answer
to this is by the help of an instruction RET which exactly does the opposite task of the
CALL. If the procedure is a near procedure, (in the same code segment as in the CALL
instruction) then the return will be done by replacing the instruction pointer with a word
from the top of the stack.

If the procedure is a far procedure (in a different code segment from the CALL instruction
which calls it), then the instruction pointer will be replaced by the word at the top of the
stack. The stack pointer will then be incremented by two. The code segment register is
then replaced with a word from the new top of the stack. After the code segment word is
popped off the stack, the stack pointer is again incremented by two. These words/ word
are the offset of the next instruction after CALL. So 8086 will fetch the next instruction
after the CALL.

3.2 Instruction Sets of 8086

The instruction sets of the 8086 can be divided into eight groups. These are

• Data movement instructions • Processor Control Instructions

• Arithmetic and Logic Instructions • External Hardware Synchronization
• String Instructions Instructions
• Program Control Transfer Instruction • Interrupt Instructions
• Iteration Control Instruction
3.2.1 Data Movement Instructions
Data movement instruction can further be classified into

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• MOV instructions to transfer • String data transfer

byte or word instructions
• PUSH/POP instructions • Miscellaneous data transfer
• Load Effective Address instructions
Instructions
3.2.1.1 Move Instructions
This is a general purpose instruction to transfer byte or word from registers to register,
register to memory, or from memory to register.
Syntax of the MOV instruction is MOV Destination, Source
The MOV instruction transfers either a byte or a word from the source to the destination.
The destination can be either register or a memory location. The source can be either a
register, memory place or an immediate number. The source and destination cannot be
both memory locations in a single instruction. The size of the source must be equal to the
size of the destination.
Examples

MOV BX, 67F2H ; Load the immediate number 67F2H in the BX register
MOV CL, [375AH] ; Copy the contents of the memory location, at a displacement of 375AH
; from the data segment into the CL register
MOV [734AH], BX ; Copy the contents of the BX register to two memory locations in the
; data segment. Copy the contents of the BL register to memory location
; at displacement of 734AH and the content of the BH register into the
; memory in the data segment at the displacement 734BH
MOV DS, CX ; Copy a word from the CX register into the data segment register
MOV TOTAL [BP], ; Copy AX to two memory locations. AL into the first and AH into the
AX ; second. The EA is represented by TOTAL and contents of BP.
; Physical address=EA+SS
MOV CS: TOTAL ; same as the above immediate instruction except the physical
[BP], AX ; address=EA+CS, because the segment override prefix is CS

3.2.1.2 PUSH/POP Instruction

These instructions are used to load or receive data from the stack memory segment. The
syntaxes for these instructions are given as follows
PUSH source
The PUSH instruction decrements the stack pointer by two and copies a word from the
source to the location in the stack where the stack pointer points.
It is very important to note that whenever data is PUSHED onto stack the most significant
byte if the data goes to the memory location specified by SP-1 and the least significant byte
to the SP-2.
Example
PUSH CX ; Decrements the SP by 2 and copies CX to stack
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Figure 13 Execution of the PUSH command

After the execution of the above instruction, the SP=0032 and this is the top of the stack.
PUSHF
This instruction pushes the flag register contents onto the stack. Whenever this command
is executed the most significant byte of flag register moves into the stack segment memory
location addressed by SP-1. The least significant bytes moves into the memory location SP-
2.
POP destination
This instruction copies a word from the stack location pointed by the stack pointer to the
memory location. After the word copied the stack pointer is automatically incremented by
2. Whenever data is removed from a stack, the data addressed at SP moves into the most
significant byte of the destination register and the byte from the stack segment memory
addressed by SP+1 moves into the least significant byte of the destination register.
Example
POP CX ; Copy a word from top of stack to CX and increment
SP by 2

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POPF
Removes word from top of stack to the flag register.
Initializing the stack
Before going to use any instruction which uses stack for its operation we have to initialize
stack segment and we have to reverse the memory area required for the stack. The stack
can be initialized by including the following sequence of instructions in the program.
Method 1
ASSUME CS: CODE, DS: DATA, SS: STACK
STACK SEGMENT ; Starts stack segment
S_DATA DB 100 DUP (?) ; fixes the stack data to be 100 bytes (DB is a
;directive for byte and DUP is Generate Duplicate
STACK ENDS
Method 2
Syntax: .Stack [size]
Example: .Stack 100
The .stack is a directive which provides shortcut in definition of the stack segment. The
default segment is 1024.

3.2.1.3 Load Effective Address

This group includes the following instructions

• LEA
• LDS
• LES

LEA Instruction: Load effective address

Syntax: LEA register, source

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This instruction determines the offset of the variable or memory location named as the
source and loads this address in the specified 16-bit register. This instruction does not the
affect flag register.

Example:

LEA CX, TOTAL ; Load CX with offset of TOTAL in DS

LEA BP, SS: STACK_TOP ; Load BP with offset of STACK_TOP in SS
LEA AX, [BX][DI] ; Load AX with EA=[BX]+[DI]

LDS Instruction; Syntax: LDS Register, Immediate memory location

Meaning:- load the specified register and DS with words from memory. This instruction
copies a word from two memory locations to the specified register and copies the next two
bytes to the DS.

Example:

LDS CX, [3218H] ; Copy the content of memory location at the specified location
; (3218H and 3219H) into CL and CH and the content of the
; 321AH and 321BH into the DS register

LES Instruction:

Syntax: LES Register, Immediate Register address this instruction does operate exactly as
the LDS however loads the ES register instead of the DS.

3.2.1.4 String Data Transfer Instructions

These instructions include MOVS/MOVSB/MOVSW. These instructions copy a byte or a
word in the data segment to a location in the extra segment. The offset of the source string
in the data segment must be in the SI segment and the offset for the destination is in the
DI. For multiple blocks of string bytes, the CX register will be used as counter and iterates
until it gets to zero. After a byte or word is moved, the SI and DI will automatically be
decremented to enable the instruction get the next byte or word. If the direction flag is 0,
then the SI and DI will be incremented by one following transfer of a byte and will be
incremented by 2 following move of a word. The MOVS instruction does not affect any flag.
The following example demonstrates how four bytes in a memory is copied using the
MOVSB command.

CLD ; Clear Direction Flag to auto-increment SI and Di

MOV AX, 0000H
MOV DS, AX ; Initialize data segment register to 0
MOV ES, AX ; Initialize extra segment register to 0
MOV SI, 2000H ; Load offset of start of source string into SI
MOV DI, 2400H ; Load offset of start of destination string into DI

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MOV CX, 04H ; Load length of the string in CX as a counter

REP MOVSB ; Decrement CX and MOVSB until CX will be 0
The prefix REP tells the processor to repeat MOVSB until the register CX becomes 0. There
are more prefixes which can affect the way MOVSB or MOVSW repeat. These are,
REP/REPE/REPZ/REPNE/REPNZ Prefixes
Instruction Code Name Condition for Exit
REP REPEAT CX=0
REPE REPEAT UNTIL EQUAL CX=0 or ZF=0
REPZ Repeat until zero CX=0 or ZF=0
REPNE Repeat Until not Equal CX=0 or ZF=1
REPNZ Repeat Until not Zero CX=0 or ZF=1

LODS/LODSB/LODSW
This instruction copies a byte from a string location pointed to by SI to AL, or a word from a
string location pointed by SI into AX. LODS does not affect any flags.
STOS/STOSB/STOSW
These instructions copy a byte from AL or a word from AX to a location in the extra
segment. DI is the offset storage that is used to give the location of the memory where the
byte or word is going to be written.
3.2.1.5 Miscellaneous Data Transfer Instructions
This group contains the following instructions.

▪ XCHG
▪ LAHF
▪ SAHF
▪ XLAT
▪ IN and OUT

XCHG Instruction

Syntax: XCHG destination, source

This instruction exchanges the content of a register with the contents of another register, or
content or a register with the contents of a memory location. The instruction can’t exchange
the contents of two memory locations directly. The segment registers cannot be used in this
instruction.

Example

XCHG BX, CX ; exchange word in BX with Word in CX

XCHG AL, SUM [BX] ; exchange bytes in AL with the byte in memory
; at EA=SUM+[BX]

LAHF INSTRUCTION: Meaning---load lower bytes of flag register in AH

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This instruction copies the contents of the lower byte of 8086 flag register to AH register.

SAHF INSTRUCTION: Meaning---copy AH register content to the lower byte of the flag
register

This instruction copies the content of the AH register into the lower bytes of the flag register

XLAT Instruction: Meaning translate byte in AL

The XLAT instruction replaces a byte in AL register with a byte from a lookup table in
memory. BX register stores the offset of the starting address of the lookup table and AL
register stores the byte number from the lookup table.

AL  [BX+AL]

IN and OUT instructions

These two instructions are used to access ports of the 8086. IN is used to input data from
the port address specified byte address in IN. The instruction OUT is used to send data to a
port specified by the address in the instruction itself. There are two basic port addressing
modes related to these instructions. These are direct and indirect port addressing modes.
In direct port addressing mode the port address is readily provided in the instruction while
in indirect it is a content of the specified register that will give out the address of the port in
mind.

Example

MOV DX, 2189H ; load 16-bit address of the port in DX

OUT DX, AL ; copy the contents of AL to port 2189H
OUT DX, AX ; copy the contents of AX to port 2189H

3.2.2 Arithmetic and Logical Instructions

This group contains the following instructions
3.2.2.1 Addition Instructions
ADD/ADC Instructions Syntax: ADD destination, Source
Destination [destination] + [source]
For ADC destination, source
Destination  [destination] + [source] + Carry;
The source in both instructions could be a register, an immediate number, or a memory
location. The source and the destination cannot be memory place at the same time. The
source and the destination must be a byte or a word. The flags affected by these
instructions are AF, CF, OF, PF, SF, and ZF.
Examples:
ADD AL, 0F0H ; ADD immediate 0F0H to the content of AL and store the sum in AL
ADC BX, DX ; add the contents of the registers BX and DX and Carry flag and
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; store the sum in BX. BXDX+BX+CY

ADD CX, TOTAL [BX] ; ADD word from effective address TOTAL and BX to the content of
; CX

INC Instruction:
Syntax Increment destination
This instruction increment the value in the destination by one (adds one to the content of
the specified destination). The destination could be a memory location, or a register. This
instruction affects the flags AF, OF, PF, SF and ZF flags.
Examples:
INC AL
AL AL + 1
INC BX
BX BX + 1
INC WORD PTR [BX] ; Increment word at offset BX in DS.

3.2.2.2 Subtraction Instructions

This group of instruction contains the following instructions

▪ SUB: subtraction
▪ SBB: Subtraction with borrow
▪ DEC: Decrement (Subtract one)
▪ NEG: 2’s Complement of a number

SUB/SBB Instructions:

Syntax SUB/SBB destination, Source

Destination [destination] - [source]

For SBB destination, source
Destination  [destination] - [source] - Carry;
The source in both instructions could be a register, an immediate number, a register or a
memory location. The source and the destination cannot be memory place at the same
time. The source and the destination must be a byte or a word. The flags affected by these
instructions are AF, CF, OF, PF, SF, and ZF.
SUB AL, 0F0H ; Subtract immediate 0F0H from the content of AL and store the
; difference in AL
SUBB BX, DX ; Subtract the contents of the registers BX and DX and Carry flag
; and store the difference in BX. BXBX-DX-CY
SUBB CX, TOTAL [BX] ; Subtract word from effective address TOTAL and BX from the
; contents of CX

DEC INSTRCUTION: decrement destination.

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This instruction subtracts one (1) from the specified destination. The destination may be a
register or a memory location. The flags affected by this instruction are AF, OF, PF, SF, and
ZF.

DEC AL
AL AL - 1
DEC BX
BX BX - 1
DEC WORD PTR [BX] ; Decrement a word at offset BX in the DS

NEG INSTRUCTION: form the 2’ complete

This instruction replaces the number in the destination with the 2’s complement of that
number. The destination can be a register or a memory location.

This instruction can be implemented by inverting each bit and adding 1 to the inversion.
This instruction affects the flags AF, CF, SF, PF, ZF and OF.

NEG AL ; if AL=0011 0101 35H

; Replace number in AL with its 2’s complement

; AL=1100 1011 CBH

3.2.2.3 Multiplication Instructions

This group contains the instructions

▪ MUL : Unsigned multiplication

▪ IMUL : Signed multiplication

MUL Instructions: MUL Source

This instruction multiplies the unsigned number in the source with the number in AL or
AX. Remember that the register AX is used as an accumulator. When a word is multiplied
by the content of AX, the most significant word of result is stored in DX and least
significant word of the result is stored in AX. MUL affects the flags AF, PF, SF and ZF.

MUL BL ; AX ALxBL

MUL BX ; DX[DXxBX] high Byte
; AX[DXxBX] low Byte
MUL WORD PTR [BX] ; multiply AX by the number in DS pointed to by the
; offset in BX

IMUL Instructions: MUL Source

This instruction multiplies the signed number in the source with the number in AL or AX.
When a word is multiplied by the content of AX, the most significant word of result is
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 8086 Assembly Language Programming and Instruction Sets

stored in DX and least significant word of the result is stored in AX. MUL affects the flags
AF, PF, SF and ZF.

If the upper byte of the 16-bit result or upper word of 32-bit result contains only copies of
the sign bit (all 0’s or all 1’s), then the CF and the OF flags will both be 0’s.

IMUL BL ; AX ALxBL

IMUL BX ; DX[DXxBX] high Byte
; AX[DXxBX] low Byte

3.2.2.4 Division
This group contains the

• DIV
• IDIV

DIV Instruction:

Syntax DIV Source

This instruction is used to divide an unsigned word by a byte or to divide an unsigned

double word by a word. When dividing a word by a byte, the word must be in AX register.
After division AL will contain an 8-bit quotient and AH will contain an 8-bit remainder. If an
attempt to divide 0 or the quotient is too large to fit in AL (greater than FFH), the 8086 will
automatically execute a type 0 interrupt.

When a double word is divided by a word, the most significant word of the double word
must be in DX and the least significant word must be in AX. After the division the AX will
contain a 16-bit quotient and the DX a 16-bit remainder.

If dividing of a byte by a byte is desired it is important to put the byte in AL and pad AH
with all zeroes. The following example demonstrates how binary division is carried out.

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 8086 Assembly Language Programming and Instruction Sets

Example

DIV BL ; AX AX/BL

; quotient in AL and Remainder in AH
DIV BX ; DX[AX/BX] high Byte (remainder)
; AX[AX/BX] low Byte ( quotient)

3.2.2.5 Comparison
Syntax CMP Destination, Source
The comparison instruction (CMP) compares a byte/word from specified source with a
byte/word from the specified destination. The source and destination must both be a byte
or word. The source could be an immediate number, a register, or a memory location. The
destination can be a register or a memory location, but both the destination and the source
cannot be memory places at the same time. The comparison is done by subtracting the
source byte or word from the destination byte or word. The result is not stored in the
destination. Rather only the flag registers are affected. Both the source and the destination
remain unchanged. The flags updated include,
The flags affected are AF, OF, SF, ZF, PF, and CF
Segment registers are not comparable; therefore the register cannot be the segment
registers
Examples
CMP BL, 01H ; compare an immediate number 01H with byte in BL
CMP CX, BX ; compare word in BX with word in CX
CMP CX, TOTAL ; compare word at the displacement TOTAL in DS with the
; word in CX
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3.2.2.6 BCD and ASCII arithmetic Instructions

This instruction set contains arithmetic manipulation for both BCD (binary coded decimal)
and ASCII (American Standard Code for Information Interchange). This instruction set can
therefore be divided into two sections.
3.2.2.6.1 BCD Arithmetic
BCD is a way of representing decimal numbers in terms of binary numbers. We have to
remember that the decimal number system uses digits from 0-9; therefore, binary numbers
should be coded to represent this numbers directly. Using three bits we can only represent
decimals from 0 to 7, but 8 and 9 is left. Therefore it implies that we must use 4bit number
system which lets us represent all the decimal digits from 0-9 and even more. However, the
four bits now are surplus. And we will not use any binary nibbles beyond 1001. There are
basically two types of binary coded decimals. These are compressed BCDs and
Uncompressed BCDs. In uncompressed BCDs we use one byte, 8-bit to represent one
decimal and in compressed BCD we use one nibble to represent a digit. The following table
shows the two representations.
Decimal Uncompressed
Compressed BCD
Digit BCD
0 0000 0000 0000
1 0001 0000 0001
2 0010 0000 0010
3 0011 0000 0011
4 0100 0000 0100
5 0101 0000 0101
6 0110 0000 0110
7 0111 0000 0111
8 1000 0000 1000
9 1001 0000 1001

This sub instruction set contains two instructions. They are DAA (Decimal Adjust After
Addition) and DAS (Decimal Adjust after Subtraction). Both are used to adjust the results
after the specific operation.
DAA Instruction
This instruction is used to make sure the result of adding two packed BCD numbers is
adjustable to be a formal BCD number. To demonstrate the function of this instruction let
us pay attention to the following example,
1001 + 1000 = 10001
9 + 8 = 17
The sum of the two binary numbers has just generated another binary number of five bits.
This is not any of the BCD format. We here understand that addition of BCDs may results
into non-BCD format that has to be re-arranged into BCD again. (Note that 10001 is not 17
in BCD). This sum can be corrected and changed into BCD by adding 6 in binary to the
sum calculated.

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 8086 Assembly Language Programming and Instruction Sets

0001 0001 + 0110 = 0001 0111 0001 0111

→
17 + 6 = 23 1 7

Adjusting of the BCD sum into BCD in 8086 can be achieved using the following algorithm.

1. If the lower order four bits (D3-D0) in AL is greater than 9 or if AF is set the
instruction adds 6 (06) to the low order four bits.
2. If the value of the high-order four bits (D7-D4) in the AL is greater than 9 or if
carry flag is set, the instruction adds 6 (60) to the high-order four bits.

Example

1 ; AL=0011 1001 = 39 BCD

; CL=0001 0010 = 12 BCD
ADD AL, CL ; AL=0100 1011 = 4B H
DAA ; Add 0110 because 1011>9
; AL=0101 0001 = 51 BCD
2 ; AL=1001 0110 = 96 BCD
; BL=0000 0111 = 07 BCD
ADD AL, BL ; AL=1001 1101 = 9D H
DAA ; Add 0110 because 1101>9
; AL=1010 0011 = A3H
; 1010>9 so add 0110 0000
; AL=0000 0011= 03 BCD, CF=1 the
; result is 103

This instruction updates the AF, CF, PF, and ZF. The OF is understand after DAA. Note
that the instruction DAA only works for AL (Register A)

DAS: Decimal Adjust After Subtraction

The instruction is used after subtracting packed BCD numbers to make sure the result is
correct packed BCD.

1. If the lower order four bits (D3-D0) in AL is greater than 9 or if AF is set the
instruction subtracts 6 (06) to the low order four bits.
2. If the value of the high-order four bits (D7-D4) in the AL is greater than 9 or if
carry flag is set, the instruction subtracts 6 (60) to the high-order four bits.

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The DAS instruction updates the AF, CF, PF, and ZF. The OF flag is unaffected after DAS
instruction. The same was as DAA, DAS only affects the AL register.

3.2.2.6.2 ASCII Arithmetic

ASCII numbers range in values from 30H to 39H from the numbers 0-9. The 8086 provides
four instructions for ASCII arithmetic.

• AAA-ASCII adjust after addition

• AAS-ASCII adjust after subtraction
• AAM-ASCII adjust after multiplication
• AAD-ASCII adjust before division

The numbers from 0-9 are represented as 30H-39H in ASCII code. Whenever adding of two
numbers is necessary in ASCII code, it is important to mask upper nibble (3) from the code
before addition.

3.2.3 Basic Logic Instructions

The basic logic instructions are AND, OR, Exclusive-OR and NOT. This group also includes
the test instructions like TEST which is a special form of AND instruction.

3.2.3.1 AND Instructions

Syntax: - AND Source, Destination

Z=X•Y X Y Z
0 0 0
Table 1 Truth Table fore AND gate 0 1 0
1 0 0
1 1 1
This instruction logically ANDs each bit of the source byte or word with the corresponding
bit in the destination and stores the result in the destination. The source may be an
immediate number, a register or a memory location. The destinations could only be a
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 8086 Assembly Language Programming and Instruction Sets

register or a memory location. The flags affected include PF, SF and ZF. Both CF and OF
are zero after AND operation.

; AL=0011 1001 = 39 H
; CL=0001 0010 = 12 H
AND AL, CL ; AL=0001 0000 = 10 H
One of the most important application of the AND operations is masking. In masking we
clear bits. Any value AND ed with zero is zero.

3.2.3.2 OR Instructions
It is known that OR operation produces logic 1 whenever one of the two inputs is one.
broadly speaking if any one of the inputs to an OR gate is one, then the output will be one.

Syntax OR destination, source

X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
Table 2 Truth Table for OR gate

The instruction OR logically ORs all bits in the destination with bits in the source and
stores the result in the destination. The source may be an immediate number, a register or
a memory location. The destination can only be a memory location or a register.

; AL=0011 1001 = 39 H
; CL=0001 0010 = 12 H
OR AL, CL ; AL=0011 1011 = 3B H
The OR instruction has a special function. It is used to set bits. Remember that any bit
ORed with one is one. Flags affected are PF, SF and ZF. Both CF and OF are both 0 after
OR instruction.

3.2.3.3 XOR Instructions

XOR Instruction
Syntax XOR destination, source
XOR produces result one (1) whenever there are odd number of one is present. Z=XY (Z=X
NOT Y+Y NOT X)

X Y Z
0 0 0
0 1 1
1 0 1
1 1 0
The source may be an immediate number, a register or a memory location. The destination
may be a register or a memory location. Flags affected are PF, SF and ZF. Both CF and OF
are both 0 after OR instruction.
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; AL=0011 1001 = 39 H
; CL=0001 0010 = 12 H
XOR AL, CL ; AL=0010 1011 = 2B H
XOR instruction has a special function. If an unknown number is XORed with all ones it
gives all toggled bits. Therefore XOR is used to toggle even unknown values.

3.2.3.4 NOT Instructions

NOT Instruction:
Syntax: NOT Destination
The NOT inverts each bit of a byte or a word. The destination can be register or a memory
location.
; AL=0011 1001 = 39 H
NOT AL ; AL=1100 0110 = C6 H
NOT does not affect any flags

Refer the following topics from Microprocessors and Interfacing, first Edition, 2009. A.P Douglas and
D.A Douglas page 3-32 to 3-50

3.2.4 Shift and Rotate Instructions

Shift instructions set binary bits to the left or right by shifting them within a register or
memory location. These operation also perform multiplications by powers of 2+n (left shift) or
division by powers of 2-n (Right Shift). Shift operations can be categorized into logical and
arithmetic shift.

3.2.4.1 Shift Instructions

3.2.4.2 Rotate Instructions
3.2.5 String Instructions
3.2.6 Program Control Transfer Instructions
3.2.6.1 CALL and RET Instructions
3.2.6.2 JMP Instructions
3.2.6.3 Conditional Jump
3.2.7 Iteration Control Instructions
3.2.8 Process Control Instructions
3.2.9 External Hardware Synchronization Instructions
3.2.9.1 Interrupt Instructions

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3.3 Assembly Language Programming

A program is a set of instructions arranged in a certain sequence designed to do specific

task. It tells the microprocessor how exactly to do some task. This process of telling the
processor what to do is called “PROGRAMING”. It can also be said that programming is a
way of ‘talking’ to processors in a language which processors can understand. There are
sets of steps that are better be followed. These are:

• Specify the problem: this is a point at which the programmer understands the
problem and decides what is to be done. This is the most important step that is used
to initiate the next steps.
• Designing the solution for the problem: this step involves coming up with the exact
step by step procedure that must be followed in order to come up with the solution.
The design of the same program could vary. This step requires designing and writing
down of the designs.
• Coding: once the problem is specified and designed, the next step would be coding
the design. Coding is also known as implementing the problem. Coding is telling the
processor what to do in which order. This requires skill so that the programmer may
select appropriate instructions to do the task. Coding for the same design could vary
depending on the experience and knowledge of the coder.
• Debugging: once the program is developed and implemented (coded), the next step is
debugging the code. Debugging is the process of testing the code if it does exactly
what it is supposed to according to the design procedure. During this process errors
are found and fixed.

There are few important questions to understand. These are

• How to develop program logic?

• How to tell the program to the processor?
• How to code the program?
• How to test the program?

There is a conventional way of providing what to be done. This is known as flow charts.
Flow charts give the actions to be performed in step by step fashion. This is a graphical way
of representing the actions.

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 8086 Assembly Language Programming and Instruction Sets

Figure 14 Graphical symbols used in flow chart

There are important steps in coming up with a 100 percent functional program. This
involves understanding the various types of languages that machines (microprocessors)
understand. Even though there are high level programs that can take the filthy works of
assembling and linking, understanding the assembler language brings in great
understanding how processors work. A program which has simply a sequence of binary
coeds for an instruction is called machine level language program. This takes a name
machine language just because it is made up of series of zeroes and ones that machines
directly understand. However, writing machine language for humans is extremely
complicated. Therefore, there must be another way of presenting these codes to humans by
compromising the level the machines understand it. Getting one more stage above the
machine language is the assembly language. The assembly language is relatively much
easier for a programmer to understand and write. We have already studied instructions in
their assembly form. AND is one of these. However, it is important to note that the
instructions AND shall finally be converted in its machine equivalent (zeroes and one). In
assembly language we have opcodes or mnemonics that represent the specific zeroes and
ones in machine languages.

A sample flow chart is shown as follows

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 8086 Assembly Language Programming and Instruction Sets

An assembly code is divided into sets of fields. These fields are:

• Mnemonic
• Operand/s
• Comments

A mnemonic is an instruction itself. An instruction could address one or two operands. The
comment is an optional field used to indicate what exactly the code does. The mnemonic
generate the control signals while when the operands are data to be processed.

ADD AX, value [BX] ; Add value to AX

Mnemonic Destination Operand Source Operand Comments

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 8086 Assembly Language Programming and Instruction Sets

No Machine Language Assembly Language

Contains binary codes which specify the Language contains mnemonics which specify
1.
operation the operation
Is processor dependent, hence requires Is processor dependent, hence requires
2. detailed internal knowledge of the detailed internals knowledge of the processor
processor
3. Program requires less memory Program requires less memory
4. Program has less execution time Program has less execution time
Program development is difficult Program development is simpler than the
5.
machine language
6. Is not user friendly Less user friendly
There are tips to be followed that help in developing an assembly language program. These
tips are

• Come up with a minimum solution to the problem: this is very important as there
is a requirement of memory spaces. Minimum code requires less memory and is
highly preferable. The design should come up with the minimum solution for the
problem.
• Use proper instruction and advanced instructions: there are more than one set of
instructions that do the same task. Going from one instruction to the other should be
based on the fact that it results in better performance for the intended application
rather than a programmer being familiar with it. Therefore, knowledge of instructions
and instruction sets is mandatory. Here falls addressing modes too. Remember that
addressing modes can indirectly specify the type of the data and addressing modes
result in different execution clock cycle for the instruction which directly affects the
performance of the program. For example, the following explains two possible ways of
implementing a code for moving blocks of data from one place to another.

One can see that the second approach requires less number of instructions and is
therefore more efficient, meaning that it occupies less amount of memory space.

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 8086 Assembly Language Programming and Instruction Sets

• Prepare documentation; a program must be made to be providing enough

information so that other users can utilize the program module without having to
examine its internal structure. Information should include
1. Description of the purpose of the program
2. Description about the subroutine nature, if or if not passing parameters and
return values
3. Register and memory locations used
4. Proper comments for each instruction used.

Figure 15 Steps in Program development and Execution

3.3.1.1 Assembling Processes

An assembler translates a source file that was created using the editor into machine
language such as binary or object code. The assembler usually produces two different types
of files. The one is called the object file and the other assembler list file. The object file
contains the binary code for the instructions and the information the addresses of the

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 8086 Assembly Language Programming and Instruction Sets

instructions. The list file contains the assembly language statements, the binary code for
each instruction, and the offset for each instruction. The following figure illustrates this.

Figure 16 A program containing object and list file

The following steps describe how the assembler functions.

1. Reads the source program instructions

2. Create a symbol table in which all symbols used in the program, together with their
attributes, are stored.
3. Replace all mnemonic codes by their binary codes
4. Detect any syntax errors in the source program
5. Assign relative address to the instructions and data.

3.3.1.2 Linking Processes

Linking is a process of joining several object files into single larger object file. Linking aids
in designing one big program. Usually programs can be developed separately in a logical
fashion and linked together to form one large program. A set of instruction which does one
specific task is designed and separately saved. When there is a need to use the module, one
can easily call the routine and add it into the code. The linker process produces a link file
that contains the binary codes for all the combined modules. The linker also produces a
map which contains the address information about the linked files. The linker however,
does not assign absolute addresses to the program; it only assigns relative addresses
starting from zero. This kind of program is said to be re-locatable because it can be placed
anywhere in the memory.

3.3.1.3 Debugging Processes

Debugging a program requires loading the object file of the program into the memory of the
target processor and executes it to see if it is possible to come up with the desired output. A
debugger is usually a software program or a hardware kit. In case of software applications,
the debugger stands on the behalf of the processor and simulates it fully. Debugger
software allow you to
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 8086 Assembly Language Programming and Instruction Sets

1. To look into the contents of register and memory locations after the program runs
2. Allows the users to change the content of registers and memory locations
3. Some debuggers allow users to execute sets of instructions step by step
4. Allows users to set breakpoints and execute lines up to the points.

Figure 17 Some assembler programs

3.3.2 Timings and Delays

In real time applications, such as traffic light control, digital clock, process control, serial
communication, it is very important to adjust the processor with real time happenings. In
case of traffic light applications there is a time between green and yellow light. We just
know that processors are extremely fast compared to human beings. Sometimes it is a
must to delay processors to be comprehendible with human world. For example a processor
running with a crystal frequency of 2MHz can turn a led 2 million times in a second.
Human eyes see a continuously lighting led, for a human eye cannot respond to that much
frequency. If one is therefore developing an application like traffic light which requires 2
seconds ON for yellow, the programmer must delay the processor for about 1000000 cycles.
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In this section we shall see the possible ways of providing delays in 8086. All are software
delays

3.3.2.1 Timer Delay Using NOP Instruction

There is a special instruction in 8086 that does nothing. This instruction is NOP
instruction. It is a mnemonic for no operation. 8086 requires 3 clock cycles to finish
executing NOP. Therefore one can at least get three clock cycles by executing it in between
two instructions.

3.3.2.2 Timer Delays Using COUNTERS

Another way to delay a processor is by making it count up to certain desired number. One
should load the number to be loaded onto the CX register so that counting it will produce
the desired amount of delay in the program. Look at the following example

Label Delay code Comment Clock cycles required

MOV CX, COUNT ; Load Count 4
BACK: DEC CX ; Decrement Count 2
JNZ BACK ; If Count  0, repeat 16/4
The JNZ instruction requires 16 clock cycles when the conditions is met (when CX is not
zero). When it is zero, the instruction must take 4 clock cycles. Now let us see how many
total clock cycles we can get from the above loop.

= 4 + (COUNT-1) X (2+16) + (2+4)

MOV CX, COUNT Loop Last Loop

For count = 150, the number of clock cycles required are,

= 4 + (150-1) X (2+16) + (2+4)

= 2692 cycles

If the processor is running on 10 MHz, we see that one clock frequency is 0.1µsec, therefore
using the above routine one can get 269.2µseconds.

3.3.2.3 Timer Delays Using Nested Loops

In this approach once or more external loop is added to execute the internal loop multiple
times so that we can get larger delays. The inner loop is nothing but the program we have
seen in the above immediate section.

Label Delay code Comment

MOV BX, Multiplier Count ; Load multiplier count
REPE: MOV CX, COUNT ; Load Count
BACK: DEC CX ; Decrement count
JNZ BACK ; If COUNT  0 repeat
DEC BX ; Decrement multiplier count
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 8086 Assembly Language Programming and Instruction Sets

JNZ REPE ; If not zero repeat

This program will provide much more clock cycles

=[ 4 + (COUNT-1) X (2+16) + (2+4) ] X multiplier count

MOV CX, COUNT Loop Last Loop

For count = 150 and multiplier=50, the number of clock cycles required are,

= [4 + (150-1) X (2+16) + (2+4)] X 50

= 134600 cycles

If the processor is running on 10 MHz, we see that one clock frequency is 1µsec; therefore
using the above routine one can get 13.46ms.

Exercise: Write an 8086 ALP to generate a delay of 100ms, if the processor is running
on 10 MHz frequency.

3.4 8086 System Configuration

8086 can be configured to work in two different modes. These are minimum and maximum
modes. In minimum mode, the processor is alone and is required to take care of all the
coordination. In maximum mode, two or more processors work in conjunction to each other
and therefore must have another third party to coordinate them. The minimum mode is
often used for small systems and the maximum mode for larger tasks requiring complex
systems. There is no literal physical difference between the two modes. There difference is
only setting of the MN/MX (MX bar). Let us see the special pins that will affect the mode in
8086.

3.4.1 Minimum Mode of Operation

To set the microprocessor into a minimum mode the following configuration is required.

1 INTA (Interrupt Acknowledge) Output: in such configuration an interrupt is

acknowledged and is therefore an interrupt service routine (ISR) will be executed.
This acknowledgement signal consists of two negative going pulses which appear
in two consecutive bus cycles. The first pulse informs the external interface that
its interrupt has been recognized and upon the receipt of the second, the interface
is to send the interrupt type to the processor over the data bus.
2 ALE (Address Latch Enable) Output: this is used to inform an external interface
to demultiplex the AD0-AD15 into A0-A15 and D0-D15 using external latches.
3 DEN (Data Enable) Output: this signal informs that the CPU is ready to receive or
send data

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 8086 Assembly Language Programming and Instruction Sets

4 DT/R (Data transmit/Receive) Output: this controls the data flow direction.
High on this pin indicates that the processor is transmitting while the low is for
receiving.
5 M/IO Output: is used to differentiate between memory (M/IO=HIGH) or IO
(M/IO=LOW) data transfer.
6 WR: Write Output: when 8086 writes data to either external IO or memory device
this pin goes LOW.
7 HOLD input, HLDA Output: A HIGH on HOLD pin indicates that another master
(DMA) is requesting to take over the system bus. When a HOLD is received the
processor outputs HLDA signal HIGH as an acknowledgement. At the same time
the processor tristates the system bus. A LOW on HOLD gives the system bus
control back to the processor. Processor then output LOW signal on HLDA.

7.1.1 Maximum Mode of Operation

1 QS1, QS0 (output): these two output signals show the status of the instruction
queue. They show the activity in the instruction queue in the previous clock cycle.
QS1 QS0 Status
0 0 No operation, queue idle
0 1 First byte of an opcode
1 0 Queue is empty
Subsequent byte of an
1 1
opcode

2 S2, S1, So (Active Low) (outputs): these three status signals indicate the type of
transfer to take place during the current bus cycle.

S2 S1 So Machine Cycle
Interrupt
0 0 0
Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Inactive-Passive

3 LOCK (Active Low): signifies that an instruction with a LOCK prefix is being
executed and the bus is not to be used by any other processor.
4 RQ/GT1 and RQ/GT0 (Active Low) in the maximum mode, HOLD and HLDA pins
are replaced by the RQ (Bus Request) and GT0 (Bus Grant), and RQ/GT1 signals.
By using bus request, another master can request for the system bus and
processor communicate that the request is granted to the requesting master by
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 8086 Assembly Language Programming and Instruction Sets

using bus granted signals. Both signals are similar except the RQ/GT0 has higher
priority than RQ/GT1.

Figure 18 Pin Configuration of 8086 in both modes

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 Chapter-4 Interfacing

4 Interfacing
Interfacing is a process of joining different equipment to a microprocessor so that a specific task shall be
worked out. A microprocessor is a controller that coordinates tasks of various devices connected to it. In this
section, we shall see interfacing of IOs, timers, serial devices, interrupts and memory. In each section, we shall
also examine the special hardware that will be integrated into the 8086 system to provide appropriate functions.

4.1 Basic IO Interfacing

There are basically two methods of interfacing I/O to the microprocessor. These are isolated I/O and memory-
mapped I/O. In isolated I/O, the I/O instructions such as the IN and OUT are used to read or write the I/O
port. However, in memory-mapped I/O, the address of an IO port is going to be indirectly be addressed so that
the location will be written or read.

Figure 1 8-Toggle switch input interfacing

Figure 2 Basic Output connection using LEDs

Page 1 of 30
 Chapter-4 Interfacing

4.1.1 Isolated I/O

The most common I/O transfer technique used in the Intel microprocessor-based system is isolated I/O. The
term isolated describes the way the I/O locations are isolated from the memory system in a separate I/O
address space.
FFFF

FFFF
1Mx8

64Kx8

0000 0000
Figure 1 Isolated I/O

FFFF

I/O

0000
Figure 2 Memory-mapped I/O

In isolated I/O, the address for the I/O devices called PORTS are separated from the memory. This implies
that only the instructions IN and OUT are used to access I/O devices. This is one disadvantage. A separate
control signal for I/O space are developed using the (M/IO and W/R). The address for isolated IO ranges
from 0000 to FFFF in 8086 (remember that 8086 has 16 bit IO addressing capability).

4.1.2 Memory-mapped I/O

In these IO addressing, memory reference instructions are used. The address for each device is stored in a
memory (20-bit address for each device). This concept would be best explained if we look at the personal
computer IO interfacing technique. CPU’s internal memory is divided into sections of memory addresses
reserved for various types of IO devices.

Figure 3 IO map of a personal computer with a fixed IO address

4.2 Programmable Peripheral Interface (PPI)

The 8086 can be interfaced with a peripheral device that can again drive most of the IO device which are
directly connected to it. One of the most popular programmable peripheral devices is the 8255. It is widely
deployed in many applications for the fact that it is cheap and easy to use. The 8255 has 24 IO pins.

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These can be programmed in two groups of 12 pins. These groups again can be made to operate in three distinct
modes. 8255 is a TTL compatible device. Therefore, when one needs to interface some higher voltage or current
valued devices, it is important to device driver circuits.

The ports are usually divided into three labels. Port A (PA7-PA0), port B (PB7-PB0) and port C (PC7-PC0). The
8255 is enabled or selected by its CS (Active low) when it is programmed, read or written.

Figure 4 Pin Outs of 8255

Figure 5 Block Diagram of the 8255

We just have seen that the 8255 has three ports. Now selecting one of the ports among the others is versatile
and is achieved through the A0 A1 pin. These two pins will select the ports to be used according to the
following table
A1 A2 Function
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Command Registers

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Ports can also be arranged into groups. One can form two main groups of the 8255 as follows.
Group A: port A including the upper nibble of the port C
Group B: port B including the lower nibble of the port C

The following figure shows the possible way of interfacing the 8255 to a microprocessor and address bit
combinations for three port selections.

Figure 6 Interfacing of the 8255 to a microprocessor

4.2.1. Programming the 8255

The 8255 is a programmable peripheral interface. Therefore it is possible to set into various modes so that one
can select the desired modes. This is achieved by one of the internal registers of the 8255. This register is a
control registers of a word wide. The programmer can write basically two types of command word bytes to
these registers. These are

• Command Byte A
• Command Byte B
Command byte A is used to program the port groups as defined above as

▪ Inputs or outputs
▪ In either modes 0, 1 and 2
The command byte B is used to set or clear specific bits when configured in modes 1 and 2.

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4.2.2. Operating modes of the 8255

The 8255 can be set into three distinct modes of operation. These are

▪ Mode 0
▪ Mode 1
▪ Mode 2
Mode 0: This mode is used to set the ports into group A. Both group A and group B have 12 ports. This mode
is the most commonly used and all pins are simple latched input or output.

Mode 1: This is an occasionally used mode in which most pins of port C are used to provide handshaking
signals to an IO device. This mode enables IOs to operate asynchronously.

Mode 2: In this mode, only group A is used. The mode sets port A into a bidirectional port while port C is used
for handshaking signals.

Programming the 8255

To program the 8255, the command register mode and the operation mode of command Byte A must be
selected.

For example, to program all the ports as an output in mode 0 (this is the most common used configuration). We
can write an ASP as follows

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MOV AL, 80H

MOV DX, COMMAD_REGISTER
OUT DX, AL

Figure 7 Programming the 8255

4.3. Timer Interfacing

The 8254 is a fundamental timer module that consists of three independent 16-bit timers. All the timers are
programmable. Since these timers are 16-bit timers, they can count up to 216 binary coded decimals (BCDs).
Timers are extremely useful at applications where microprocessors are used to control real time events. They are
used to generate various types of waves and used in complex motor control application. 8254 runs on a
maximum of 10MHz clock. Timers like the PPI are programmed by writing the control word to the command
registers.

The timer is interfaced to a microprocessor through bits A1 and A0. These bits therefore define the immediate
task as follows.

A1 A2 Function
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word (Command Byte)

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Figure 8 Structure and Pin definitions of 8254

4.2.1 The 8254 Programmable Interval Timer (PIT)

The 8254 is made up of 3 identical 16-bit timers. If one needs to understand all the timers, it is very important to
understand the working principle of the single one timer. The timer fortunately has two byte latch on its output,
as this result therefore; the count output will stay on the ports till it is cleared.

Figure 9 Close examination of a timer block

Let us now examine how the timer 8254 can be programmed. We have just seen that the control word selection
is achieved using the A1A0=11. The rest c combinations are used to select one timer among three. A counter
must first be programmed before it can be used. Programming a counter involves selecting a counter, writing
the initial count value and specifying the count type. All these values can be set after the control word
(A1A0=11) is applied. During timer programming,

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• CS (Active Low)=0
• A1A0=11
• RD (Active Low)=1
• WR (Active Low)=0

After these bits are set as stated, selection of one of the three counters, loading initial value and specifying count
type must be provided in the data bits coming. (D0 to D7). The bits D0 to D7 can be used as follows during
programming.

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

Bit definitions

SC1 SC0 TASK

0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read Back Command

Bits M2 to M0 define modes of counting

M2 M1 M0 MODE
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
Bits RW1 and RW0 are defined as

RW1 RW0 FUNCTION

0 0 Counter Latch Command
0 1 Read/Write Least Significant Byte Only
1 0 Read/Write Most Significant Byte Only
Read/Write Least Significant Byte first and then Most Significant
1 1
Byte
The BCD bit is defined as

BCD FUNCTION
0 Binary Counter
1 Binary Decoded Decimal (BCD) Counter [4 Decades]

The initial count for the currently selected counter must be sent after the control word. The initial count values
are written into the IO addresses of the specified counter. Upon programming all the three counters, one must
follow certain sequences otherwise it will result in invalid settings. The following four sequences are all possible
followed by the initial counts.

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Read can have three basic techniques. These are,

1. Simple Read: inhibit clocking by clearing G (disrupt future counts) to ensure stable counter at a proper
level and then simply read the counters at their address (for example A1A0=01 for counter one)
2. Issue a counter latch command by writing appropriate byte into the control word register. This is
achieved by setting RW1RW0=00 and selecting the appropriate counter using SC1 SC0. This command
latches the counter’s output parallaly and the count value is available in the Output Latch (OL) and
remains unchanged till the output is read by the microprocessor or the counter is re-programmed.
After the timers are programmed, the next step will be reading their count values. Reading operation
happens while when the counters count.

For a read operation to be set the following conditions must be fulfilled

• A1A0=11
• CS (Active Low)=0
• RD (Active Low)=0
• WR (Active Low)=1

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 0 0 X X X X

D5D4 =00 designates Counter Latch Command

SC1 SC0 Counter

0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read Back Command

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3. Using the Read Back Command:- this is a command word (A1A0=11)written into the control word to
latch status and or count of any of the three counters. All the three counters can be specified
simultaneously. The command word looks like the following.

Figure 10 The Read back Command Word format

Figure 11 Format for Counter Status Register

Counter modes

Mode 0 Event counter

Mode 1 Hardware triggered One-Shot
Mode 2 Divide-by N Counter
Mode 3 Square Wave Generator
Mode 4 Software Triggered Strobe
Mode 5 Hardware Triggered Strobe
Mode 0

This mode is used to count events. It is also used to interrupt a processor on

• Arrival of predetermined number of events (1→0 clock transition = n+1)

• Or upon elapse of ∆t = (n+1)*Tclk

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Figure 12 Timing diagram for Mode 0

Mode 1

This mode is hardware triggered one-shot. Gate G is used as the monostable hardware trigger input. This
application loads the counter on the next falling edge after the trigger goes high and the output remains low till
the terminal count. The duration of the output will be nTclk. If the Gate goes high again, the monostable is
retriggered and the count will be postponed for another duration.

Figure 13 Mode 1 timing diagram

Mode 2

This mode is used to divide a frequency by a specified number. (it is a programmable frequency clock). The gate
G is always enabled to count. The out frequency fOUT=Clock frequency/n.

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Figure 14 Mode 2 timing diagram

Mode 3

This mode is similar to mode 2 except it only produces square wave outputs.

Figure 15 Mode 3 Timing diagram

Mode 4

This will give an active low OUT signal when the count finishes. The count remains for n+1 pulses. This is used
to trigger external devices.

Figure 16 Mode 4 timing diagram

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Mode 5

This is hardware triggered strobe output (Active Low). Gate G is used as hardware trigger. Upon receiving a
high on the gate the OUT gives an active low of one pulse (for the duration of one period). This is a similar
mode of counting to that of mode 1.

Figure 17 Mode 5 Timing Diagram

Summary of the counting modes

Mode Specifications
M2 M1 M0 Function
# (n = pre-loaded initial count, Tclk = clock interval)

0 0 0 0 Event Counter Delay to rising edge = (n+1) Tclk

0 0 1 1 Hardware-Triggered One-Shot Width of negative going pulse = (n) Tclk

X 1 0 2 Divide-by-N Counter fout = fclk / (n) Duty cycle: Mark:Total = (n-1):n

X 1 1 3 Square-Wave Generator fout = fclk / (n) Duty cycle  50% (for all n)

1 0 0 4 Software-Triggered Strobe Strobe width = Tclk Strobe Delay = (n+1) Tclk

1 0 1 5 Hardware-Triggered Strobe Strobe width = Tclk Strobe Delay = (n) Tclk

Interfacing examples
In the following schematic, it is desired to generate 100KHz and 200KHz frequency from counters 0 and 1. The
wiring diagram and the assembly language program would be as follows.
TIME PROC NEAR USES AX DX
MOV DX, 706H ; address Control register
MOV AL, 00110110B ; program counter 0 for mode 3
; Counter Load/Read format is 2 bytes (1 for mode 2)
OUT DX, AL
MOV AL, 01110100B ; program counter 1 for mode 2
OUT DX, AL

MOV DX, 700H ; Address counter 0

MOV AL, 80 ; Load initial count 80d into counter 0
; LS byte of initial count
OUT DX, AL
MOV AL, 00; ;Then MS byte of initial count

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OUT DX, AL

MOV DX, 702H ; Address counter 1; A procedure that programs the 8254 timer to function as illustrated in Fig. 18 LS 1st)
MOV AL, 40 ; Load initial count 40d into counter 1
OUT DX, AL
MOV AL, 00 ; Then MS byte of initial count
OUT DX, AL

RET
TIME ENDP

Figure 18 Timer interfacing example

4.4 Serial I/O Interface

We have just seen how the PPI can be used to interface parallel IOs. In this discussion we shall look into how
one can interface devices serially. There is an advantage in terms of hardware signal lines. The following figure
19 shows the difference between the serial and parallel data transfer.

Figure 19 Serial Vs Parallel Data Transfer

Depending on the communication channel interface between the receiver and transmitter, one can have three
types of data transfers between a receiver and transmitter.

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4.4.1 Asynchronous Communication

Asynchronous communication is a type of communication between two entities that requires no exact timing
base for both the receiver and the transmitter. If one wishes to use the asynchronous communication, it is
important to provide the frame delimination bits (start and stop bits). The bit streams in between the two bits
can be recognized by the receiver provided that the timing information is known. In asynchronous
communication, therefore timing information can be embedded into the bit streams and sent over a link. The
receiver can then extract the timing information and use it to decode the data.

4.4.2 Programmable Communication Interface UART 16550

Our discussion here forth will be based on the 16550. This is a synchronous Asynchronous communication
interface chip. It has totally independent Tx and Rx and can be used in simplex, half duplex or full duplex.

Figure 20 Pin Configuration of 16550

Programming the UART has two steps

1. Initializing the UART
a. Programming the line control registers
b. Programming the baud rate generator

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2. Operating the UART (opening the actual communication)

The 3 IO address bits from the microprocessor can refer to various functions as follows.

A2 A1 A0 Function

0 0 0
Receiver buffer (read data from RX) and transmitter holding (write data to TX). Also write LS byte of baud rate divisor

0 0 1
Interrupt enable. Also write MS byte of baud rate divisor

0 1 0 Interrupt identification (read) and FIFO control Register (write)

- Used for operation dialog programming

0 1 1
Line control Register (Write into the line control register to program asynchronous communication at initialization)

1 0 0
Modem control

1 0 1
Line status LSTAT (Read the line status register to see if TX or RX are ready and to check for errors )

1 1 0
Modem status

1 1 1
Scratch

1. Programming the UART

a. Programing the line control register.
As seen from the table above to get access to the line control registers the address lines must be A2A1A0=011.
Then let us examine line control register bits.

Figure 21 Programming the Line control Register

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The 3 parity control bits function in the following way.

ST P PE Function

0 0 0 No parity

0 0 1 Odd parity

0 1 0 No parity

0 1 1 Even parity

1 0 0 Undefined

1 0 1 Send/receive 1 (send 1 in place of the parity bit)

1 1 0 Undefined

1 1 1 Send/receive 0 (send 0 in place of the parity bit)

b. Programming the baud rate generator

The baud rate is programmed by loading a 16-bit divisor for the crystal oscillator or the external input frequency
into the I/O port addresses. To write the 16-bit divisor value, the operation will be done in two steps. First,
write the LSB into Byte of the divisor and then the MSB of the divisor. This can be achieved as follows

o {A2 A1 A0} = 000: LS Byte of divisor

o {A2 A1 A0} = 001: MS Byte of divisor

The divisor value is dependent on the oscillator frequency and the baud rate required. The baud rates supported
are
Baud Rate
110
300
1200
2400
4800
9600
19,200
38,400
57,600
115,200
Divisor value can be calculated using the following formula

𝑂𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑜𝑟 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
𝐷𝑖𝑣𝑖𝑠𝑜𝑟 =
(16 ∗ 𝐵𝑎𝑢𝑑 𝑟𝑎𝑡𝑒)

For a certain clock frequency, one can calculate divisor values of each baud rate.

c. Programming the FIFO control Register

The address of this control register is at A2A1A0=010. The 8-bit exposition of the FIFO control register is as
follows

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Figure 22 FIFO Control Register

d. Programing the Line Status Register (LSTAT)

The address of this register is at A2A1A0=101

Figure 23 The Line Status Register

Interfacing Example:

Interface 16550 to 8086 having a clock frequency of 18.432MHz. The desired baud rate is 9600 with frame
format of 7 bit data, odd parity and one stop bit.

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Schematic of the connection

Figure 24 Schematic of the proposed circuit

Program the 16550 using Assembly Language Programs.

;Initialization dialog for Figure 24
;Baud rate 9600, 7 bit data, odd parity, 1 stop bit
LINE EQU 0F3H ; A2 A1 A0 = 011 for the Line Control Register
LSB EQU 0F0H ; A2 A1 A0 = 000 for LSB of divisor
MSB EQU 0F1H ; A2 A1 A0 = 001 for MSB of divisor
FIFO EQU 0F2H ; A2 A1 A0 = 010 for the FIFO Control Register

INIT PROC NEAR

MOV AL,10001010B
OUT LINE,AL ; Enable Baud rate programming See slide 108
; program Baud 9600
; Divisor = 120d (calculate using the given formula)
MOV AL,120 ; LSB of divisor
OUT LSB,AL
MOV AL,0 ; MS Byte of divisor
OUT MSB,AL
MOV AL,00001010B ;program 7 bit data, odd parity, 1 stop bit
OUT LINE,AL ; write the line control register
;(& disable baud rate programming?)
MOV AL,00000111B ;enable transmitter and receiver
OUT FIFO,AL ;by writing into the FIFO control Reg.
RET
INIT ENDP
The next step will be writing the sender and receiver program

SENDER PROGRAM
;//////////////////////////////////////////////////////////////////////////////////////
;A procedure that transmits the byte in AH serially
;via the 16650 UART
LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)
DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)
SEND PROC NEAR USES AX
.REPEAT ;test the TH bit (bit 5) in to see if TX is available

IN AL,LSTAT

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TEST AL,20H ;20H is the mask for the TH bit

.UNTIL !ZERO?
MOV AL,AH
OUT DATA,AL ;send data to TX
RET
SEND ENDP
;//////////////////////////////////////////////////////////////////////////////////////
RECEIVER PROGRAM
; Procedure receives byte from UART into AL if no comm. error
; If error detected, it load Al with ‘?’ as an alert
LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)
DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)
REVC PROC NEAR
.REPEAT
IN AL,LSTAT ;test DR bit
TEST AL,1
.UNTIL !ZERO?
TEST AL,0EH ;test for any error
.IF ZERO? ;no error
IN AL,DATA ;Read RX Data Register into AL
.ELSE ;any error
MOV AL,’?’ ;Put “?” in AL to indicate error
.ENDIF
RET
RECV ENDP
;//////////////////////////////////////////////////////////////////////////////////////

4.5 Interrupts
An interrupt is an event which informs the CPU that its service (action) is needed. The possible sources of
interrupts are:
• Internal fault (e.g... divide by zero, overflow)
• Software
• External hardware:

Hardware interrupts can further be categorized as maskable and non-maskable interrupt. A reset is also one type
of hardware interrupt.

When a CPU is requested to service an interrupt, it will stop or finish (depending on the priority of the
interrupt) the current job. If it is stopping an execution, it will PUSH the current flag register, IP and CS register
and jumps to a fixed memory location known as Interrupt Service Routine (ISR). Upon finishing the ISR block
it will get back to its previous instruction by POPing the aforementioned registers. 8088 has the following
hardware interrupts.

• INTR: Interrupt Request.

o If this interrupt is activated, the CPU will finish the current instruction and respond with the
interrupt acknowledge operation
o Can be masked (ignored) through instructions CLI and STI
• NMI: NonMaskable interrupt.
o Cannot be masked or unmasked through CLI and STI
o Examples are: power failure, memory error
• INTA: Interrupt Acknowledge.
o This is an output from the processor to acknowledge the external device on its interrupt request

The interrupt flag in the flag register is used to mask any hardware interrupt that may arrive on the INTR pin. It
this bit is 0, all incoming interrupts will be masked and shall not be serviced. However, this has no effect on the
interrupts arriving on the NMI pin as the pin is not maskable. The CLI sets the interrupt flag (IF) to 0 and the
STD will set it to 1.

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4.5.1 Interrupt Driven I/O

Unlike programmed IO interrupt programmed IO technique will not inhibit the CPU from executing other
software. This will greatly improve the CPU’s performance as the request may be serviced immediately. Upon
receiving an interrupt request from an IO, CPU will halt its current operation, go to an ISR and execute the
block and come back to where stopped upon completing the ISR. This will bring the following advantages of
interrupt driven IO

▪ Increases the CPU’s throughput(the processor will not waste busy waiting sequential executions)
▪ Will prioritize services
▪ Improves response time

4.5.2 Software and Hardware Interrupts

A hardware interrupt is an electronic alerting signal sent to the processor from an external device, either a part
of the computer itself such as a disk controller or an external peripheral. For example, pressing a key on the
keyboard or moving the mouse triggers hardware interrupts that cause the processor to read the keystroke or
mouse position. Unlike the software type (below), hardware interrupts are asynchronous and can occur in the
middle of instruction execution, requiring additional care in programming. The act of initiating a hardware
interrupt is referred to as an interrupt request (IRQ). NMI and INTR are hardware interrupt of the 8086.
A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction
in the instruction set which causes an interrupt when it is executed. The former is often called a trap or
exception and is used for errors or events occurring during program execution that is exceptional enough that
they cannot be handled within the program itself. For example, if the processor's arithmetic logic unit is
commanded to divide a number by zero, this impossible demand will cause a divide-by-zero exception, perhaps
causing the computer to abandon the calculation or display an error message. Software interrupt instructions
function similarly to subroutine calls and are used for a variety of purposes, such as to request services from low
level system software such as device drivers. For example, computers often use software interrupt instructions
to communicate with the disk controller to request data be read or written to the disk. Software interrupt in
8086 include INTn, INTO, INT3 and BOUND. Special interrupt for given n is as follows (these are all
conditional interrupts)

n Interrupt type
1 Single trap (will be enabled if Trap flag is set)
3 INT3 (Breakpoint)
4 INTO (Overflow) the OF bit in the flag
5 BOUND (Check limits)

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Each interrupt has its own interrupt handler. The number of hardware interrupts is limited by the number of
interrupt request (IRQ) lines to the processor, but there may be hundreds of different software interrupts.
Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a
system is said to be interrupt-driven. Special instruction IRET is used at the end of the ISR for both types of
interrupts.

4.5.3 Interrupt Vectors and Vector Tables

The interrupt vector table (IVT) is located in the first 1024 bytes of memory at address 00000H -003FFH. This
table contains 256 different interrupt of each 4-byte long.

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The interrupt vector contains the starting address (both the offset and segment) of the ISR. The first two bytes
of the vector are the OFFSET address while the second two bytes contain the segment address of the ISR.

4.5.4 The 8259A Priority Interrupt Controller (PIC)

The following are the main features of the 8259A.

• It accepts eight interrupt requests (can be expanded to 64 by using * slave PICs)

• Prioritizes the interrupt requests
• Individual interrupt can be masked independently
• Issues single interrupt request to CPU
• Has various modes of programmable modes of operation

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Figure 25 PIC block diagram and PIN configuration

The sequence that is involved in the interrupt processing is presented below

1. One or more of the interrupt Request lines (IR7-IR0) are set high that in turn will set the corresponding
Interrupt Request Register (IRR) bits.
2. The 8259 will then evaluate these requests and then sends an INT to the CPU, if appropriate
3. The CPU will acknowledges with an INTA pulse
4. When an INTA pulse is received from the CPU, the high priority IRS bit will be set and the
corresponding IRR bit is set.
5. The 8086 will initiate the second INTA pulse. During this pulse, the 8259A releases an 8-bit pointer
onto the data bus where it is ready by the CPU.
6. This completes the interrupt cycle. The End of Interrupt command will be executed at the end of an
ISR.

The IRR Register

• Is a transparent latch (any request will be transparently latched here)

• If the interrupt request is not masked as per the Interrupt Mask Register (IMR), it will reach to the
priority Resolver (PR).
• If a new request arrives with priority higher than the interrupt under service the INT signal is raised by
the PR to make a request to the CPU.
• Upon receiving the INTA signal from the CPU the IRR will be frozen and the highest priority interrupt
is identified by the PR. The corresponding bit of the interrupt in the ISR will be set and the
corresponding IRR bit is cleared.
• On the second INTA signal (pulse), the vector type is sent out and then the INT signal is lowered.

Programming the 8259A

The 8259A accepts two types of command words generated by the CPU:

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1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system
must be brought to a starting point-by a sequence of 2 to 4 bytes timed by WR (Active low) pulses.
2. Operation Command Words (OCWs): These are the command words which command the 8259A to
operate in various interrupt modes. Theses modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A any time after initialization.
Refer to the 8259A PROGRAMMABLE INTERRUPT CONTROLLER application note for the rest of
the information.

4.6 Direct Memory Access (DMA)

Direct memory access (DMA) is a process in which an external device takes over the control of system bus from
the CPU. This communication scheme is meant for high-speed data transfer from/to mass storage peripherals,
like hard-disk drive, magnetic tape, CD-ROM, and sometimes video controllers.

For example, a hard disk may boast a transfer rate of 5 M bytes per second, i.e. 1 byte transmission every 200 ns.
To make such data transfer via the CPU is both undesirable and unnecessary.

The basic idea of DMA is to transfer blocks of data directly between memory and peripherals. The data don’t go
through the microprocessor but the data bus is occupied. “Normal” transfer of one data byte takes up to 29
clock cycles. The DMA transfer requires only 5 clock cycles. Nowadays, DMA can transfer data as fast as 60 M
byte per second. The transfer rate is limited by the speed of memory and peripheral devices.

Figure 26 How DMA works

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4.6.1 Basic DMA Operations

Remembering that the 8086 can work in two modes, let us see how the DMA can be achieved in both cases.
These are the basic DMA operation that must be carried out before any device gets control over data bus. Let us
see at glance how DMA operation is performed in both cases.
In Minimum Mode
The HOLD and HLDA pins are used instead to receive and acknowledge the hold request respectively.
Normally the CPU has full control of the system bus. In a DMA operation, the peripheral takes over bus control
temporarily.
In Maximum Mode
The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals.
Sequence of events of a typical DMA process

1 Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority)
2 8088/8086 completes its current bus cycle and enters into a HOLD state
3 8088/8086 grants the right of bus control by asserting a grant signal via the same pin as the request
signal.
4 DMA operation starts
5 Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to
relinquish bus control.

4.6.2 DMA Controlled I/O

There are basically two three of interfacing IO devices to a processor. These are

• Memory Mapped IO and

• Interrupt driven IO
• DMA controlled IO

However the later is associated only with bulk data movement and is designed to function with other interfaces.
DMA controlled IOs must follow certain procedure in order to get successful data transfer. The followings are
features of DMA protocol

▪ The direct memory access (DMA) I/O technique provides direct access to the memory while the
microprocessor is temporarily disabled.
▪ A DMA controller temporarily borrows the address bus, data bus, and control bus from the
microprocessor and transfers the data bytes directly between an I/O port and a series of memory
locations.
▪ The DMA transfer is also used to do high-speed memory-to memory transfers.
▪ Two control signals are used to request and acknowledge a DMA transfer in the microprocessor-based
system.
▪ The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses
after the current bus cycle.
▪ The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released
control of its buses by placing the buses at their high-impedance states.
▪ The HOLD input has a higher priority than the INTR or NMI interrupt inputs.

4.6.3 The 8237 DMA Controller

The 8237A is a one of the Intel’s DMA controller IC.

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Figure 27 8237 DMA IC

The 8237 can be cascaded to produce Master-Slave architecture. This is used to interface priority based IO
devices. The 8237 DMA controller supplies the memory and I/O with control signals and memory address
information during the DMA transfer. 8237 is a four-channel device that is compatible to the 8086/8088
microprocessors and can be expanded to include any number of DMA channel inputs.

The 8237 is capable of DMA transfers at rates of up to 1.6M bytes per second and each channel is capable of
addressing a full 64K-byte section of memory and can transfer up to 64K bytes with a single programming.

The internal Register of the 8237

▪ The current address register (CAR) is used to hold the 16-bit memory address used for the DMA
transfer.
▪ The current word count register (CWCR) programs a channel for the number of bytes (up to 64K)
transferred during a DMA action.
▪ The base address (BA) and base word count (BWC) registers are used when auto-initialization is
selected for a channel. In this mode, their contents will be reloaded to the CAR and CWCR after the
DMA action is completed. Each channel has its own CAR, CWCR, BA and BWC.
▪ The command register (CR) programs the operation of the 8237 DMA controller
▪ The mode register (MR) programs the mode of operation for a channel.
▪ The request register (RR) is used to request a DMA transfer via software, which is very useful in
memory-to-memory transfers.
▪ The mask register set/reset (MRSR) sets or clears the channel mask to disable or enable particular
DMA channels.
▪ The mask register (MSR) clears or sets all of the masks with one command instead of individual
channels as with the MRSR.
▪ The status register (SR) shows the status of each DMA channel.

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The following table shows the operation along with address lines of some of the listed registers.

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