UNIT – IV

MSP430 INTERFACING
MSP430 INTERFACING: Timer & Real Time Clock (RTC), PWM control, timing
generation and measurements. Analog interfacing and data acquisition: ADC and
Comparator in MSP430, data transfer using DMA.

4.1 REAL TIME CLOCK:

The Real-Time Clock (RTC) is a timer module that provides a clock with calendar. It
provides seconds, minutes, hours, day, month, and year.

Real-Time Clock features include:

 Configurable for Real-Time Clock mode (or) general purpose counter.
 32-bit counter mode with selectable clock sources
 Provides seconds, minutes, hours, day of week, day of month, month and year.
 Interrupt capability
 Selectable BCD or binary format in Real-Time Clock mode.
 Programmable alarms in Real-Time Clock mode.
 Calibration logic for time offset correction in Real-Time clock mode.
 The current time and date are held in a set of registers that contain the following
bytes:

RTCSEC : Seconds
RTCMIN : Minute
RTCHOUR : Hour which runs from 0–23 (24-hour format).
RTCDOW : Day of week which runs from 0–6.
RTCDAY : Day of month (1-31)
RTCMON : Month (1-12)
RTCYEARL : Year, assuming BCD format.
RTCYEARH : Century, assuming BCD format.
 Figure 4.1 RealTime Clock

The Real-Time Clock module can be configured as a real-time clock with calendar function
(or) as a 32-bit general purpose counter with the RTCMODEx bits
(a) Calendar Mode:
 Calendar mode is selected when RTCMODEx = 11.
 In calendar mode, the RTC provides seconds, minutes, hours, day of week,
day of month, month, and year in selectable BCD or hexadecimal format.
 Switching from counter to calendar mode clears the seconds, minutes, hours,
day-of week, and year counts and sets day-of-month and month counts to 1.
 When RTCBCD = 1, BCD format is selected for the calendar registers.
 The calendar includes a leap year algorithm

(b) Counter Mode:

 Counter mode is selected when RTCMODEx < 11.
 In this mode, a 32-bit counter is provided that is directly accessible by
software.
 Switching from calendar mode to counter mode resets the count value.
 The clock source can be selected from ACLK, SMCLK, or from BTCNT2
clock.
 The counter can be stopped by setting the RTCHOLD bit.
 The following counters are available: RTCNT1, RTCNT2, RTCNT3,
RTCNT4
These Four individual 8-bit counters are cascaded to provide the 32-bit
counter.
  This provides 8-bit, 16-bit, 24-bit, or 32-bit overflow intervals of the counter
clock.
 Each counter is individually accessible and may be read or written to.

Figure 4.2 : Control register of real time clock

BCD format 0→ Hexadecimal format

Bit 7 RTCBCD
select 1 → BCD format

Real-Time Clock 0 → Real-Time Clock is operational

Bit 6 RTCHOLD
hold 1 → The RTC module is stopped
0 → 32-bit counter with ACLK input
Real-Time Clock
01 → 32-bit counter with BTCNT2.Q6
Bit 5-4 RTCMODEx mode and clock
10 → 32-bit counter with SMCLK
source select
11 → Calendar mode with BTCNT2.Q6
Counter Mode: Calendar Mode:
00 : 8-bit overflow 0 : Minute changed
Real-Time Clock 01 : 16-bit overflow 01 : Hour changed
Bits 3-2 RTCEVx
interrupt event 10 : 24-bit overflow 10 : Every day at
11 : 32-bit overflow midnight
11 : Every day at noon
Real-Time Clock 0 Interrupt not enabled
Bit 1 RTCIE
interrupt enable 1 Interrupt enabled

Real-Time Clock 0 No time event occurred

Bit 0 RTCFG
interrupt flag 1 Time event occurred
4.2 MSP430 PWM is the pulse width modulation channel whose pulse width can be varied
to execute various applications such as motor control, audio generation etc.

Assigning proper timing intervals for ON and OFF produces equivalent DC output voltage to
the desired analog value. The fraction of the period in which the signal is high is known as
the duty cycle.

Duty cycle = ON time / Total time period

The analog output of the PWM circuit is proportional to the product of duty cycle and DC
level for ON of the digital wave.

Voutput (PWM) = Duty cycle x ON Voltage level

PWM generation in MSP430:

There are three to five capture/compare blocks inside Timer_A of MSP430 controller. Any
one of the blocks may be used to capture timer data or generate intervals. The compare mode
is used to generate PWM output signals. Each capture/compare block has an output unit,
which is used to generate output PWM signals.

Timer_A is used for generating PWM signal. In Timer_A, the TACCR0 is stored for total
period value of PWM and TACCR1 is used to store ON period of PWM (Duty cycle).

The Timer _A count register (TAR) is in upmode and gets incremented for every clock given
by the selected clock source. OUT1 signal of compare module of Timer_A is configured to
an output pin and the pin value is started with Logic 1.

Compare circuitry compares TAR and TACCR1, when TAR reaches TACCR1 the OUT1
signal is changed to logic 0. The TAR is still counting up and compared with TACCR0.
When it matches, then the OUT1 signal goes back to Logic 1 and TAR is reset to zero.

TACCTL : This register is used to select PWM Modes

The module also sets the compare capture interrupt flag 1 (CCIFG1) upon TAR
matching with TARCC1. This flag can be used for a typical timer purpose and is mostly
not used in PWM generation. In a similar way, Timer_B can also be configured to
PWM generation
4.2.1 PWM OUTPUT
 The idea behind PWM is very simple: The load is switched on and off
periodically so that the average voltage has the desired value.
 The fraction of the time while the load is active is called the duty cycle D.
 The duty cycle is almost always varied by keeping the period constant and
changing the width of the pulses, hence the name of PWM.

Figure 4.3: PWM outputs

 The period of Timer_A is set by TACCR0 in the Up mode.

 TAR counts from 0 up to the value in TACCR0, and returns to 0 to for the next
clock
 The period is therefore TACCR0 + 1

 The flag CCIFG0 is set when TAR counts to TACCR0 and the TAIFG flag is
set when TAR returns to 0, one cycle later.
 The flag CCIFG1 is set when TAR counts to TACCR1, which is 60 here.

 There are two main parameters be chosen for PWM output.

 Now, the average voltage across the output is given by

This means that, by changing the value in TACCR1, we can change the duty cycle.
The above Figure shows that, the Reset/Set output mode (7) is used for active high
loads, called as positive PWM and the Set/Reset mode (3) is used for active low loads,
called as negative PWM.

4.3. MEASUREMENT OF TIME & FREQUENCY IN CAPTURE MODE

The Capture mode is used to take a time stamp of an event, and to note the time at which it
occurred. The timer usually runs in the Continuous mode for captures because this makes it
easy to calculate differences of times when TAR has rolled over between them

(a) Measurement of duration and Time period :

 In most cases the timer clock is either ACLK or SMCLK, whose frequency
is known, and the unknown signal is applied to the capture input.
 To measure the duration of the pulse, we should capture both rising and
falling edges and subtract the captured times.
 To measure the time period of the signal, we might capture only the rising
edges (or falling if preferred) and the difference gives the period directly.

(b) Measurement of frequency :

 The signal is used as the timer clock (TACLK) and the edges of ACLK are
captured whose frequency is known.
 The difference between the captured value gives the number of cycles of the
signal in one cycle of ACLK. This gives the frequency rather than the
period.

Figure 4.4: Two ways in which the capture mode is used to time a signal

Here are a few examples of the use of the Capture mode:

  Many speed sensors produce no. of pulses per revolution. The Capture
mode is used to measure the period between pulses to determine the speed.
 Some sensors encode their outputs as a frequency, length of a pulse, or the
duty cycle of a square wave, the fraction of the time during which the signal
is high.
 The delay between transmission and reception of an ultrasonic pulse is
measured in the range finder application -Ultrasonic Distance Measurement
with the MSP430

4.4. COMPARATOR

 An analog comparator compares the voltages on its two input terminals, V+

and V−. ▪ The comparator output CAOUT is high if V+ > V− and low if
V+ < V−.
 It provides a basic bridge between analog & digital domains and acts as a 1-
bit ADC ▪ The comparator can be switched ON or OFF using control bit
CAON.
 The comparator should be switched off when not in use to reduce current
consumption.
 When the comparator is switched off, the CAOUT is always low.

 Features of Comparator_A+ include:

o Inverting and non-inverting terminal input multiplexer
o Software selectable RC-filter for the comparator output
o Output provided to Timer_A capture input
o Software control of the port input buffer
o Interrupt capability
o Selectable reference voltage generator
o Comparator and reference generator can be powered down in LPMs
 The comparator is used to compare a variable input voltage with a reference.

 The internal reference voltage VCAREF can be chosen from ¼ VCC, ½ VCC or a
nominally fixed voltage from a transistor, Vdiode. This is selected with the
CAREFx bits.

 The voltage reference VCAREF can be applied to either comparator input terminal
according to the CARSEL bit.
 If external signals are applied to both comparator input terminals, the internal
reference generator should be turned OFF to reduce current consumption.
 The non-inverting input V+ can be connected to external signals CA0–CA2 or
left without an external connection. This is selected using bits P2CA4 and
P2CA0.
 Similarly, the inverting input V− can be connected to external signals CA1–
CA7 or left unconnected, according to bits P2CA3 –P2CA1.
 The output of the comparator can be used with or without internal filtering.
When control bit CAF is set, the output is filtered with an on-chip RC-filter to
reduce oscillations in the signal.
 The output is brought to an external pin CAOUT. It is also connected internally
to capture input CCI1B of Timer_A, which allows precise timing without
delays.
 The flag CAIFG is raised on either a rising or falling edge of the comparator
output, selected with the CAIES bit. This can in turn request an interrupt if
CAIE is set. Comparator_A has its own interrupt vector and the flag is cleared
automatically when the interrupt is serviced.
COMPARATOR_A CONTROL REGISTER (CACTL)

Comparator_A This bit exchanges the comparator inputs

Bit 7 CAEX
exchange and inverts the comparator output.

This bit selects terminal for Reference voltage

Comparator_A
Bit 6 CARSEL 0 → VCAREF is applied to the + terminal
reference select
1 → VCAREF is applied to the – terminal

These bits select the reference voltage VCAREF.

0 → Internal reference off.
Comparator_A An external reference can be applied.
Bits 5-4 CAREF
reference 01 → 0.25*VCC
10 → 0.5 *VCC
11 → Diode reference is selected
0→ Comparator OFF
Bit 3 CAON Comparator_A on.
1 → Comparator ON
Comparator_A
0→ Rising edge
Bit 2 CAIES interrupt edge
1 → Falling edge
select
Comparator_A 0→ Disabled
Bit 1 CAIE
interrupt enable 1 → Enabled
The
0→ No interrupt pending
Bit 0 CAIFG Comparator_A
1 → Interrupt pending
interrupt flag

4.5: THE ADC10: SUCCESSIVE APPROXIMATION ADC

 The ADC10 module supports fast, 10-bit analog-to-digital conversions.

 The module implements a 10-bit SAR core, sample select control, reference
generator, and data transfer controller (DTC).
 The DTC allows ADC10 samples to be converted and stored anywhere in
memory without CPU intervention.
 Figure 4.6: Simplified block diagram of ADC10

ADC10 features include:

 Greater than 200 Ksps maximum conversion rate

 Sample-and-hold with programmable sample periods
 Conversion initiation by software or Timer_A
 Software selectable internal or external reference
 Software selectable on-chip reference voltage generation (1.5 V or 2.5 V)
 Up to 12- external input channels
 Conversion channels for internal temperature sensor, VCC, and external
references
 Selectable conversion clock source
 Single-channel, repeated single-channel, sequence, & repeated sequence
conversion modes.
 ADC core and reference voltage can be powered down separately
 Data transfer controller (DTC) for automatic storage of conversion results

10-Bit ADC Core:

The ADC core converts an analog input to its 10-bit digital representation and
stores the result in the ADC10MEM register. Conversion results may be in
straight binary format or 2’s complement format. The conversion formula for
the ADC result when using straight binary format is:
Conversion Clock Selection
The ADC10CLK is used both as the conversion clock and to generate the
sampling period. The ADC10 source clock is selected using the ADC10SSELx
bits and can be divided from 1-8 using the ADC10DIVx bits.

Possible ADC10CLK sources → SMCLK, MCLK, ACLK, internal oscillator

ADC10OSC.

ADC10 Inputs and Multiplexer

The 8-external and 4-internal analog signals are selected for the conversion by
the analog input multiplexer (INCHx). The input multiplexer is a break-before-
make type to reduce input-to-input noise injection resulting from channel
switching

Voltage Reference Generator

The ADC10 module contains a built-in voltage reference with two selectable
voltage levels.

Setting REFON = 1 enables the internal reference.

When REFOUT =0, externally on pin VREF+.

Sample and Conversion Timing

An analog-to-digital conversion is initiated with a rising edge of sample input
signal, selected with the Sample and Hold source (SHSx) bits - ADC10SC,
Timer_A outputs OUT1, OUT2, OUT3.

Conversion Sequence Modes:

CONSEQx Mode Operation

00 Single channel single-conversion Single channel is converted once.
01 Sequence of channels Sequence of channels is converted once
10 Repeat single channel Single channel is converted repeatedly
11 Repeat sequence of channels Sequence of channels is converted
repeatedly

ADC10 Data Transfer Controller

The ADC10 includes a data transfer controller (DTC) to automatically transfer

conversion results from ADC10MEM to other on-chip memory locations.

4.6. DATA TRANSFER USING DMA CONTROLLER

 The direct memory access (DMA) controller transfers data from one address to
another, without CPU intervention, across the entire address range. For example, the
DMA controller can move data from the ADC10 conversion memory to RAM.
  Devices that contain a DMA controller may have up to eight DMA channels
available.
 DMA controller can increase the throughput of peripheral modules. It can also
reduce system power consumption by allowing the CPU to remain in a low-power
mode without having to awaken to move data to or from a peripheral.

DMA Addressing Modes:

 Fixed address to fixed address
 Fixed address to block of addresses
 Block of addresses to fixed address
 Block of addresses to block of addresses

The addressing mode for each DMA channel is independently configurable with the control
bits DMASRCINCRx and DMADSTINCRx. These bits are also used to select the
increment / decrement mode for source and destination addresses, after each transfer.

Transfers may be byte-to-byte, word-to-word, byte-to-word, or word-to-byte. When

transferring word-to-byte, only the lower byte of the source-word transfers. When
transferring byte-to-word, the upper byte of the destination-word is cleared when the
transfer occurs.
 Figure 4.7: DMA controller block diagram

Figure 4.8: DMA addressing modes

DMA Transfer modes:

The DMA controller has 6-transfer modes selected by the DMADTx bits as listed in
the Table. Each channel is individually configurable for its transfer mode. For example,
channel 0 may be configured in single transfer mode, while channel 1 is configured for
burst-block transfer mode, and channel 2 operates in repeated block mode. The transfer
mode is configured independently from the addressing mode. Any addressing mode
can be used with any transfer mode.

Table: DMA transfer modes

DMADT Transfer Mode
x
000 Single transfer
001 Block transfer
010,011 Burst-block transfer
100 Repeated single transfer
101 Repeated block transfer
110,111 Repeated burst-block transfer